JPH064464A - Peripheral equipment access device - Google Patents

Abstract

PURPOSE:To control the peripheral equipment in which address bus width, data bus width, and the number of control lines are different from each other by one peripheral equipment control IC in which the number of pins is small, with regard to the access device of the peripheral equipment connected to a computer system. CONSTITUTION:For instance, in peripheral equipments #x and #y of 103, to a control signal terminal C, an address signal terminal A, and a data signal terminal D of each of them, different signal lines 106 on a peripheral equipment bus 104 are allocated. In such a state, a control signal, internal address data, and internal access data for each peripheral equipment 103 are accessed from a host processor 101 through buffer means 107 corresponding to the signal lines 106 to which data signal lines 105 of a host bus 102 and each terminal C, A and D of each peripheral equipment are connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an access device for peripheral devices connected to a computer system.

[0002]

2. Description of the Related Art When connecting a peripheral device such as an interface circuit, an auxiliary storage device or a printer to a computer system, if the peripheral device is directly connected to the CPU bus, the access speed of the peripheral device is particularly slow. In this case, each time the CPU accesses the peripheral device, C
The PU bus is occupied for that access for a long time, and C
The usage efficiency of the PU bus is poor.

Therefore, conventionally, a peripheral device control IC such as a SCSI controller is connected to a CPU bus, and a bus for peripheral devices is connected to the peripheral device control IC, so that a bus to which peripheral devices are connected and a CPU bus. There is a technology to separate.

As described above, by providing a bus for the peripheral device in addition to the CPU bus and providing a buffer memory in the peripheral device control IC, for example, the peripheral device control IC performs access to the peripheral device on behalf of the CPU. The time taken for the CPU bus to be accessed by the peripheral device can be shortened.

[0005]

Here, when the address bus width, the data bus width, and the number of control lines are different depending on the peripheral device and the control method is also different, conventionally, the peripheral device is different for each peripheral device having different characteristics. Since a control IC must be provided, the scale of hardware is increased, and the system expandability is poor.

In the above case, the peripheral device control IC having the address bus width, the data bus width, and the address bus width, the data bus width, and the number of control lines which are wider than the number of the peripheral devices that can be connected. Although a technique of providing only one bus is conceivable, there is a problem that the bus width cannot be widened in many cases due to the limitation of the number of pins of the IC.

According to the present invention, even if the address bus width, the data bus width, and the number of control lines are different depending on the peripheral device, those peripheral devices can be controlled by one peripheral device control IC having a small number of pins. The purpose is to

[0008]

FIG. 1 is a block diagram of the present invention. The present invention is premised on a peripheral device access device 110 which is connected to a host bus 102 to which a host processor 101 is connected and which houses a peripheral device bus 104 to which a plurality of peripheral devices 103 are connected.

First, the data signal line 1 of the host bus 102.
05 and each signal line 106 (# 1 to #q) of the peripheral device bus 104
It has a plurality of buffer means 107 (# 1 to #q) provided for each of the signal lines 106 for coupling with.

Next, when the host processor 101 is connected to the address signal line 108 of the host bus 102 and each of the plurality of peripheral devices 103 is accessed, the host processor 101 passes through the address signal line 108 of the host bus 102. It has a peripheral device input / output control means 109 which executes the following first, second and third functions based on the address data designated by:

First, the peripheral device input / output control means 109
First, the signal line 106 of the peripheral device bus 104 to which the control signal terminal C of the peripheral device 103 to be accessed is connected.
The buffer means 107 connected to the host processor 101 and the peripheral device 103 to be accessed via the buffer means 107, the data signal line 105 of the host bus 102, and the signal line 106 of the peripheral device bus 104. To send and receive control signals.

Next, the peripheral device input / output control means 109
Second, the signal line 1 of the peripheral device bus 104 to which the address signal terminal A of the peripheral device 103 to be accessed is connected.
Of the peripheral device 103 which controls the buffer means 107 connected to the host processor 101 and is accessed from the data signal line 105 of the host bus 102 to the host processor 101 via the buffer means 107 and the signal line 106 of the peripheral device bus 104. To set the internal address data for

Peripheral device input / output control means 109
Thirdly, it controls the buffer means 107 connected to the signal line 106 of the peripheral device bus 104 to which the data signal terminal D of the accessed peripheral device 103 is connected, and the peripheral device accessed with the host processor 101. Host bus 1 using the buffer means 107 for 103
The internal access data is transferred via the data signal line 105 of No. 02 and the signal line 106 of the peripheral device bus 104.

In the above structure, the plurality of buffer means 107 are divided into a plurality of groups, and the peripheral device input / output control means 109 assigns each of the groups of the buffer means 107 from the host processor 101 to the address signal of the host bus 102. It can be configured to collectively control based on the address data corresponding to each group specified via the line 108.

Here, for example, the host processor 101
Is connected to the signal line 106 of the peripheral device bus 104 to which the control signal terminal C of the peripheral device 103 to be accessed is connected to the peripheral device input / output control means 109 via the address signal line 108 of the host bus 102. Via the data signal line 105 of the host bus 102 while sequentially specifying the control signal data to be supplied to the accessed peripheral device 103 while designating the address data for writing in the buffer means 107 to be accessed. It operates so as to sequentially write to the buffer means 107.

Alternatively, the peripheral in which the control signal terminal C of the peripheral device 103 to be accessed by the host processor 101 is connected to the peripheral device input / output control means 109 via the address signal line 108 of the host bus 102. Buffer means 107 connected to signal line 106 of device bus 104
After designating address data for writing to the peripheral device 103 and sequentially writing control signal data for supplying to the accessed peripheral device 103 to the buffer means 107 via the data signal line 105 of the host bus 102, The control signal data in the buffer means 107 may be sequentially changed in time to generate a control signal to be supplied to the peripheral device 103 to be accessed, and a control signal generating means (not shown) may be further provided. .

[0017]

For example, in the peripheral device 103 of #x, the control signal terminal C is connected to the signal line 106 of #i of the peripheral device bus 104, and the address signal terminal A is #l of the peripheral device bus 104.
Is connected to the signal lines 106 of #m to #m, and the data signal terminal D is connected to the signal lines 106 of #n to #q of the peripheral device bus 104.

On the other hand, in the peripheral device 103 of #y, the control signal terminal C is connected to the signal line 106 of #j of the peripheral device bus 104, and the address signal terminal A is of the peripheral device bus 104.
The data signal terminal D is connected to the signal lines 106 of #l to #o, and the data signal terminal D is connected to the signal lines 106 of #p to #q of the peripheral device bus 104.

For example, a case where the host processor 101 accesses the peripheral device 103 #x will be described. First, the peripheral device input / output control unit 109 controls the address signal line 108 from the host processor 101 to the host bus 102.
The signal line 106 of #i of the peripheral device bus 104 to which the control signal terminal C of the peripheral device 103 of #x is connected based on the address data for access to the control signal specified via.
The #i buffer unit 107 connected to the #i is controlled, and a control signal designated by the host processor 101 via the data signal line 105 of the host bus 102 is written in the #i buffer unit 107.

Next, the peripheral device input / output control means 109
It controls the buffer means 107 of #l to #m connected to the signal lines 106 of #l to #m of the peripheral device bus 104 to which the address signal terminal A of the peripheral device 103 of #i is connected, and controls the host processor 101. On the other hand, for the peripheral device 103 of #x from the data signal line 105 of the host bus 102 via the buffer means 107 of #l to #m and the signal line 106 of #l to #m of the peripheral device bus 104. Set the internal address data.

Peripheral device input / output control means 109
Controls the #n to #q buffer means 107 connected to the #n to #q signal lines 106 of the peripheral device bus 104 to which the data signal terminal D of the #x peripheral device 103 is connected, and the host processor 101 and the peripheral device 103 of #x.
Internal access data is transmitted and received via the data signal line 105 of the host bus 102 and the signal lines 106 of #n to #q of the peripheral device bus 104 using the #q buffer means 107.

In this case, for example, the host processor 10
1 designates the peripheral device input / output control means 109 via the address signal line 108 of the host bus 102 to the address data for writing to the buffer means 107 of #i, and the peripheral device 103 of #x. To the host bus 102.
It operates so as to sequentially write the data in the #i buffer means 107 via the data signal line 105.

On the other hand, for example, the host processor 101
A case of accessing the peripheral device 103 of #y will be described. First, the peripheral device input / output control unit 109 controls the control signal terminal of the peripheral device 103 of #y based on the address data for control signal access designated from the host processor 101 via the address signal line 108 of the host bus 102. Controls the #j buffer means 107 connected to the #j signal line 106 of the peripheral device bus 104 to which C is connected,
For example, the control signal designated from the host processor 101 via the data signal line 105 of the host bus 102 is changed to #j
To the buffer means 107.

Next, the peripheral device input / output control means 109
The host processor 101 controls the buffer means 107 of #l to #o connected to the signal lines 106 of #l to #o of the peripheral device bus 104 to which the address signal terminal A of the peripheral device 103 of #j is connected. On the other hand, for the peripheral device 103 of #y from the data signal line 105 of the host bus 102 through the buffer means 107 of #l to #o and the signal line 106 of #l to #o of the peripheral device bus 104. Set the internal address data.

Then, the peripheral device input / output control means 109
Controls the #p to #q buffer means 107 connected to the #p to #q signal lines 106 of the peripheral device bus 104 to which the data signal terminal D of the #y peripheral device 103 is connected, and controls the host processor. 101 to the peripheral device 103 of #y
Internal access data is transmitted and received via the data signal line 105 of the host bus 102 and the signal lines 106 of #p to #q of the peripheral device bus 104 using the #q buffer means 107.

In this case, for example, the host processor 10
1 designates the address data for writing to the buffer means 107 of #j to the peripheral device input / output control means 109 via the address signal line 108 of the host bus 102, and the peripheral device 103 of #y. To the host bus 102.
It operates so as to sequentially write to the #j buffer means 107 via the data signal line 105 of.

[0027]

Embodiments of the present invention will now be described in detail with reference to the drawings. In the following embodiment, the peripheral device 3 in the message communication device 103 of FIG.
Peripheral device bus 318 to which 24 (# 1, # 2, ...) Is connected
The configuration of the I / O controller 315 that houses the I / O controller 315 is most relevant to the present invention. <Overall Configuration of Embodiment of the Present Invention> FIG. 2 is a configuration diagram of a network to which the embodiment of the present invention is applied.

A plurality of nodes 202 (see FIG. 2) are included in a network 201 which is composed mainly of an optical fiber ring 206.
Are indicated by numbers such as # 000, # ***, # %%%, etc.)
Are connected.

At node 202, processor bus 2
A plurality of processors 204 are connected to 05, and the processor bus 205 is accommodated in the message communication device 203. The message communication device 203 includes the processor bus 20.
5, the processor 204 processes the message data transmitted or received, and also processes the frame in which the message data input to or output from the optical fiber ring 206 is stored. This message communication device 203
The configuration of the buses within is most relevant to the present invention.

Next, FIG. 3 is a configuration diagram of the message communication device 203 in the node 202 of FIG. 2 in the embodiment of the present invention. The real memory 307 functions as a communication buffer that temporarily holds message data.

The control memory 308, for each virtual page address in the virtual storage space used for message communication, if the virtual page address is allocated to the real page address in the real memory 307, the real page. The address and data indicating the page state (communication state) of the virtual page address are stored.

The processor bus interface 312 is
2 is connected to the external bus 301 and accommodates the message data and the like input from the processor 204 of FIG. 2 via the processor bus 205 via the external bus 301 and the virtual memory controller 309. 307 and vice versa, the message data and the like input from the real memory 307 via the virtual memory controller 309 and the external bus 301 are output to the processor 204 via the processor bus 205.

Further, the processor bus interface 31
2 exchanges communication control data with the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

Although not shown in FIG. 2, two processor buses 205 are provided for each node in FIG. Therefore, the processor bus interface 312 also
Two # 0 and # 1 are provided corresponding to each processor bus 205. Then, the # 0 processor bus interface 312 uses the control line 319 to perform contention control when the # 0 and # 1 processor bus interfaces 312 access the external bus 301. Further, the # 0 processor bus interface 312 is connected to the control lines 321 and 322.
Via a CPU bus arbiter 314 and I /
While exchanging control data regarding bus use with the O controller 315, competition control of the external bus 301 is performed, and opening / closing control of the bus coupling unit 311 is performed via the control line 320 when necessary.

The network control circuit 310 receives the CPU bus 302, I from the CPU 313 at the time of frame transmission.
A control memory 308 via a control memory access bus 306 based on a transmission command input via the I / O controller 315 and the network command / result bus 303.
While accessing, read message data to be transmitted from the real memory 307 via the virtual memory controller 309 and the network data transmission bus 305, construct a transmission frame including the message data, and send it to the optical fiber ring 206. The transmission result is sent to the network command / result bus 303 and the I / O controller 31.
5 and the CPU 313 via the CPU bus 302.

Further, the network control circuit 310 receives the frame from the optical fiber ring 206, and the control memory 308 via the control memory access bus 306.
Access the received frame to another node 2
Relay to 02. Alternatively, the message data in the received frame is extracted and the network data reception bus 30
4 to the real memory 307 via the virtual memory controller 309, and the reception result is notified to the CPU 313 via the network command / result bus 303, the I / O controller 315, and the CPU bus 302.

The CPU 313 is connected to the CPU bus 302, and is connected to the CPU bus 302 at the start of operation.
It operates according to a control program written from the PROM 316 to the program RAM 317 connected to the CPU bus 302.

The CPU 313 has a CPU bus 302,
Communication control data is exchanged with the processor bus interface 312 via the bus coupling unit 311 and the external bus 301.

Further, the CPU 313, when transmitting a frame, uses the CPU bus 302, the I / O controller 315,
And output a send command to the network control circuit 310 via the network command / result bus 303, and thereafter
From the network control circuit 310, a network command /
Result bus 303, I / O controller 315, and CP
The transmission result notification is received via the U bus 302. Conversely, the CPU 313 receives from the network control circuit 310 the network command / result bus 303, the I / O controller 315, and the CPU bus 3 when receiving a frame.
A reception result notification is received via 02.

Further, the CPU 313 has a CPU bus 302.
The page state data (data indicating the communication state) of each virtual page address in the control memory 308 is accessed via the CPU memory 302 and the virtual page address of each virtual page address in the control memory 308 is accessed via the CPU bus 302 and the virtual memory controller 309. The page address data and the real memory 307 are accessed.

The I / O controller 315 is connected to the CPU bus 302 and houses a peripheral device bus 318 to which external # 0 and # 1 peripheral devices 324 are connected. This accommodation configuration is most relevant to the present invention.

Further, the I / O controller 315, as described above, uses the CPU bus 302 and the network instruction /
The transmission command, the transmission result notification, or the reception result notification exchanged between the CPU 313 and the network control circuit 310 is relayed via the result bus 303.

Further, the I / O controller 315 is a CP
The address that U313 uses to access the external bus 301 is C
When specified for the PU bus 302, the control line 322
To the processor bus interface 312 of # 0 via
Outputs an external bus access request.

The CPU bus arbiter 314 is a C bus from the processor bus interface 312 via the control line 321.
When the PU bus access request (bus grant request) is received, the bus use request (bus grant request) is output to the CPU 313 via the control line 323, and the CPU 3
13 receives a bus use permission (bus grant acknowledge) from the control line 323 through the control line 323, and based on that, the CPU
Bus access permission (bus grant acknowledge) is sent via the control line 321 to the # 0 processor bus interface 3
Return to 12.

The virtual memory controller 309 is
Processor bus interface 312 and real memory 307
Data exchanged with the external bus 301 via the external bus 301, C
Data transmitted and received between the PU 313 and the real memory 307 or the control memory 308 via the CPU bus 302, and between the network control circuit 310 and the real memory 307 via the network data reception bus 304 or the network data transmission bus 305. The switching control and the contention control of the exchanged data are performed.

The operation of the embodiment of the present invention having the above configuration will be described. <Overall operation of inter-processor communication> Now, in FIG. 2 and FIG. 3, for example, message data is sent from one processor 204 in the node 202 of # 000 to another processor 204 in the node 202 of # ***. The overall operation when transmitting will be described.

In this case, the message data transmitted from one processor 204 in the node # 000 is the message communication device 203 in that node (hereinafter, the message communication device 203 in # 000) via the processor bus 205. Call)) to the real memory 307,
It is sent to the real memory 307 of the message communication device 203 in the node 202 of # *** (hereinafter referred to as the message communication device 203 of # ***), and then the destination from the real memory 307 via the processor bus 205. The processor 204
Transferred to. That is, the real memory 307 of each message communication device 203 functions as a communication buffer. Communication Method Between Message Communication Devices 203 Here, a special method called a network virtual storage method is applied to communication of message data between the message communication devices 203.

First, in the entire network 201 of FIG.
A virtual memory space is defined. This virtual storage space is divided into a plurality of virtual pages, and message data is communicated via these virtual pages. For example, the virtual storage space is divided into virtual page addresses of 0000 to FFFF pages (hexadecimal number). One virtual page has a fixed length (for example, 8 kilobyte length) data length that can sufficiently accommodate a packet that is one unit of message data. Unless otherwise specified, the virtual page address and the dictated real page address are represented by hexadecimal numbers.

Next, the message communication device 203 of each node 202 connected to the network 201 is allocated every predetermined number of pages of this virtual storage space, for example, every 16 pages. For example, the message communication device 203 of the # 000th node 202 is allocated to the 0000 to 000F page, the message communication device 203 of the # 001th node 202 is allocated to the 0010 to 001F page, and so on. ** 0-*** F page and %%% 0-%%% F page (3 digit *
And% are arbitrary numbers in hexadecimal numbers 0 to F), the message communication device 203 of each node 202 of the # *** th and # %%% th is assigned.

Therefore, in the above example, the network 20
1, a maximum of 3096 message communication devices 203 from # 000 to #FFF can be connected. On the other hand, the real memory 307 in each message communication device 203 is divided into a plurality of real pages each having the same data length as the above-mentioned virtual page. The page capacity of the real memory 307 may be much smaller than the page capacity of the virtual storage space, and may be, for example, about 64 to 256 pages.

Next, in the control memory 308 of each message communication device 203, as shown in FIG. 4, control data for all virtual page addresses are stored. As shown in FIG. 4, the control data of each virtual page address indicates the real page address data of the real memory 307 in the own message communication device 203 associated with the virtual page address and the communication state of the virtual page address. And page status data shown.

Then, as an initial state, each node 202
In the control memory 308 of the message communication device 203 in the internal message communication device 203, the virtual page address assigned to the node 202 is set to an arbitrary empty page in the real memory 307 of the message communication device 203 by the network reception control function of the CPU 313. The real page address of the network receiving buffer provided in the above and the receiving buffer allocation state VP as the page state are respectively written in advance. The network reception control function is a CP
This is realized by the U313 executing the control program stored in the program RAM 317.

For example, the # 000 message communication device 203
In the control memory 308 of the own message communication device 2
As shown in FIG. 4, each virtual page address of 0000,0001, ..., 000F pages assigned to the 03 is assigned to each real page of s, q, ..., p in the real memory 307. The address has been written and the page status VP indicating the receive buffer allocation status has been written.

Further, in the control memory 308 of the message communication device 203 of # ***, the own message communication device 20
As shown in FIG. 4, each virtual page address of **** 0, *** 1, ..., *** F page assigned to
The page status indicating the receive buffer allocation status in which each real page address of v, u, ..., T in the real memory 307 is written.
VP is written.

Similarly, # %%% message communication device 203
In the control memory 308 of the own message communication device 2
, %%% 0, %%% 1, ..., %%% F, the virtual page addresses of the pages of the real memory 307 include y, w, and , X are written, and the page state VP indicating the receive buffer allocation state is written.

Now, by the transfer operation described later, for example, # 000
Message data is transferred from one processor 204 in the node # 000 202 to a network transmission buffer (to be described later) whose real page address is r in the real memory 307 of the message communication device 203 of FIG. To do.

The network transmission control function of the CPU 313 analyzes the destination address part in the header of the message data stored in the network transmission buffer in the real memory 307 via the CPU bus 302 and the virtual memory controller 309. By doing so, the virtual page address assigned to the node 202 in which the processor 204 corresponding to the destination address is accommodated is determined as the one whose page state is the buffer unallocated state NA. In the example of FIG. 4, for example, the virtual page address *** 2 is determined. The network transmission control function is realized by the CPU 313 executing the control program stored in the program RAM 317.

Next, the network transmission control function of the CPU 313 writes the real page address of the network transmission buffer in which the above-mentioned message data is stored in the determined virtual page address in the control memory 308, and the page is written. Change the status from the buffer unallocated status NA to the transmission status SD. In the example of FIG. 4, the real page address r and the transmission state SD are set to the virtual page address *** 2, for example.

The network transmission control function of the CPU 313 is the transmission F function in the I / O controller 315.
The virtual page address and the transfer length of the message data described above are written to the IFO via the CPU bus 302 together with the transmission command.

When the network control circuit 310 reads the above-mentioned transmission command or the like from the transmission FIFO in the I / O controller 315 via the network command / result bus 303, the virtual page added to the transmission command. An address is designated to the control memory 308 via the control memory access bus 306, the real page address set in the above-mentioned virtual page address is read from the control memory 308, and set in the DMA transfer register in the virtual memory controller 309. To do.

Then, the network control circuit 310 is
The page data of the real page address in the real memory 307 including the message data to be transmitted to the virtual memory controller 309 is transferred to the network control circuit 310 via the network data transmission bus 305.
To DMA transfer.

The network control circuit 310 extracts message data corresponding to the transfer length of the message data added to the send command from the above-mentioned page data, and the message data and the virtual page address added to the send command. And a transmission frame including the transfer length of the message data and generating the transmission frame.
Send to 6. The token ring network method is adopted as the frame transmission method of the optical fiber ring 206, and the network control circuit 310 can send a transmission frame only when a free token circulating on the optical fiber ring 206 is acquired. .

In the example of FIG. 4, the transmission frame including the virtual page address *** 2 and the message data stored in the real page address r in the real memory 307 from the message communication device 203 of # 000 is It is sent to the optical fiber ring 206.

The above-mentioned transmission frame is transmitted to another node 202 (see FIG. 2) connected to the optical fiber ring 206.
Are sequentially transferred to. When the network control circuit 310 of the message communication device 203 in each node 202 fetches the transmission frame from the optical fiber ring 206, the page state corresponding to the virtual page address stored in the transmission frame is set to the control memory access bus 306. Read from the control memory 308 via the, and whether the page status is the receive buffer allocation status VP, that is, whether the virtual page address is assigned to the message communication device 203 of the own node 202, or the page It is determined whether or not the state is the transmission state SD, that is, whether or not the transmission frame is transmitted by the own network control circuit 310.

When the network control circuit 310 determines that the page state of the virtual page address stored in the transmission frame is the reception buffer allocation state VP,
The message data stored in the transmission frame is taken into the real memory 307 as follows.

That is, the network control circuit 310 first designates the virtual page address stored in the transmission frame to the control memory 308 via the control memory access bus 306, and the control memory 308 changes the virtual page address to the above-mentioned virtual page address. The set real page address is read out and set in the DMA transfer register in the virtual memory controller 309. Then, the network control circuit 310 causes the virtual memory controller 309 to
The message data included in the transmission frame is DMA-transferred to the above-mentioned real page address in the real memory 307 via the network data reception bus 304.

After that, the network control circuit 310
The virtual page address stored in the transmission frame is
Control memory 30 via control memory access bus 306
8 is specified, and the page status of the virtual page address is changed from the reception buffer allocation status VP to the reception completion status RD.
Further, the network control circuit 310 causes the reception FIFO in the I / O controller 315 to execute a network command /
Through the result bus 303, the virtual page address extracted from the transmission frame and the transfer length of the message data are written together with the result code indicating the success or failure of the reception.

Finally, the network control circuit 310
After writing the reception success notification in the response area in the above-mentioned transmission frame received from the optical fiber ring 206, the transmission frame is sent to the optical fiber ring 206 again.

For example, in the example of FIG. 4, the network control circuit 310 of the message communication device 203 of # *** is # 000.
The message stored in the transmission frame is determined by determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 is the reception buffer allocation state VP. The data is transferred to the real memory 30 having the real page address u set to the virtual page address *** 2 of the control memory 308.
After fetching in the network reception buffer in 7, the page state of the virtual page address *** 2 of the control memory 308 is changed from the reception buffer allocation state VP to the reception completion state RD.

The above notification of the reception result is received by the CPU 313 via the CPU bus 302. That is, CP
The U313 network reception control function uses the reception F in the I / O controller 315 via the CPU bus 302.
When the above reception result notification is received from the IFO and if the result code is successful in reception, the virtual page address which is a part of the reception result notification is designated to the control memory 308 via the CPU bus 302, and the page state Read the real page address.

If the page state described above is the reception completion state RD, the network reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. Separates the real page specified by the page address from the network receive buffer and connects it to the processor send-wait buffer queue.

After that, the network reception control function of the CPU 313 controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect an arbitrary empty page to the network reception buffer, and further Control memory 3 via CPU bus 302 with a virtual page address that is part of the reception result notification
08 is accessed, and the real page address of the above-mentioned empty page and the reception buffer allocation state VP as the page state are written to the virtual page address.

Thereafter, the processing for the processor transmission waiting buffer queue in the real memory 307 is performed by the CPU 31.
3 from the network reception control function to the processor transmission control function described later.

On the other hand, the network control circuit 310 reads the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, and as a result, the page state is neither the reception buffer allocation state VP nor the transmission state SD. If it is determined that the transmission frame is transmitted, the transmission frame is directly transmitted to the optical fiber ring 206.

For example, in the example of FIG. 4, the network control circuit 310 of the # %%% message communication device 203 is
By determining that the page state on the control memory 308 of the virtual page address *** 2 stored in the transmission frame from the node 202 of the node 202 is neither the reception buffer allocation state VP nor the transmission state SD, the transmission frame is left as it is. It is sent to the optical fiber ring 206.

Optical fiber ring 206 as described above
The transmission frame sequentially transferred above returns to the network control circuit 310 of the message communication device 203 in the node 202 which is the transmission source.

The source network control circuit 310 is
As a result of reading out the page state corresponding to the virtual page address stored in the transmission frame from the control memory 308, by determining that it is the transmission state SD,
It is determined that the transmission frame is the transmission frame transmitted by the own network control circuit 310.

In this case, the network control circuit 310
After confirming that the reception success notification is written in the response area of the received transmission frame, the control memory 308 of the control memory 308 corresponding to the virtual page address stored in the transmission frame is transmitted via the control memory access bus 306. The page state is changed from the transmission state SD to the transmission completion state SC.

Then, the network control circuit 310
The virtual page address extracted from the transmission frame is written to the reception FIFO in the I / O controller 315 via the network command / result bus 303 together with the result code indicating the success or failure of the transmission.

The above-mentioned transmission result notification is received by the CPU 313 via the CPU bus 302. That is, CP
The network transmission control function of the U313 is performed by the reception F in the I / O controller 315 via the CPU bus 302.
When the above result notification is received from the IFO, if the result code is successful, the virtual page address that is a part of the result notification is specified in the control memory 308 via the CPU bus 302, and the page status is changed. Read the real page address.

If the above-mentioned page state is the transmission completion state SC, the network transmission control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to make the above-mentioned real state. The real page specified by the page address is separated from the network send buffer and used as a free page.

After that, the network transmission control function of the CPU 313 controls the control memory 3 via the CPU bus 302 with the virtual page address which is a part of the above-mentioned transmission result notification.
08 is accessed, and the buffer unallocated state NA is written as the page state of the virtual page address.

As described above, the network 201 (see FIG.
In the above, one virtual storage space is defined, and a virtual page having a fixed data length that constitutes this space is assigned to each message communication device 203. Communication of message data between the message communication devices 203 is performed using this virtual page. As a result, blocking control and sequence control that are performed in normal packet communication are not required.

When the network control circuit 310 of the message communication device 203 in each node 202 on the optical fiber ring 206 receives the transmission frame, the virtual page address stored in the transmission frame causes the network control circuit 310 on the control memory 308. By accessing the page state, the received transmission frame can be processed at high speed.

In addition, a response area is provided in the transmission frame transferred on the optical fiber ring 206, and the network control circuit 310 of the message communication device 203 in the receiving side node 202 transmits the reception result of the transmission frame. It writes in the response area of the frame and sends it out again to the optical fiber ring 206. Therefore, by the time this transmission frame is transferred on the optical fiber ring 206 and returned to the transmission source, the message data transmission processing is completed, and the response from the reception side to the transmission source is sent using another frame. No need to notify. As a result, the communication protocol can be simplified and high-speed response processing can be performed.

Further, communication of message data between the message communication devices 203 is performed using the real memory 307 while the network control circuit 310 in the message communication device 203 accesses the control memory 308, and the communication with the processor 204 and the message communication device 203 is performed. The communication of message data between 203 is performed by the message communication device 2 as described later.
The processor bus interface 312 in 03 uses the real memory 307 independently of the operation of the network control circuit 310 described above. Further, the correspondence between the message data stored in the real page address in the real memory 307 and the virtual page address in the virtual storage space is as described below, in which the CPU 313 sends the destination address in the header added to the message data. Based on. Therefore, between the processor 204 and the message communication device 203,
Message communication device 203 and message communication device 203
It is possible to efficiently perform the processing between them at high speed. From the processor 204 at the sender to the message communication device
Operation of Transferring Message Data to Device 203 Next, from one processor 204 in the source node 202 (# 000 node 202 in the example of FIG. 4) to the real memory 307 of the message communication device 203 in that node, The operation when the message data is transferred will be described.

First, the processor reception control function of the CPU 313 accesses the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to connect the processor reception buffer queue to the free buffer queue in the real memory 307. Connect the free buffer that is being used. The processor reception control function is a function realized by the CPU 313 executing the control program stored in the program RAM 317.

The processor reception control function of the CPU 313 activates, for example, the # 0 processor bus interface 312 via the CPU bus 302, the bus coupling unit 311, and the external bus 301. The start address of the above-mentioned processor receive buffer queue is notified.

The processor bus interface 312 is
The message data transferred from the processor 204 via the processor bus 205 is received, and the received message data described above is updated while sequentially updating the buffer address with the start address as the reception start address.
External bus 301 and virtual memory controller 30
9 is sequentially transferred to an empty buffer connected to the processor reception buffer queue in the real memory 307.

The processor bus interface 312 is
When there is no free buffer connected to the processor reception buffer queue, the free buffer is automatically stopped, and the fact is notified to the CPU 313 via the external bus 301, the bus coupling unit 311, and the CPU bus 302.

The processor reception control function of the CPU 313 first controls the real memory 307 via the CPU bus 302 and the virtual memory controller 309 to separate the received buffer from the processor reception buffer queue and transmit it to the network. Connect to a buffer. Thereafter, the processing for the network transmission buffer in the real memory 307 is transferred from the processor reception control function of the CPU 313 to the network transmission control function described above, and the transmission source of the transmission source is transmitted in accordance with the communication method between the message communication devices 203 described above. From the real memory 307 in the message communication device 203 of the node 202 (# 000 message communication device 203 in the example of FIG. 4), the message communication device 203 of the node 202 (in the example of FIG. 4) in which the destination processor 204 is accommodated # *** message communication device 20
The message data transfer operation to the real memory 307 in 3) is executed. From the message communication device 203 on the receiving side to the process
Transfer Operation of Message Data to Server 204 Next, the real memory 3 of the message communication device 203 in the receiving node 202 (# 202 node 202 in the example of FIG. 4).
07 to one processor 204 in that node 202
The operation when the message data is transferred will be described below.

When the network control circuit 310 succeeds in receiving the transmission frame, as described above, the CPU 313.
The network reception control function of (1) connects the received message data to the processor transmission waiting buffer queue in the real memory 307.

On the other hand, the processor transmission control function of the CPU 313 includes the CPU bus 302 and the bus coupling unit 31.
For example, the # 0 processor bus interface 312 is activated via 1 and the external bus 301, and the interface 312 is notified of the start address of the above-mentioned processor transmission waiting buffer queue.

The processor bus interface 312 is
While sequentially updating the buffer address with the start address as the transmission start address, the real memory 30 is accessed via the external bus 301 and the virtual memory controller 309.
7 sequentially reads the message data stored in the buffer connected to the processor transmission waiting buffer queue, analyzes the destination address part in the header of the message data, and transfers the message data to the processor bus 205. Via the destination processor 204. <First embodiment of interface for peripheral device of I / O controller> Next, I / O controller 3 of FIG.
FIG. 5 shows the configuration of the first embodiment of the interface portion for 15 peripheral devices 324. The structure of this part is most relevant to the present invention. In the configuration I / O controller 315 of the first embodiment , first, the input / output control circuit 501 accommodates the control line of the CPU bus 302 and the address bus.

The address decoder 502 decodes the address designated by the input / output control circuit 501 and the address bus of the CPU bus 302. The control circuit 503 is a peripheral device 3.
Generate control signals for 24.

1-bit D flip-flop (DF / F) C
_i (i = 1 to m) holds the control signal for the peripheral device 324. The 1-bit DF / F D _j (j = 1 to n) is a direction control signal D _Rj (j = 1 to n) for bidirectional buffers B _j1 and B _j2 (j = 1 to n) described later.
Hold ~ n).

1-bit DF / F R _j (j = 1 to n) is used by the CPU 3
13 (see FIG. 3) holds the address data or write data for the peripheral device 324 set via the data bus of the CPU bus 302.

The 1-bit latch L _j (j = 1 to n) holds the read data set by the peripheral device 324. The bidirectional buffers IB _j and OB _j (j = 1 to n) are both DF /
Based on the direction control signal D _Rj (j = 1 to n) from F D _j (j = 1 to n), DF / F R _j (j = 1 to n) or latch L _j (j = 1 to n) Data bus of CPU bus 302 and peripheral device bus 3
Connect to 18. As a result, whether the access from the CPU 313 is a write access having a direction from the CPU 313 to the peripheral device 324, or the access from the peripheral device 324 to the CPU
It is determined whether the read access has a direction to 313.

In the peripheral device 324 of # 0 connected to the peripheral device bus 318, for example, the control signal input terminal C is I
It is connected to the / O controller signal line connected to the DF / F C ₁ in 315. The address input terminal A is connected to the signal line group connected to the bidirectional buffer OB ₁ ~OB _p. Further, the data input / output terminal D is connected to a signal line group connected to the bidirectional buffers OB _{p + 1 to} OB _n .

On the other hand, # 1 connected to the peripheral device bus 318
In the peripheral device 324 of the control signal input terminal C
It is connected to a signal line connected to the DF / F C ₂ in the I / O controller 315. Also, address input terminal A
Are connected to a signal line group connected to the bidirectional buffers OB _{1 to} OB _q . Further, the data input / output terminal D is connected to a signal line group connected to the bidirectional buffers OB _{q + 1 to} OB _n .

As described above, in the configuration of FIG. 5, the peripheral devices 324 of # 0 and # 1 connected to the peripheral device bus 318 accommodated in the I / O controller 315 have different address bus widths and data bus widths. , And different control lines are used.

That is, on one peripheral device bus 318, the address bus width, the data bus width, and the number / position of control lines can be appropriately changed according to the type of the peripheral device 324. Description of Division Mode of Peripheral Bus 318 Now, DF / F C _i , DF / F D _j , and DF / F R _j and latch L _j (i = 1 to m, j = 1 to n) are grouped into a plurality of groups. The address is assigned to each group.

For example, in division 1 shown in FIG. 6, DF / F
An address ADRS _C1 is assigned to the group consisting of C _i (i = 1 to _m ) and DF / F D _j (j = 1 to n), and DF / F R _{1 to} R _p.
Alternatively, the address AD is added to the group consisting of the latches L _{1 to} L _p .
RS _A1 is assigned and DF / FR _{p + 1 to} R _n or latch L
_The address ADRS _D1 is assigned to the group consisting of _{p + 1 to} L _n .

In division 2, ADRS _C1 is allocated in the same manner as in division 1, and DF / F R _{1 to} R _q or latch L is assigned.
_The address ADRS _A2 is assigned to the group of _{1 to} L _q, and the address ADRS _D2 is assigned to the group of DF / F R _{q + 1 to} R _n or the latches L _{q + 1 to} L _n .

Furthermore, in division 3, DF / FC _i (i = 1 to m)
DF / F D _j (j = 1 to n) and DF / F R _{1 to} R _p or latch L ₁
The address ADRS _A3 is assigned to the group consisting of ˜L _p, and the assignment of ADRS _D1 is the same as in the case of division 1. Data is written from the CPU 313 to the peripheral device 324 of # 0.
In the case where the CPU 313 writes the data by designating an address to the peripheral device 324 of # 0, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address ADRS _C1 is designated to the second address bus, and the control data for the data write access to the peripheral device 324 of # 0 is set to the data bus of the CPU bus 302. Address decoder 5 in I / O controller 315
02 asserts the F / F control signals A _Ci (i = 1 to m) and A _Dj (j = 1 to n) based on the decoding result of the address ADRS _C1 on the address bus. As a result, DF / F C _i (i = 1 to m) and DF / F
The above-mentioned control data is written in D _j (j = 1 to n). Specifically, the signal indicating the negated state to the DF / F C ₁ is written, the _{DF / FD j (j = 1~n} ), data indicating the bus data direction towards the peripheral device 324 side from the CPU313 side Written.

Then, as a result of the above write operation, DF / F
Based on the direction control signals D _{R1 to} D _Rn output from D _j (j = 1 to n), the bidirectional buffers IB _{1 to} IB _n , OB _{1 to} O.
The bus data direction in B _n is set to the direction from the CPU 313 side to the peripheral device 324 side.

Next, the CPU 313 determines that the CPU bus 302
The address ADRS _A1 is specified on the address bus of the above, and the internal address data specified for the peripheral device 324 of # 0 is set on the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the F / F control signals A _{R1 to} A _Rp based on the decoding result of the address ADRS _A1 on the address bus. As a result, DF / F R ₁
The above-mentioned internal address data is written in to R _p .

Further, the CPU 313 is connected to the CPU bus 302.
The address ADRS _D1 is designated to the address bus of the above, and the internal write data to be written to the peripheral device 324 of # 0 is set to the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the F / F control signals A _{Rp to} A _Rn based on the result of decoding the address ADRS _D1 on the address bus. As a result, DF / FD
_The above-mentioned internal write data is written in _{Rp + 1 to} D _Rn .

After that, the CPU 313 determines that the CPU bus 30
While specifying the address ADRS _C1 to the 2nd address bus, C
In the data bus of the PU bus 302, the output state of DF / FC ₁ changes from the negated state to the asserted state, and thereafter,
Control data for returning to the negated state again is sequentially specified based on a predetermined timing. DF / F D _j (j =
The control data is designated so that the data instructing the bus data direction from the CPU 313 side to the peripheral device 324 side is written in (1 to n) every time.

As a result, the peripheral device 324 of # 0 is DF / F
At the timing when the control signal input from C ₁ to the control signal input terminal C is asserted, the bidirectional buffer OB
An internal address data is output from the DF / F R ₁ ~R _p to the signal line on peripheral bus 318 which is connected to the _{1 ~OB p} uptake from the address input terminal A, a bidirectional buffer OB _{p ~OB n} The internal write data output from DF / F R _{p + 1 to} R _n is taken in from the data input / output terminal D to the signal line on the connected peripheral device bus 318. Data is read from the peripheral device 324 of # 0 to the CPU 313.
Then, when the CPU 313 specifies an address to the peripheral device 324 of # 0 to read data, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address ADRS _C1 is designated for the second address bus, and control data for data read access to the peripheral device 324 # 0 is set on the data bus of the CPU bus 302. Address decoder 5 in I / O controller 315
02 asserts the F / F control signals A _Ci (i = 1 to m) and A _Dj (j = 1 to n) based on the decoding result of the address ADRS _C1 on the address bus. As a result, DF / F C _i (i = 1 to m) and DF / F
The above-mentioned control data is written in D _j (j = 1 to n). Specifically, the signal indicating the negated state to the DF / F C ₁ is written, the data indicating the bus data direction from CPU313 side DF / FD ₁ ~D _p to the peripheral device 324 side is written DF / Data designating the bus data direction from the peripheral device 324 side to the CPU 313 side is written in F D _{p + 1 to} D _n .

Then, as a result of the above write operation, DF / F
Based on the direction control signals D _{R1 to} D _Rn output from D _j (j = 1 to n), the bidirectional buffers IB _{1 to} IB _p , OB _{1 to} O.
The bus data direction in B _p is set to the direction from the CPU 313 side to the peripheral device 324 side, and the bus data direction in the bidirectional buffers IB _{p + 1 to} IB _n and OB _{p + 1 to} OB _n is set from the peripheral device 324 side to the CPU 313. It is set to the side.

Next, the CPU 313 uses the CPU bus 302.
The address ADRS _A1 is specified on the address bus of the above, and the internal address data specified for the peripheral device 324 of # 0 is set on the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the F / F control signals A _{R1 to} A _Rp based on the decoding result of the address ADRS _A1 on the address bus. As a result, DF / F R ₁
The above-mentioned internal address data is written in to R _p .

After that, the CPU 313 determines that the CPU bus 30
While specifying the address ADRS _C1 to the 2nd address bus, C
In the data bus of the PU bus 302, the output state of DF / FC ₁ changes from the negated state to the asserted state, and thereafter,
Control data for returning to the negated state again is sequentially designated at an appropriate timing. In addition, DF / FD _1-
Data for instructing the bus data direction from the CPU 313 side to the peripheral device 324 side is written in D _p every time, and D-
For F / F D _{p + 1 to} D _n , CPU 31 from the peripheral device 324 side
The control data is designated so that the data designating the bus data direction toward the 3 side is written every time.

As a result, the peripheral device 324 of # 0 is DF / F
At the timing when the control signal input from C ₁ to the control signal input terminal C is in the asserted state, the signal lines on the peripheral device bus 318 connected to OB _{1 to} OB _p are connected to DF / FR ₁ to
The internal address data output from R _p is fetched from the address input terminal A, and the bidirectional buffers OB _{p to} OB
_The internal read data is output from the data input / output terminal D onto the signal line on the peripheral device bus 318 connected to _n .

This internal read data is latched by the latches L _{p to} L _n via the bidirectional buffers OB _{p to} OB _n and then transferred to the data bus of the CPU bus 302 via the bidirectional buffers IB _{p to} IB _n. It is output and processed by the CPU 313. When the CPU 313 accesses the peripheral device 324 of # 1 As described above, when the CPU 313 accesses the peripheral device 324 of # 0, the addresses ADRS _A1 and ADRS _D1 are designated, so that the internal address data is DF. / FR ₁ ~
The internal write / read data is processed using R _p
It is processed using DF / F R _{p + 1 to} R _n or latches L _{p + 1 to} L _n .

On the other hand, the basic operations when data is written from the CPU 313 to the peripheral device 324 of # 1 and when data is read from the peripheral device 324 of # 1 to the CPU 313 are also described by the CPU 313 # 0. 6 is the same as the case of accessing the peripheral device 324 of FIG. 6, but as shown in FIG. 6, instead of the addresses ADRS _A1 and ADRS _D1 in the case of the peripheral device 324 of # 0, the addresses ADRS _A2 and ADRS.
_{When D2} is specified, the internal address data is DF /
The internal write / read data is processed using F R ₁ to R _q , and the internal write / read data is DF / F R _{q + 1 to} R _n or latches L _{q + 1 to} L _n.
Be processed using.

As described above, in the configuration of FIG.
The address bus width, the data bus width, etc. on the peripheral device bus 318 can be dynamically changed by the peripheral device 324 accessed by the device 13. Function of Control Circuit 503 In the above description, the processing of changing the control signal supplied to the peripheral device 324 from the negated state to the asserted state and then returning it to the negated state is performed by the software processing in the CPU 313. . As a result, even if the peripheral device 324 connected to the peripheral device bus 318 is changed, it is possible to flexibly deal with it by the software processing on the CPU 313 side.

On the other hand, when the peripheral device 324 connected to the peripheral device bus 318 is fixed to some extent, high speed access to the peripheral device 324 is achieved by using the control circuit 503 of FIG. It will be possible.

That is, the CPU 313 activates the control circuit 503 by designating a predetermined address on the address bus. Accordingly, the control circuit 503 specifies the F / F control signals A _Ci (i = 1 to m) and A _Dj (j = 1 to n) while the control signal supplied to the peripheral device 324 is in the negated state. Control data including data that changes to the asserted state and then returns to the negated state is added to DF / FC _i (i = 1 to
m) and D _j (j = 1 to n) are sequentially designated. <Second Embodiment of Interface of I / O Controller to Peripheral Device> Next, I / O controller 3 of FIG.
FIG. 7 shows the configuration of the second embodiment of the interface portion for 15 peripheral devices 324. Configuration In FIG. 7, the input / output control circuit 701 and the address decoder 702 have the same functions as the input / output control circuit 501 and the address decoder 502 in the first embodiment of FIG.

In this case, the register control signals L _IOAR , L _IODRH , L _IODRL , L are set by the addresses A _IOAR , A _IODRH , A _IODRL , and A _MODE designated by the CPU 313 (see FIG. 3) on the address bus of the CPU bus 302. _MODE is
Assume that each is asserted.

The register IOAR is DF / F R _j (j
= 1 to n) and the function corresponding to DF / FC _i (i = 1 to m),
One register control signal L in the address decoder 502
It is a register that can be controlled by asserting _IOAR . In order to control the peripheral device 324 from the CPU 313 by software processing, some bits of the register IOAR include chip select signal bits CS1 and CS2 for selecting each peripheral device 324 and the selected peripheral device. 324 is assigned to a read / write designation signal bit R / W for giving a read instruction or a write instruction to 324, and the remaining bits are assigned to address signal bits.

The registers IODRH and IODRL hold internal address data or internal write data for the peripheral device 324, which is set from the CPU 313 (see FIG. 3) via the data bus of the CPU bus 302, and each of them has a register control signal L. It is a register that can be controlled when _IODRH and L _IODRL are asserted.

Based on the assertion of the register control signal L _MODE , the register _MODE receives the _MODE from the CPU 313.
The signal is set. And OR gate OR1, OR
2. In the logic circuit including the inverter INV and the AND gate AND1, the MODE signal described above and the register control signal L _IODRL output from the address decoder 702,
Register control signals ILL and ILH based on L _IODRH
Are generated and register IODR based on these signals
L and IODRH are controlled.

When logic "0" is designated as the MODE signal, the register IODRL and the bidirectional buffer OBL
Is used for internal write data, register IODRH
And the bidirectional buffer OBH is used for internal address data, and the peripheral device 324 of # 0 is accessed.

On the other hand, when logic "1" is designated as the MODE signal, the register IODRL and the bidirectional buffer OBL, and the register IODRH and the bidirectional buffer OBH.
In this case, both are used for internal write data, and the # 1 peripheral device 324 is accessed.

In the peripheral device 324 of # 0 connected to the peripheral device bus 318, for example, the control signal input terminal C is I
A signal line connected to the read / write designation signal bit R / W of the register IOAR in the / O controller 315 and the chip select signal bit C of the register IOAR.
It is connected to the signal line connected to S1. The address input terminal A is connected to a signal line group connected to the address signal bit group of the register IOAR and a signal line group connected to the bidirectional buffer OBH. Further, the data input / output terminal D is connected to a signal line group connected to the bidirectional buffer OBL.

On the other hand, # 1 connected to the peripheral device bus 318
In the peripheral device 324 of the control signal input terminal C
Are connected to the signal line connected to the read / write designation signal bit R / W of the register IOAR in the I / O controller 315 and the signal line connected to the chip select signal bit CS2 of the register IOAR. The address input terminal A is connected to the signal line group connected to the address signal bit group of the register IOAR. Further, the data input / output terminal D is connected to a signal line group connected to the bidirectional buffer OBL and a signal line group connected to the bidirectional buffer OBH.

As described above, even in the configuration of FIG.
Similar to the above configuration, the peripheral devices # 0 and # 1 connected to the peripheral device bus 318 housed in the I / O controller 315 are connected.
24 has different address bus widths and data bus widths, and different control lines are used. Data is written from the CPU 313 to the peripheral device 324 of # 0.
In the case where the CPU 313 writes the data by designating an address to the peripheral device 324 of # 0, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address A _MODE is designated to the address bus _No. 2 and the MODE signal having the logic "0" is set to the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the register control signal L _MODE based on the decoding result of the address A _MODE on the address bus. As a result, the MODE signal having the logic “0” is written in the register MODE.

Next, the CPU 313 uses the CPU bus 302.
The address A _IOAR is specified in the address bus of the CPU bus 302, and control data and a part of the internal address data for the data write access to the peripheral device 324 of # 0 are set in the data bus of the CPU bus 302. I / O controller 31
The address decoder 502 in 5 asserts the register control signal L _IOAR based on the decoding result of the address A _IOAR on the address bus. As a result, the register IOAR
The control data described above is written in. Specifically, a signal of logic "0" indicating a write instruction is written in the read / write designation signal bit R / W, a signal indicating a negated state is written in the chip select signal bit CS1, and data for internal address data is written. Part of the internal address data is written in the bit group.

Next, the CPU 313 uses the CPU bus 302.
The address A _IODRH is designated in the address bus of the _above, and a part of the internal address data designated for the peripheral device 324 of # 0 is set in the data bus of the CPU bus 302. I / O
The address decoder 502 in the controller 315 asserts the register control signal L _IODRH based on the decoding result of the address A _IODRH on the address bus.

Since the MODE signal whose logic is "0" is set in the register MODE, the output of the OR gate OR1 becomes the same as the logic of the register control signal L _IODRH , and the OR gate OR2 outputs the AND gate AND.
The input signal to 1 has the logic "1" which is the logic "0" of the MODE signal inverted by the inverter INV. Therefore, when the register control signal L _IODRH is asserted, the register control signal ILH is asserted, and the register I
Part of the internal address data is written to the ODRH from the data bus of the CPU bus 302.

On the other hand, in the bidirectional buffer IB, based on the read / write designating signal R / W having the logic "0" indicating the write designation output from the read / write designating signal bit R / W of the register IOAR. The bus data direction is set from the CPU 313 side to the peripheral device 324 side.

In this state, the CPU 313 makes the CP
The address A _IODRL is specified to the address bus of the U bus 302, and the peripheral device 3 of # 0 is set to the data bus of the CPU bus 302.
The internal write data written to 24 is set. Address decoder 5 in I / O controller 315
02 asserts the register control signal L _IODRL based on the decoding result of the address A _IODRL on the address bus. As a result, the register control signal ILL is asserted, and the internal write data is written to the register IODRL from the data bus of the CPU bus 302.

After that, the CPU 313 determines that the CPU bus 30
While specifying the address A _IOAR to the address bus of 2, C
Control data for changing the output state of the chip select signal bit CS1 of the register IOAR from the negated state to the asserted state on the data bus of the PU bus 302 and then returning to the negated state again based on a predetermined timing. Specify sequentially.

At this time, the read / write designation signal R / whose logic indicating the write instruction output from the read / write designation signal bit R / W of the register IOAR is "0".
Based on W, the bus data direction in the bidirectional buffer OBL is set to the direction from the CPU 313 side to the peripheral device 324 side. Further, since the AND gate AND2 is turned off by the MODE signal of which the logic output from the register MODE is “0”, the logic output from the AND gate AND2 is based on the read / write designation signal R / W of “0”.
The bus data direction in the bidirectional buffer OBH is also CP
The direction is set from the U313 side to the peripheral device 324 side.

As a result, the peripheral device 324 of # 0 instructs the state of the read / write designation signal R / W input from the read / write designation signal bit R / W of the register IOAR to the control signal input terminal C to write. The chip select signal bit C of the register IOAR.
At the timing when the state of the chip select signal CS1 input from S1 to the control signal input terminal C is asserted, both the signal line group on the peripheral device bus 318 connected to the internal address data bit group of the register IOAR The peripheral device bus 318 connected to the bidirectional buffer OBL receives internal address data output from the registers IOAR and IODRH to the signal line group on the peripheral device bus 318 connected to the bidirectional buffer OBH. The internal write data output from the register IODRL to the upper signal line is transferred to the data input / output terminal D.
Take in from. Data is read from the peripheral device 324 of # 0 to the CPU 313.
Then, when the CPU 313 specifies an address to the peripheral device 324 of # 0 to read data, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address A _MODE is designated to the address bus _No. 2 and the MODE signal having the logic "0" is set to the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the register control signal L _MODE based on the decoding result of the address A _MODE on the address bus. As a result, the MODE signal having the logic “0” is written in the register MODE.

Next, the CPU 313 uses the CPU bus 302.
The address A _IOAR is specified for the address bus of the CPU bus 302, and control data and a part of the internal address data for the data read access to the peripheral device 324 of # 0 are set to the data bus of the CPU bus 302. I / O controller 31
The address decoder 502 in 5 asserts the register control signal L _IOAR based on the decoding result of the address A _IOAR on the address bus. As a result, the register IOAR
The control data described above is written in. Specifically, a signal of logic "1" indicating a read instruction is written in the read / write designation signal bit R / W, a signal indicating a negate state is written in the chip select signal bit CS1, and a signal for internal address data is written. Part of the internal address data is written in the bit group.

Next, the CPU 313 uses the CPU bus 302.
The address A _IODRH is designated in the address bus of the _above, and a part of the internal address data designated for the peripheral device 324 of # 0 is set in the data bus of the CPU bus 302. I / O
The address decoder 502 in the controller 315 asserts the register control signal L _IODRH based on the decoding result of the address A _IODRH on the address bus.

Since the MODE signal having the logic "0" is set in the register MODE, the output of the OR gate OR1 becomes the same as the logic of the register control signal L _IODRH , and the OR gate OR2 outputs the AND gate AND.
The input signal to 1 has the logic "1" which is the logic "0" of the MODE signal inverted by the inverter INV. Therefore, when the register control signal L _IODRH is asserted, the register control signal ILH is asserted, and the register I
Part of the internal address data is written to the ODRH from the data bus of the CPU bus 302.

After that, the CPU 313 determines that the CPU bus 30
While specifying the address A _IOAR to the address bus of 2, C
Control data for changing the output state of the chip select signal bit CS1 of the register IOAR from the negated state to the asserted state on the data bus of the PU bus 302 and then returning to the negated state again based on a predetermined timing. Specify sequentially.

At this time, the read / write designation signal R / whose logic indicating the read instruction output from the read / write designation signal bit R / W of the register IOAR is "1".
Based on W, the bus data direction in the bidirectional buffers IB and OBL changes from the peripheral device 324 side to the CPU 313.
It is set to the side. On the other hand, the register MODE
Since the AND gate AND2 is turned off by the MODE signal whose logic is “0” output from the bidirectional buffer OBH, the AND gate AND2 is output based on the read / write designation signal R / W whose logic is “0”. The bus data direction is set from the CPU 313 side to the peripheral device 324 side.

As a result, the peripheral device 324 of # 0 indicates the state of the read / write designation signal R / W input to the control signal input terminal C from the read / write designation signal bit R / W of the register IOAR. The chip select signal bit C of the register IOAR.
At the timing when the state of the chip select signal CS1 input from S1 to the control signal input terminal C is asserted, both the signal line group on the peripheral device bus 318 connected to the internal address data bit group of the register IOAR The internal address data output from the registers IOAR and IODRH to the signal line group on the peripheral device bus 318 connected to the destination buffer OBH.
From the data input / output terminal D onto the signal line on the peripheral device bus 318 connected to the bidirectional buffer OBL.

The internal read data is latched by the latch L via the bidirectional buffer OBL, then output to the data bus of the CPU bus 302 via the bidirectional buffer IB, and processed by the CPU 313. When the CPU 313 accesses the peripheral device 324 of # 1 As described above, when the CPU 313 accesses the peripheral device 324 of # 0, the internal address data specified by the CPU 313 is the register IOAR in the I / O controller 315. Of the internal I / O controller 315, and the internal read / write data is transferred to the peripheral device 324 of # 0 by using the register IODRH and the register IODRH.
Alternatively, it is processed using the latch L.

On the other hand, when the CPU 313 accesses the peripheral device 324 of # 1, the internal address data designated by the CPU 313 is the I / O controller 315.
The internal read / write data is transferred to the peripheral device 324 of # 1 by using only a part of the register IOAR in the internal I / O.
Registers IODRL and IO in the I / O controller 315
It is processed using both DRH or Latch.

Below, the CPU 313 sets the peripheral device 32 of # 1.
The control operation when accessing 4 will be described. Data is written from the CPU 313 to the # 1 peripheral device 324.
When the CPU 313 writes data by designating an address to the peripheral device 324 # 1, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address A _MODE is designated for the second address bus, and the MODE signal having the logic “1” is set for the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the register control signal L _MODE based on the decoding result of the address A _MODE on the address bus. As a result, the MODE signal having the logic “1” is written in the register MODE.

Next, the CPU 313 determines that the CPU bus 302
The address A _IOAR is specified in the address bus of No. 1, and control data and internal address data for data write access to the peripheral device 324 of # 1 are set in the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the register control signal L _IOAR based on the decoding result of the address A _IOAR on the address bus. As a result, the above-mentioned control data is written in the register IOAR. Specifically, a signal of logic "0" indicating a write instruction is written in the read / write designation signal bit R / W, a signal indicating a negated state is written in the chip select signal bit CS2, and the internal address data Internal address data is written in the bit group.

As a result, the read / write designation signal R / whose logic indicating the write instruction output from the read / write designation signal bit R / W of the register IOAR is "0".
Based on W, the bus data direction in the bidirectional buffer IB is set to the direction from the CPU 313 side to the peripheral device 324 side.

In this state, the CPU 313 sends the CP
The address A _IODRL is specified to the address bus of the U bus 302, and the peripheral device 3 of # 0 is set to the data bus of the CPU bus 302.
The internal write data written to 24 is set. Address decoder 5 in I / O controller 315
02 asserts the register control signal L _IODRL based on the decoding result of the address A _IODRL on the address bus. Here, the MODE signal whose logic is “1” output from the register MODE turns on the AND gate AND1 via the OR gate OR1. Therefore, the register control signal L _{IODRL causes} the register control signal ILL to be asserted, and at the same time, the OR gate OR2 and the AND gate AN.
The register control signal ILH is also asserted via D1. As a result, the internal write data is simultaneously written from the data bus of the CPU bus 302 to both the registers IODRL and IODRH.

After that, the CPU 313 determines that the CPU bus 30
While specifying the address A _IOAR to the address bus of 2, C
Control data for changing the output state of the chip select signal bit CS2 of the register IOAR from the negated state to the asserted state on the data bus of the PU bus 302 and then returning to the negated state again based on a predetermined timing. Specify sequentially.

At this time, the read / write designating signal R / having a logic "0" indicating the write instruction output from the read / write designating signal bit R / W of the register IOAR.
Based on W, the bus data direction in the bidirectional buffer OBL is set to the direction from the CPU 313 side to the peripheral device 324 side. Further, since the AND gate AND2 is turned on by the MODE signal whose logic is “1” output from the register MODE, the read / write designation signal R / W whose logic indicating the above-mentioned write instruction input to this is “0”. Based on the above, the bus data direction in the bidirectional buffer OBH is also set in the direction from the CPU 313 side to the peripheral device 324 side.

As a result, the # 1 peripheral device 324 issues a write command indicating the state of the read / write designation signal R / W input from the read / write designation signal bit R / W of the register IOAR to the control signal input terminal C. The chip select signal bit C of the register IOAR.
At the timing when the state of the chip select signal CS2 input from S2 to the control signal input terminal C is asserted, the register is set in the signal line group on the peripheral device bus 318 connected to the internal address data bit group of the register IOAR. The internal address data output from the IOAR is taken in from the address input terminal A, and the bidirectional buffer OBL
, And internal write data output from the registers IODRL and IODRH to the signal line group on the peripheral device bus 318 connected to OBH and OBH from the data input / output terminal D. Data is read from the # 1 peripheral device 324 to the CPU 313.
Then, when the CPU 313 designates an address to the peripheral device 324 # 1 to read data, the following operation is executed.

First, the CPU 313 determines that the CPU bus 30
The address A _MODE is designated for the second address bus, and the MODE signal having the logic “1” is set for the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 asserts the register control signal L _MODE based on the decoding result of the address A _MODE on the address bus. As a result, the MODE signal having the logic “1” is written in the register MODE.

Next, the CPU 313 uses the CPU bus 302.
The address A _IOAR is designated for the address bus of No. 1, and control data and internal address data for data read access to the peripheral device 324 of # 1 are set to the data bus of the CPU bus 302. The address decoder 502 in the I / O controller 315 receives the register control signal L _IOAR based on the decoding result of the address A _IOAR on the address bus.
Assert. As a result, the above-mentioned control data is written in the register IOAR. Specifically, a signal of logic "1" indicating a read instruction is written in the read / write designation signal bit R / W, and a signal indicating a negated state is written in the chip select signal bit CS2.

After that, the CPU 313 determines that the CPU bus 30
While specifying the address A _IOAR to the address bus of 2, C
Control data for changing the output state of the chip select signal bit CS2 of the register IOAR from the negated state to the asserted state on the data bus of the PU bus 302 and then returning to the negated state again based on a predetermined timing. Specify sequentially.

At this time, the read / write designating signal R / having the logic "1" indicating the read instruction output from the read / write designating signal bit R / W of the register IOAR.
Based on W, the bus data direction in the bidirectional buffers IB and OBL changes from the peripheral device 324 side to the CPU 313.
It is set to the side. In addition, the register MODE
Since the AND gate AND2 is turned on by the MODE signal whose logic is “1”, the logic indicating the above-mentioned read instruction inputted to the AND gate AND2 is based on the read / write designation signal R / W whose logic is “1”. The bus data direction in the bidirectional buffer OBH is also from the peripheral device 324 side to the CPU 31.
It is set in the direction toward the 3 side.

As a result, the peripheral device 324 of # 0 indicates the state of the read / write designation signal R / W input to the control signal input terminal C from the read / write designation signal bit R / W of the register IOAR. The chip select signal bit C of the register IOAR.
At the timing when the state of the chip select signal CS2 input from S2 to the control signal input terminal C is asserted, the register is set in the signal line group on the peripheral device bus 318 connected to the internal address data bit group of the register IOAR. The internal address data output from the IOAR is taken in from the address input terminal A, and the bidirectional buffer OBL
, And internal read data is output from the data input / output terminal D onto a signal line on the peripheral device bus 318 connected to OBH.

This internal read data is latched in the latch L via the bidirectional buffers OBL and OBH, and then,
The data is output to the data bus of the CPU bus 302 via the bidirectional buffer IB and processed by the CPU 313. Other Aspects In the second embodiment of the interface to I / O controller peripherals described above, I / O controller 315
The signal line group on the peripheral device bus 318 connected to the internal address data bit group of the internal register IOAR is connected to the address input terminal A of the peripheral device 324, but the peripheral device 324 does not select the chip select signals CS1 and CS2. And a control signal other than the read / write designation signal R / W is required, the signal line group on the peripheral device bus 318 connected to a part of the above-mentioned internal address data bit group is controlled by other control signals. It may be used for signaling.

Further, in the above-mentioned embodiment, one register IOAR is provided for control data and a part of internal address data.
Is provided and the register is configured to be controlled by the register control signal L _IOAR . However, a register for control data and a register for internal address data are separately provided and controlled by different register control signals. You may

Further, in the above embodiment, the peripheral device 324
The process of changing the chip select signals CS1 and CS2 supplied to the IC chip from the negated state to the asserted state and then returning it to the negated state is performed by the software processing in the CPU 313. The control circuit 503 of FIG. By providing a dedicated hardware circuit similar to, it is possible to speed up access to the peripheral device 324.

[0165]

According to the present invention, depending on the peripheral device accessed by the CPU, the address bus width on the peripheral device bus,
Since the data bus width and the like can be dynamically changed, one peripheral device control IC having a limited number of pins can control peripheral devices having various bus widths.

The control signal supplied to the peripheral device is C
By changing the software processing in the PU, even if the peripheral device connected to the peripheral device bus is changed, it is possible to deal flexibly with the software processing on the CPU side.

On the other hand, when the peripheral device connected to the peripheral device bus is fixed to some extent, a dedicated hardware circuit for changing the control signal is provided to enable high-speed access to the peripheral device.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a configuration diagram of a network to which an embodiment of the present invention is applied.

FIG. 3 is a configuration diagram of a message communication device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of message communication.

FIG. 5 is a configuration diagram of a first embodiment of an interface of the I / O controller to peripheral devices.

FIG. 6 is an explanatory diagram of a division form of a peripheral device bus.

FIG. 7 is a configuration diagram of a second embodiment of the interface of the I / O controller to the peripheral device.

[Explanation of symbols]

 101 Host Processor 102 Host Bus 103 Peripheral Device 104 Peripheral Device Bus 105 Data Signal Line of Host Bus 102 106 Signal Line of Peripheral Device Bus 104 107 Buffer Means 108 Address Signal Line of Host Bus 102 109 Peripheral Device Input / Output Control Means 110 Peripheral Device Access device

Claims (4)

[Claims] 1. A peripheral device access device (110) for accommodating a peripheral device bus (104) connected to a host bus (102) to which a host processor (101) is connected and to which a plurality of peripheral devices (103) are connected. ), A plurality of signal lines (105) of the host bus (102) and a plurality of signal lines (106) for connecting the signal lines (106) of the peripheral device bus (104) are provided. Buffer means (107) and address signal line (108) of the host bus (102)
Connected to the host processor (101) and each of the plurality of peripheral devices (103) is accessed by the host processor (101), via the address signal line (108) of the host bus (102) from the host processor (101). Firstly, based on the address data designated by the above, the signal line (106) of the peripheral device bus (104) to which the control signal terminal (C) of the peripheral device (103) to be accessed is connected. The buffer means (10
7) to control the buffer means (107), the data signal line (105) of the host bus (102) and the peripheral device for the host processor (101) and the accessed peripheral device (103). A control signal is transmitted and received via the signal line (106) of the bus (104), and secondly,
The peripheral device bus (10) to which the address signal terminal (A) of the peripheral device (103) to be accessed is connected.
4) Controlling the buffer means (107) connected to the signal line (106), the host processor (101)
With respect to the data signal line (1) of the host bus (102)
05) to set internal address data for the accessed peripheral device (103) via the buffer means (107) and the signal line (106) of the peripheral device bus (104), and thirdly, It controls the buffer means (107) connected to the signal line (106) of the peripheral device bus (104) to which the data signal terminal (D) of the accessed peripheral device (103) is connected, and controls the host processor. (101) and the peripheral device (103) to be accessed by using the buffer means (107), the data signal line (105) of the host bus (102)
And a peripheral device input / output control means (109) for transmitting and receiving internal access data via the peripheral device bus (104) signal line (106). 2. The plurality of buffer means are grouped into a plurality of groups, and the peripheral device input / output control means connects each of the groups of the buffer means to the address signal line of the host bus from the host processor. The peripheral device access device according to claim 1, wherein the peripheral device access device is collectively controlled based on address data corresponding to each of the groups designated through the peripheral device access device. 3. The peripheral device bus in which the control signal terminal of the peripheral device to be accessed is connected to the peripheral device input / output control means via the address signal line of the host bus. The address signal data for writing to the buffer means connected to the signal line of the host bus is supplied with the control signal data which is sequentially changed with time to be supplied to the peripheral device to be accessed. 3. The peripheral device access device according to claim 1, wherein the buffer device is sequentially written via a line. 4. The peripheral device bus, wherein the host processor is connected to a control signal terminal of the peripheral device to be accessed to the peripheral device input / output control means via an address signal line of the host bus. Address data for writing to the buffer means connected to the signal line, and control signal data for supplying to the peripheral device to be accessed is supplied to the buffer means via the data signal line of the host bus. Further comprising control signal generating means for generating a control signal for supplying to the peripheral device to be accessed by sequentially changing the control signal data of the buffer means in time after sequentially writing in the means. The peripheral device access device according to claim 1 or 2.