JPH0644190A - Multi-processor system - Google Patents

Abstract

PURPOSE:To enable transmitting plural messages at a time by providing a means which executes the buffering of a message transmitted and received between processors and also plural pairs of its control information in a message area so as to control them. CONSTITUTION:A system is constituted of the plural processors which are provided with an interruption issuing control part 2 which issues inter-program interruption to a issueing source, an interruption reception control part 3 which receives inter-processor interruption from another processor and a transmission side message control part 1 and a reception side message control part 4 which control the message area where the message and the control information transmitted and received between one of the issuing side processors and one of the reception side processors are stored. Moreover, the transmission side message control part 1 and the reception side message control part 4 execute the buffering of the message and the plural pairs of its control information which are transmitted and received between the processors in the message area so as to control them. Thus, the opening stand-by of the message area is eliminated so that plural messages can be transmitted at a time.

Description

Detailed Description of the Invention

[0001]

The present invention is used in a multiprocessor information processing system. In particular, it relates to inter-processor communication means.

[0002]

2. Description of the Related Art In the conventional example, as shown in FIG. 5, since there is a one-to-one relationship between the message areas of the transmitting side processor and the receiving side processor, only one message can be transmitted at a time. Therefore, the message area was not released and the message could not be sent unless the message was picked up by the receiver. In addition, some time was spent on inter-processor communication processing such as waiting time for releasing the message area and processing time for logging messages on the transmitting side and the receiving side.

[0003]

As described above, in the conventional example, only one message can be transmitted at a time, which causes a considerable amount of waiting for the message area to be released in the transmitting side processor. In order to record the temporal transition of the operating state (command, message detailed information, system clock, etc.) of the inter-processor communication of the above, it is necessary to perform message logging processing on the transmitting and receiving side processor, and a great deal of processing time was spent.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a multiprocessor system having means capable of transmitting a plurality of messages at one time.

[0005]

According to the present invention, an interrupt issuing unit for issuing an inter-program interrupt to an issue destination, an interrupt receiving control unit for receiving an inter-processor interrupt from another processor, and one of the issuing side processors are provided. In a multiprocessor system composed of a plurality of processors including a message management unit that manages a message area in which a message transmitted and received to and from one of the side processors is stored, the message management unit is ,
It is characterized in that the message area includes means for buffering and managing a plurality of sets of messages transmitted and received between processors and their control information.

[0006]

A message area for storing a message transmitted and received between one of the issuing side processor and one of the receiving side processor and its control information is multi-buffered. This makes it possible to send a plurality of messages at once without waiting for the message area to be released.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing this embodiment. In this embodiment, on the transmission side, a message management unit 1 for storing a message to be transmitted to an issuing destination, an interrupt issuing control unit 2 for issuing an interprocessor interrupt to the issuing destination, and an interrupt for receiving an interprocessor interrupt on the receiving side. The reception control unit 3 and the reception side message management unit 4 that receives and processes the transmitted message are configured. That is, this embodiment is similar to FIG.
, An interrupt issue control unit 2 for issuing an inter-program interrupt to an issue destination, an interrupt reception control unit 3 for receiving an inter-processor interrupt from another processor, one issuing processor and one receiving processor. And a receiving side message managing section 4 that manages a message area in which messages sent and received between the sending side and the control information thereof are stored. As a characteristic means, the transmission side message management section 1 and the reception side message management section 4 include means for buffering and managing a plurality of sets of messages and their control information exchanged between the processors in the message area.

FIG. 2 shows the structure of the message area of this embodiment, FIG. 3 shows a flow chart of the operation of the transmitting side processor, and FIG. 4 shows a flow chart of the operation of the receiving side processor. Next, the operation of this embodiment will be described.

When performing inter-processor communication, the number of messages to be transmitted to the partner processor is obtained by the transmitting processor (step S212), and the pointer of the message area of the target processor is obtained (step S213). Next, the control flag in the control information is checked (step S214). If the control flag is not on, the interrupt issue control flag is turned on (step S215), and processing such as message storage (steps S216 to S21) is performed.
7) is performed to update the pointer in the message area (step S218). Repeat until the number of sent messages reaches zero. After that, a bit indicating a communication request to the receiving processor is added to the communication request table (hereinafter, P-
TBL) (step S220) and issue an inter-processor interrupt (step S221). If the control flag is on, the inter-processor interrupt is issued depending on the state of the interrupt issue control flag. At the receiving processor, when an inter-processor interrupt occurs, P-TB
By reading L (step S311), the processor having the communication request is known. The transmission processor number is specified from the P-TBL (step S314), and the pointer of the message area of the target processor is read (step S314).
316). Information is taken from the message area and the inter-processor communication command is executed (step S318).
-Step S320). Next, the pointer in the message area is updated (step S321), and the interprocessor communication command is executed until the control flag is turned off.

[0010]

As described above, the present invention eliminates the waiting for the release of the message area from the sending side by multi-buffering the message area, and
The effect is that multiple messages can be sent at one time. In addition, since the message area information automatically becomes logging information, it is not necessary to log the message, and the inter-processor communication processing performance can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing the structure of a message area according to the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 4 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a message area of a conventional example.

[Explanation of symbols]

 1 Sending side message management section 2 Interrupt issuing control section 3 Interrupt receiving control section 4 Receiving side message management section

Claims (1)

[Claims] 1. An interrupt issuing unit that issues an inter-program interrupt to an issue destination, an interrupt reception control unit that receives an inter-processor interrupt from another processor, and one of the issuing processor and one of the receiving processors. In a multiprocessor system including a plurality of processors having a message management unit that manages a message area in which messages to be transmitted and received and control information thereof are stored, the message management unit is provided in the message area between the processors. A multiprocessor system including means for buffering and managing a plurality of sets of messages to be transmitted and received and control information thereof.