JPH0642207B2 - Multi-level programming method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a multi-level programming system provided with nano program control at a lower level under the control of micro program control, and particularly detects an address error of a nano program sequencer. It is something that is done.

[Conventional technology]

Conventionally, in order to improve the operation processing speed, nano-program control at a lower level is provided under the control of micro-program control, and multiple clocks are required by multiple loops such as abnormal logical operations and function operations other than arithmetic operations. A multi-level programming method has been proposed in which such special operations are assigned to the nano program control and the program level is changed as necessary.

This multi-level programming method is shown in FIGS.
As shown in the figure, a micro program control unit 1 including a micro sequencer 11, a micro program memory 12, and a micro dedicated pipeline register 13,
A nano program control unit 2 including a nano sequencer 21, a nano program memory 22, and a nano dedicated pipeline register 23, and a control target based on a dedicated control signal at each program level and a micro / nano program common control signal For example, the data processing unit 3 is provided.

The data processing unit 3 includes a calculator 31 and a high-speed work register 3
2, 33, cache memory 34 and system memory 3
5, the high speed data processing unit 4 uses the registers 32 and 33 because the cache memory 34 and the system memory 35 are used for calculation in the micro program processing and the control clock is high speed in the nano program processing.
To perform high-speed calculation between registers.

Thus, when the microprocessor is operating under the control of the micro program control unit 1, the nano program control unit 2 is in an idle state waiting for execution permission from the micro program control unit 1, and the nano sequencer The program counter included in 21 is stopped, all the nano program dedicated control signals output from the nano dedicated pipeline register 23 are locked, and the output from the micro / nano common pipeline register 15 is set by the micro / nano program selector 14. The program control signal is output.

The nano program control unit 2 is managed by the micro program control unit 1 via the nano program execution control circuit shown in FIG.

That is, 50 is a nano-program control flip-flop composed of a D-type flip-flop, 51 is a nano-program control AND gate, 52 is a micro watchdog timer, and a micro program pipeline by a nano program start instruction in micro program processing. A nanoprogram activation request signal is output from the register 13 and is supplied to the nanoprogram control flip-flop 50 via the AND gate 51. Therefore, the nano program control flip-flop 50 is set at the time when the nano control clock becomes high level, the nano program execution permission signal is output from the output side thereof, and this is input to the nano program control unit 2. , Nanoprogram processing is executed. At this time, the output of the AND gate 51 is input to the micro program control unit 1 as a micro program stop command, whereby the micro program control unit 1 enters a standby state waiting for the end of the nano program processing.

On the other hand, a nano program end command (NEND command) shown in FIG. 7B is provided at the end of each of the plurality of nano program groups stored in the nano program memory 22 of the nano program control unit 2, and the nano program memory 2
In the unused area of No. 2, a halt instruction (HA
(LT instruction) is provided, and when the nano program ends normally by the nano program end instruction, the nano program end signal is output from the nano-dedicated pipeline register 23 to the AND gate 51 to operate the micro program control unit 1. Then, the nanoprogram control unit 2 is reset when the nanoprogram control flip-flop 50 is reset at the time when the nanocontrol clock becomes high level, so that the nanoprogram execution is stopped and the nanoprogram control unit 2 enters the idle state. When an address error occurs in the nano sequencer 21 and the halt command is reached, the nano sequencer is stopped and the nano program end signal is not output. Therefore, since the output of the AND gate 51 becomes low level when the micro watchdog timer 52 times out, the stop instruction of the micro program is canceled and the micro program processing is returned to.

[Problems to be solved by the invention]

However, in the conventional multi-level programming method described above, the halt instruction is stored in the nano program memory, and the micro program processing is performed when the micro watchdog timer times out after the nano sequencer is stopped at the time of an address error. Since it takes time to return to the microprogram processing from the time when an address error occurs, the microwatchdog timer times up to detect the address error. It is not possible to determine whether or not there is an error in the nano sequencer address, and it is not possible to determine whether the program can be continuously executed by the microprogram processing operating system, so the system will be down. There is a problem.

Therefore, the present invention has been made in view of the problems of the above-mentioned conventional example, in which an address abnormal instruction is stored in the nano program control unit, and when the address abnormal signal is output from the nano program control unit, the address By providing an address error detection circuit that performs error processing, it quickly returns to microprogram processing when a nanosequencer address error occurs, facilitates recognition of nanosequencer address error in microprogram processing, and makes no judgment of the operating system for microprogram processing. It is an object of the present invention to provide a multi-level programming method that can prevent the activation of a new nanoprogram process and solve the problems of the conventional example.

[Means for solving problems]

In order to achieve the above object, the first invention of the present application comprises a micro program control unit and a nano program control unit,
Upon receiving a nanoprogram activation request from the microprogram control unit, a microprogram stop command is output to the microprogram control unit, a nanoprogram execution permission is output to the nanoprogram control unit, and In a multi-level programming method having a nano program execution control circuit for receiving the nano program end signal and canceling the micro program stop command and the nano program execution permission, an unused area in the program memory of the nano program control unit and each nano program group The nano end instruction with address error flag is stored at the boundary position of each address, and when the nano program counter reaches the address of the nano end instruction with address error flag, the nano program control unit sends the address error message. Is output, the address abnormality signal is latched by the address abnormality control circuit, the address abnormality notification is output to the nanoprogram control unit, the microprogram stop command and the nanoprogram execution permission are released, and the microprogram processing is forced. When the operating system for microprogram processing is notified of an address abnormality and the operating system for microprogram processing is capable of continuing execution of nanoprogram processing, a latch state release command is output to the address abnormality control circuit. The nanoprogram activation request is locked by the output of the address abnormality control circuit until the latching state of the address abnormality control circuit is released.

Further, a second invention of the present application comprises a micro program control unit and a nano program control unit, receives a nano program activation request from the micro program control unit, and outputs a micro program stop command to the micro program control unit. A multi-level having a nano-program execution control circuit for outputting a nano-program execution permission to the nano-program control unit and canceling the micro-program stop command and the nano-program execution permission in response to a nano-program end signal from the nano-program In the programming method, the nano program counter stores the nano end instruction with an address error flag at an unused area in the program memory of the nano program control unit and the boundary position of each nano program group, and the nano program counter causes the address error flag to be stored. When the address of the nano end command is reached, an address abnormality signal is output from the nano program control unit, the address abnormality signal is latched by the address abnormality control circuit, and an address abnormality notification is output to the nano program control unit. While canceling the micro program stop command and nano program execution permission and forcibly returning to the micro program processing, an address error is notified to the operating system of the micro program processing, and the runaway of the nano program is monitored by the nano program monitoring circuit, When the nanoprogram monitoring circuit detects a nanoprogram runaway, the state is latched and this is notified to the operating system, and when an address error or nanoprogram runaway occurs, the nanoprogram address before and after that will occur. To Held by a dress holding circuit, and when the operating system of the microprogram processing can continue execution of the nanoprogram processing, a latch state release command is output to the address abnormality control circuit and the nanoprogram monitoring circuit, and the address abnormality control circuit and The nanoprogram activation request is locked by the output of the address abnormality control circuit and the nanoprogram monitoring circuit until the latch state of the nanoprogram monitoring circuit is released.

[Action]

In the first invention, the nano-end instruction with the address abnormality flag is stored in the unused area of the nano program area and the boundary position of a plurality of nano program groups, and the nano program counter causes the nano program counter to address when the address abnormality occurs in the nano sequencer. When the number of nano-end instruction with error flag is reached, the nano-program control unit outputs an address error signal to the address error control circuit, and this address error control circuit immediately activates the nano-program control circuit to forcibly execute the micro program. At the same time as returning to the processing, the nano sequencer address error notification is sent to the micro program processing operation system, and this operation system can recognize the nano sequencer address error and judge whether the nano program processing can be continued or not. , Can be continued When it is determined that it is, and outputs the latched state release instruction to address the abnormality control circuit inhibits the activation of the new nano programs unless latched off of the address anomaly signal.

In addition, in the second invention, in addition to the operation of the first invention, the microprogram processing is forcibly restored and the name program is executed even when the nanoprogram runaway circuit detects a runaway of the nanoprogram. Since the runaway is notified to the operating system, it can be recognized whether the nanoprogram error is an address error or a program runaway error, and when either a nanoprogram address error or a nanoprogram runaway is detected. Further, by holding the nano program address before and after that in the address holding circuit, the cause of the abnormality can be analyzed.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In the figure, 1 is a micro program controller, 2 is a nano program controller, 11 is a micro sequencer, 12 is a micro program memory, 13 is a micro dedicated pipeline register, 21 is a nano sequencer, 22 is a nano program memory, and 23 is a nano program memory. Pipeline register, 50 is a nano-program control flip-flop, and 51 is a nano-program control AND gate. Since these have the same configuration as the conventional example of FIG. 5, detailed description thereof will be omitted. .

In the present invention, the nano program memory 22 of the nano program control unit 2 is constructed as shown in FIG. That is, in FIG. 3, M ₁ is a map area, which constitutes a jump table for jumping to the nanoprogram of the number designated by the nanoprogram activation instruction of the microinstruction, and N _{1 to} N _n are plural n. It is a group of individual nano programs. Then, in the unused area of the map area M ₁ , the check point at the boundary position of the nanoprogram group, and the unused area of the program, the nano-end instruction with the address abnormality flag is stored as shown by the diagonal lines.
This nano end instruction with address abnormality flag (AERR instruction) is the normal nano program end instruction (NEND instruction) shown in FIG. 2 (a), and the address abnormality flag represented by the least significant 1-bit information of the operand part is " On the other hand, as shown in FIG. 2 (b), the opcode part is exactly the same as the nanoprogram end instruction, and the lowest 1
The only difference is that the address abnormality flag represented by a bit is set to "1". Therefore, the nano-end instruction with the address abnormality flag is configured so that the processing for the nano program and the processing for outputting the nano program end signal are exactly the same as the nano program end instruction, and the pipeline register 23 stores the least significant 1-bit information of the operand part. When it is "1", an address abnormality signal is output.

The address abnormality signal output from the pipeline register 23 is supplied to the J input side of the JK flip-flop 53 which constitutes the address abnormality control circuit, and the K input side of the JK flip-flop 53 is supplied from the operation system of the microprogram processing. An error reset signal as an input latch state release command is supplied. Then, the address abnormality notification signal obtained from the output side of the JK flip-flop 53 is notified to the operation system of the microprogram processing, and is supplied to one input side of the address abnormality control OR gate 54.
The pipeline register 23 is provided to the other input of the R gate 54.
The nano program end signal from And
The output side of the OR gate 54 is connected to the other inverting input side of the nano program control AND gate 51 to which the nano program start request signal from the pipeline register 13 of the micro program control section 1 is input to one input side. There is.

Next, the operation of the first embodiment will be described. Now, when the nano program processing is executed by the nano program start request signal from the micro program control unit 1 and the nano program processing is normally completed, a nano program end command is output from the nano program memory 22 and the pipeline is executed. Since the nano program end signal is output from the register 23, this is input to the nano program control AND gate 51 via the OR gate 54, so that the output side becomes low level, and the micro program stop command is released and the micro program stop command is released. The nanoprogram control flip-flop 50 is returned to the program processing.
Is reset when the nano control clock arrives, and the nano program control unit 2 enters the idle state.

However, (1) the nanoprogram counter of the nanosequencer 21 specifies the address of the address abnormal instruction in the unused area of the map area M ₁ by activating the unregistered nanoprogram from the microprogram control unit 1. In the case of (2) when an incorrect address is set in the nano program counter during the nano program processing and the program runs out of control, and the nano program counter reaches the addresses of nano sequencer address abnormal instructions scattered in multiple places of the nano program memory 22. Is a nano-only pipeline register 2
A nanoprogram end signal and an address abnormality signal are output from 3. Therefore, the nanoprogram end signal is O
By being supplied to the AND gate 51 via the R gate 54, the output side of the AND gate 51 becomes low level, the micro program stop command signal is released, and the micro program control unit 1 quickly returns to the operating state,
After that, when the nano control clock is input to the nano program control flip-flop 50, the nano program execution permission signal is not output from the output side, so the nano program control unit 2 is in the idle state.

Due to the transition of the nano program control unit 2 to the idle state, the nano program end signal is not output, but the address abnormal signal is the JK flip-flop 53.
When the nano control clock is input to, it is latched, and the address error notification signal is output from its output side.
Since this is input to the AND gate 51 through the OR gate 54, the AND gate 51 does not output a microprogram stop command and the nanoprogram control flip-flop 50 is not set.

Further, the address abnormality notification signal output from the JK flip-flop 53 is input to the micro operation system, and it is possible to easily recognize that the nano sequencer has an address abnormality in this micro operation system. When the nano program memory 22 is composed of RAM, when it is judged that the nano program control can be continued by reloading the nano program and analyzing the cause of abnormality, a new nano program is started until an error reset signal is output. Is prohibited.

As described above, according to the first embodiment, it is possible to easily and promptly return to the microprogram processing from the nano-address abnormal instruction through the simple control circuit, and recognize the address abnormality in the micro operation system. It is possible to prohibit the activation of new nano programs.

Next, a second embodiment of the present invention will be described with reference to FIG.

The second embodiment makes it possible to recognize whether the runaway pattern of the nanosequencer is an infinite loop or an address error.

That is, as shown in FIG. 4, the output of the AND gate 51 for controlling the nano program is changed to the nano watchdog timer 6
0 to notify the micro-operation system of the time-up signal, and to the inverting input side of the AND gate 51 for nano program control and the AND gate 61 for nano clock control, and the other one input of the AND gate 61. The nano control clock is input to the other side, the address abnormality notification signal is input to the other inverting input side, the address signal output from the nano sequencer 21 is supplied to the address latch register 62, and the latch address thereof is supplied to the other address latch register 63. And a configuration similar to that of the first embodiment except that the output of the nanoclock controlling AND gate 61 is supplied to both address latch registers 62 and 63 as a latch clock.
Portions corresponding to those in the figure are denoted by the same reference numerals and detailed description thereof will be omitted.

According to the second embodiment, when the nanoprogram control unit 2 normally executes the nanoprogram, the address abnormality signal is not output from the pipeline register 23 as described above, so that the JK flip-flop 53 is In the reset state, the address abnormality notification signal is not output, and since the nano watchdog timer 60 does not time up, the nano clock control AND gate 61 outputs the nano control clock as it is to the address latch register 62 and the nano control clock. The present address data and the previous address data, which are output to 63 and are output from the nano sequencer 21, are latched in the address latch registers 62 and 63.

When an address abnormality occurs in the nanosequencer 21 in this state, as described above, the pipeline register 23 outputs the address abnormality signal, which is latched by the JK flip-flop 53, and the address abnormality notification signal is output from the output side. Since this is output to the nanoprogram control AND gate 51, the microprogram stop command signal is released, the microprogram processing is restored, and the output of the nanoclock control AND gate 61 is maintained at a low level. The address latches of the address latch registers 62 and 63 are stopped. Therefore, the address latch register 62 latches the address data output from the current nano-sequencer 21, and the address latch register 63 latches the address data immediately before the address data. By notifying the data to the micro operation system, it is possible to recognize the address in which the error occurred in the micro operation system and the address immediately before it, which is effective in analyzing the cause of the error.

Further, when the nano sequencer 21 enters an infinite loop and goes into a runaway state, the nano program end signal is no longer output from the pipeline register 23, so that the output of the nano program control AND gate 51 maintains a high level. The watchdog timer 60 times up, and the time-up signal is AND for nano program control.
It is input to the gate 51 and the nano clock control AND gate 61. Therefore, AND for nano program control
The output of the gate 51 becomes low level, the microprogram processing is resumed, the nanoprogram control unit 2 becomes idle, and the address latch register 62
And 63, the address data output from the nano sequencer 21 when the nano watchdog timer 60 times out and the address data immediately before it are respectively latched. Then, the time-up signal of the nano watchdog timer 60 and the address data at that time and the address data immediately before are notified to the micro operation system, so that an abnormal state due to an infinite loop occurs in the nano program in the micro operation system. It is possible to recognize what has happened, and the cause of the infinite loop can be analyzed by the address data at that time.

As described above, according to the second embodiment, the address abnormality in the nano sequencer 14 of the nano program control unit 2 and the runaway due to the infinite loop can be properly discriminated, and the knowledge of the abnormality factor can be strengthened. .

In the above embodiments, the case where the AND gate 51 and the D flip-flop 50 are applied as the nano program control circuit has been described, but the present invention is not limited to this, and other logic elements or determination circuits may be applied. The address abnormality control circuit is not limited to the JK flip-flop 53, and other equivalent logic elements, latch circuits, etc. can be applied.

〔The invention's effect〕

As described above, according to the first aspect of the invention, the nano-end instruction with the address abnormality flag of the nano instruction causes the address abnormality signal output from the nano program control unit to be held in the simple address abnormality control circuit, and the holding signal Is input to the nano program control circuit and is notified to the micro operation system, it is possible to quickly return to the micro program processing when the nano sequencer address error occurs, and continue execution of the nano program according to the judgment of the micro operation system. If possible, the effect on the system can be reduced, and the cause of the address error in the nano program control unit can be easily recognized by the output of the address error control circuit. RAS The new nano program is prohibited until the latch release command is output from the micro operation system when an address error occurs. There is no occurrence of abnormality, and it is possible to obtain various effects such as being able to hold various information such as the address register at the time of abnormality.

According to the second invention, in addition to the configuration of the first invention, the nanoprogram monitoring circuit monitors the runaway of the nanoprogram, and when the runaway is detected, the microprogram processing is forcibly restored. At the same time, the fact is notified to the operating system of the microprogram, so that when an abnormality occurs in the nanoprogram processing in the operating system of the microprogram, it can be surely recognized whether the address is abnormal or the program is out of control. Moreover, when an abnormality occurs in the nanoprogram processing, the address holding circuit holds the addresses before and after the abnormality, so that the cause of the abnormality can be easily analyzed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIGS. 2 (a) and 2 (b) are explanatory views showing nano-commands for controlling nano-programs, and FIG. 3 shows the structure of a nano-program memory. FIG. 4, FIG. 4 is a block diagram showing a second embodiment of the present invention, FIG. 5 is a block diagram showing a microprocessor having nanoprogram control, FIG. 6 is a block diagram showing a conventional example, and FIG. (a) And (b) is explanatory drawing which shows the nano command for nano program control of a prior art example, respectively. In the figure, 1 is a micro program control unit, 2 is a nano program control unit, 3 is a data processing unit, 11 is a micro sequencer, 12 is a micro program memory, 13 is a micro dedicated pipeline register, 21 is a nano sequencer,
Reference numeral 22 is a nano program memory, 23 is a nano dedicated pipeline register, 50 is a nano program control flip-flop, 51 is a nano program control AND gate, 5
3 is a JK flip-flop, 54 is an OR gate for address abnormality control, 60 is a nano watchdog timer, 61 is an AND gate for nano clock control, and 62 and 63 are address latch registers.

Claims (3)

[Claims] 1. A micro program control unit and a nano program control unit are provided, and in response to a nano program activation request from the micro program control unit, a micro program stop command is output to the micro program control unit and the nano program In a multi-level programming method having a nano program execution control circuit that outputs a nano program execution permission to the control unit, and receives the nano program end signal from the nano program and cancels the micro program stop command and the nano program execution permission, The nano program counter stores nano end instructions with an address abnormality flag at an unused area in the program memory of the nano program control unit and a boundary position of each nano program group, and the nano program counter uses the nano end with an address abnormality flag Outputs an address abnormality signal from the nano program control unit when it reaches the address of the decree, latches the address anomaly signal in the address abnormal control circuit,
An address abnormality notification is output to the nanoprogram control unit, the microprogram stop command and the nanoprogram execution permission are released to forcefully return to the microprogram processing, and an address abnormality is notified to the operating system of the microprogram processing, Until the operating system of the micro program processing outputs the latch state cancellation command to the address abnormality control circuit when the nano program processing can be continuously executed, the address abnormality control circuit is released until the latch state of the address abnormality control circuit is released. A multilevel programming method characterized in that the nanoprogram activation request is locked at the output. 2. The address abnormality control circuit comprises a JK flip-flop to which an address abnormality signal is input to the J input side and a latch state release command of an operating system for microprogram processing is input to the K input side, respectively. The multi-level programming method according to claim 1. 3. A nano program control unit and a nano program control unit are provided, and upon receiving a nano program activation request from the micro program control unit, outputting a micro program stop command to the micro program control unit, and at the same time, the nano program. In a multi-level programming method having a nano program execution control circuit that outputs a nano program execution permission to the control unit, and receives the nano program end signal from the nano program and cancels the micro program stop command and the nano program execution permission, The nano program counter stores nano end instructions with an address abnormality flag at an unused area in the program memory of the nano program control unit and a boundary position of each nano program group, and the nano program counter uses the nano end with an address abnormality flag Outputs an address abnormality signal from the nano program control unit when it reaches the address of the decree, latches the address anomaly signal in the address abnormal control circuit,
An address error notification is output to the nanoprogram control unit to cancel the microprogram stop command and the nanoprogram execution permission to forcibly return to the microprogram process, and to notify the operating system of the microprogram process of the address error. The runaway of the nanoprogram is monitored by the nanoprogram monitoring circuit,
When the nanoprogram monitoring circuit detects a nanoprogram runaway, the state is latched and this is notified to the operating system, and when an address error or nanoprogram runaway occurs, the nanoprogram address before and after that will occur. Is held by the address holding circuit, and when the operating system of the microprogram processing can continue execution of the nanoprogram processing, a latch state release command is output to the address abnormality control circuit and the nanoprogram monitoring circuit to output the address abnormality control circuit. A multi-level programming method characterized in that the nano program activation request is locked by the output of the address abnormality control circuit and the nano program monitoring circuit until the latch state of the nano program monitoring circuit is released.