JPH063906B2 - Address setting method for terminals of time division multiplex transmission equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an address setting method for a terminal of a time division multiplex transmission device.

BACKGROUND ART FIG. 4 shows a system diagram of a time division multiplex transmission device of this type. A plurality of terminal devices 3 each having a unique address are connected to a master device 1 via a dedicated transmission line 2. The base unit 1 periodically calls each terminal device 3 by a time division multiplex signal, and the base unit 1 controls and monitors each terminal device 3.

By the way, conventionally, since the address setting of each terminal device 3 is performed in advance by a dip switch or the like before the construction, the set address cannot be easily changed after the construction. That is, the troublesomeness of the address setting before the construction and the difficulty of the change are the drawbacks of the conventional device of this type.

[Object of the Invention] The present invention has been made in view of the above-mentioned drawbacks, and an object thereof is time division multiplexing in which the address of a terminal device can be set automatically and remotely from a master device and can be easily changed. A method of setting an address of a terminal of a transmission device is provided.

Example 1 Figure 1 [Disclosure of the Invention] Conventionally, focusing on a point to carry out a transmission line 2 and the terminal device 3 ₁ ... connect the feed line construction of a most terminal unit 3 ₁ striking the sender switch 4 ₁ ... is a switching element in series and respectively inserted into the transmission line 2 in .... FIG. 2 is a block diagram of the terminal device 3 of the embodiment, which is connected to the transmission line 2 in front of the switch 4 to perform reception / reproduction of the transmission signal and signal return and transmission for performing mode determination and address determination. Signal transmission / reception processing unit 5 and transmission signal transmission / reception processing unit 5
Based on the transmission signal received / reproduced in step S1, mode determination, address determination, control signal output, and monitoring input acquisition are performed, and at the same time, the transmission signal transmission / reception processing unit 5 returns the monitoring signal to the master unit 1 And an address memory unit 7 including memory elements such as a nonvolatile RAM for writing an address to be set, a magnetic reversal display switch, and a latch contact.
And an address setting processing section 8 for writing a set address in the address memory section 7, and a switch driving section 9 for controlling opening / closing of the switch 4. The switch driving section 9 includes the address setting processing section 8 Is controlled by the logical sum output of the transmission line switch signal S ₁ output from the control monitor signal 6 and the control switch signal S ₂ output from the control monitoring unit 6, and the address setting processing unit 8 transmits and receives the inverted signal of the logical sum output and the transmission signal transmission / reception. The logical product output with the address setting mode signal of the processing unit 5 is used as the setting signal.

FIG. 3 shows the format of the transmission signal used in this embodiment, and includes a start signal ST indicating the beginning of the transmission signal,
It comprises a mode signal MD for control and monitoring, an address signal AD, a control signal CD, and a monitoring band signal WD for setting the timing of returning the monitoring signal.

In each terminal device 3, when a transmission signal having an address setting mode signal as the mode signal MD is transmitted from the master device 1 until a switch signal is generated, the transmission signal transmission / reception processing unit 5 causes the address setting mode regardless of the preset address. When a signal is output and input to the address setting processing unit 8 via the AND gate 10, and the transmission line switch signal S ₁ or the control switch signal S ₂ is output, the output of the AND gate 10 is output by the inverted signal. Is set to "L" to stop the input of the address setting mode signal to the address setting processing section 8. When the address setting mode signal is input, the address setting processing unit 8 takes in the address signal AD received by the transmission signal transmission / reception processing unit 5 and outputs the address signal A.
The data D is written in the address memory unit 7.

At the construction stage, switch 4 ₁ on transmission line 2
... are all in the off state, and it is assumed that the terminal device 3 ₁ closest to the master device 1 is connected to the transmission line 2, and the master device 1 sends the address setting mode signal and the terminal device 3 ₁ concerned. When transmitting a transmission signal and an address signal AD of the address to be set, it causes input from the terminal device 3 _first transmission signal transmission and reception processing section 5, which has received the transmission signal an address setting mode signal to the address setting processing section 1, Address signal AD
To write the address data in the address memory unit 7. When this writing is completed, the transmission line switch signal S ₁ is output from the address setting processing unit 1 via the OR gate 11, and the transmission line switch signal S ₁ drives the switch driving unit to turn on the switch 4 ₁ for transmission. connecting line 2 to the next terminal unit 3 _2. At the same time, the control monitoring section 6 sends a write completion return signal to the master unit 1 via the transmission signal transmission / reception processing section 5. Base unit 1 determines completion of writing in the reception of the return signal, the next stage of the terminal unit 3 _{and second} address signal AD and transmitted along with address setting mode signal, the above-mentioned terminal unit 3 ₁ address setting as well as the terminal device 3 _{Use 2} to set the address. In this way Megutsugi, switch 4 ₁ ... can set the terminal unit 3 ₁ ... address while on the, all of the terminal devices 3 ₁ ... address setting of remotely from the base unit 1 It can be done.

Setting the terminal unit 3 ₁ ... address this manner in an initial state, moves to the normal monitoring control mode, sequentially transmitted to each terminal unit 3 ₁ a transmission signal of the format shown in FIG. 2 cyclically ... accesses the terminal device 3 ₁ ... control is performed to monitor.

Then when changing the setting terminal unit 3 ₁ ... address after address setting, in this embodiment the control signal CD address setting mode by assigning one bit switch 4 ₁ ... for opening and closing the out of control bits It can accept signals.

That back to first the control bits erected to the terminal unit 3 ₁ ... sequentially opening switches 4 ₁ ... a belonging to the address setting previous state if you want to change the terminal unit 3 ₁ ... address of a main unit 1 side The address setting mode signal can be accepted.

Also because it is possible to continue to cut or connect each of the switches 4 ₁ ... by utilizing the main unit 1 side sequentially terminal unit 3 ₁ ... to a from the transmission line 2, the transmission line from the switch 4 ₁ ... charged portion of the abnormal occurrence time 2 short-circuit, open, the entire terminal unit 3 ₁ ... can determine the location of the failure of the system can be prevented from be down.

In addition to the address setting, the use of the above switching elements
For example it can also be used for function setting or the like for determining the terminal unit 3 ₁ ... kind of.

EFFECTS OF THE INVENTION The present invention relates to a switching element serially inserted in a transmission line sent to the next stage to each terminal unit, an address memory unit for rewriting a set address, and an address memory unit. An address setting processing unit that writes a setting address and a switch driving unit that opens and closes the switching element are provided, and the address signal of the transmission signal is received when the address setting mode signal is received from the master unit with the switching element open. Since it is possible to receive the transmission signal of the terminal device of the next stage by closing the switching element while writing it in the address memory unit as the setting address of the terminal device, and stopping accepting the address setting signal in the terminal device, The terminal address can be set from the master unit by remote control, and the individual terminal units can be individually set during construction. Since it is not necessary to set the address by the switch operation etc., the address setting becomes easy, and since the switching element is inserted in the transmission line, the transmission line, the terminal device, etc. when the transmission failure occurs when the switching element is closed. There is an effect that it is possible to discriminate the location of the switching element where the abnormality or the like is closed and prevent the system from going down.

The address of the terminal device can be arbitrarily changed by opening the closed switching element in response to a control signal from the master unit.

[Brief description of drawings]

FIG. 1 is an overall schematic configuration diagram of a time division multiplex transmission device used in an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram of a terminal device of the above,
FIG. 3 is a format diagram of the above transmission signal, and FIG. 4 is an overall schematic configuration diagram of a conventional time division multiplex transmission apparatus.
Base unit, 2 the transmission line, 3 ₁ ... terminal device, 4 ₁ switch, 5
Is a transmission signal transmission / reception processing unit, 6 is a control monitoring unit, 7 is an address memory unit, and 8 is an address setting processing unit.

Claims (2)

[Claims] 1. A master unit and a plurality of terminals are connected via a transmission line, and a transmission signal including a mode signal, an address signal, a control signal, etc. is sequentially and cyclically transmitted from the master unit to the terminals. In a time division multiplex transmission device for monitoring and controlling terminals, a switching element inserted in series to a transmission line sent to the next stage to each terminal, an address memory section for rewriting a set address and an address memory section An address setting processing unit for writing a setting address to the, and a switch driving unit for opening and closing the switching element are provided, and the transmission signal of the transmission signal is received when the address setting mode signal is received from the master unit with the switching element opened. The address signal is written in the address memory as the set address of the terminal and the switching element is closed to transmit the next terminal. Terminal unit address setting method of time division multiplex transmission apparatus characterized by it possible to receive the item, and stops the reception of the address setting signal in the terminal device. 2. A method of setting an address of a terminal unit of a time division multiplex transmission apparatus according to claim 1, wherein the closed switching element can be opened by a control signal from a master unit. .