JPH06339126A - Picture processor - Google Patents

Abstract

PURPOSE:To provide a large display screen even when all of the picture to be displayed is displayed on a display screen with a larger aspect ratio (shorter in the lateral direction) so as to use effectively the display screen. CONSTITUTION:This processor is provided with a frame memory 22 storing picture data by one frame, multipliers 24, 25 reading sequentially two consecutive lines from picture data by one frame stored in the frame memory 22 and multiplying a constant with each of picture data by two lines to be read by one line each, a synchronization control circuit 21 being a multiplier control circuit deciding constants K1, K2 being multipliers in the multipliers 24, 25 and an adder 26 adding picture data by two lines outputted from the multipliers 24, 25 and multiplied by a constant to obtain picture data of a new line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for displaying image data on a display screen having an aspect ratio different from that of the image data.

[0002]

2. Description of the Related Art A display screen of a general NTSC television receiver has an aspect ratio of 3: 4, while a display screen also called a so-called cinema size has an aspect ratio of 9:16. Therefore, if an attempt is made to display the entire cinema size display image on the NTSC display screen as it is, as shown in FIG. 4, there is a wasteful area above and below the display screen that is not used for display, as shown by hatching in the drawing. Not only that, but there is also the problem that the displayed image becomes smaller than the size of the screen.

FIG. 5 shows a circuit configuration of a general liquid crystal television receiver. Television radio waves received by an antenna 11 are sent to a tuner 12. The tuner 12 selects a TV radio wave of a designated channel from the received radio waves, converts it into an intermediate frequency signal, and sends it to the television linear circuit 13.

The television linear circuit 13 amplifies the intermediate frequency signal from the tuner 12, then video-detects the video signal to obtain a video signal, and performs chroma signal processing on the obtained video signal to obtain R, G, B color signals. Is obtained and sent to the A / D conversion circuit 15, the composite sync signal in which the horizontal sync signal and the vertical sync signal are superimposed is sent to the sync control circuit 14, and the audio signal is sent to the audio detection circuit 19.

The sync control circuit 14 generates various timing signals for displaying an image from the composite sync signal to generate the A / D signal.
It outputs to each of the conversion circuit 15, the common electrode drive circuit 16, and the segment electrode drive circuit 17.

The A / D conversion circuit 15 digitizes the R, G, B color signals sent from the television linear circuit 13 by using the timing signal from the synchronization control circuit 14 as a sampling clock, and digitizes each color. The signal is output to the segment electrode drive circuit 17.

However, the common electrode drive circuit 16 and the segment electrode drive circuit 17 both drive and control the display panel 18, and the common electrode drive circuit 16 includes the synchronization control circuit 14
The segment electrode driving circuit 17 drives the common electrodes sequentially by the timing signal from the A / D conversion circuit 15, and the segment electrode driving circuit 17 drives the segment electrodes by each color signal sent from the A / D conversion circuit 15 in synchronization with the timing signal from the synchronization control circuit 14. Thus, a television program of a color image is displayed and output on the liquid crystal display panel 18.

The voice detection circuit 19 is a TV linear circuit.
The sound signal from 13 is detected, and the detected sound signal is output to the speaker 20 to emit sound. With such a circuit configuration, when the entire cinema size display image is displayed as it is on the NTSC display screen as shown in FIG. 4, the liquid crystal display panel 18 is provided with 1 / each of the upper end side and the lower end side. 8 common electrodes are not actually driven, but only the central 3/4 common electrodes are driven by the common electrode drive circuit 16, while the segment electrode drive circuit 17 fully gradations the segment electrodes of the liquid crystal display panel 18. It is driven to display a color image.

[0009]

Therefore, as described above, the ⅛ regions on the upper end side and the lower end side of the display screen of the liquid crystal display panel 18 are not used for display, and the liquid crystal display panel 18 is not used.
The image displayed in the center 3/4 of the screen will also be smaller than the size of the screen.

The present invention has been made in view of the above situation, and an object of the present invention is to display an image to be displayed, for example, when displaying an entire cinema size image on an NTSC display screen. To provide an image processing apparatus capable of obtaining a large display image by effectively utilizing the display screen even when displaying the whole on a display screen having an aspect ratio larger (horizontally shorter) than the image. is there.

[0011]

That is, according to the present invention, a frame memory for storing one frame of image data and two consecutive lines of one frame of image data stored in the frame memory are sequentially read out. A multiplier for multiplying the read image data of two lines by one line each, a synchronous control circuit as a multiplication control circuit for determining a constant value that is a multiplier in this multiplier, and the output from the multiplier. And an adder that obtains image data of a new line by adding image data of two lines that are each multiplied by a constant.

[0012]

With the above-described structure, the lines can be interpolated and the image data can be stretched in the vertical direction and displayed on the entire display screen. Even when displaying on a large (horizontally short) NTSC display screen, a large display image can be obtained by effectively utilizing the display screen.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a liquid crystal television receiver will be described below with reference to the drawings. FIG. 1 shows the circuit configuration, and since the basic configuration is the same as that shown in FIG. 5, the same parts are designated by the same reference numerals and the description thereof will be omitted.

However, the sync control circuit 21 which receives the composite sync signal from the television linear circuit 13 generates various timing signals for image display from the composite sync signal to generate the A / D conversion circuit 15 and the common electrode drive circuit. While outputting to 16 and the segment electrode drive circuit 17, the frame memories 22 and 1 for storing image data for one frame
The timing signal is also output to the line memory 23 that stores the image data for the lines, and multipliers K1 and K2 corresponding to the line timing are output to the multipliers 24 and 25, respectively.

The A / D conversion circuit 15 is a television linear circuit 13
The R, G, B color signals sent from the device are digitized, and the digitized color signals are converted to the frame memory.
Output to 22.

The frame memory 22 is an A / D conversion circuit.
Image data by each color signal from 15 is stored for one frame corresponding to one display screen of the liquid crystal display panel 18, and the stored image data is stored from above by a timing signal from the frame memory 22. The data for one line is sequentially read out to the line memory 23 and the multiplier 25.

The multiplier 25 multiplies the image data for one line sent from the frame memory 22 by the multiplier value K2 (0≤K2≤1) from the synchronization control circuit 21 and obtains the product. The image data is output to the adder 26.

The line memory 23 stores one line of image data read from the frame memory 22 in synchronization with a timing signal from the synchronization control circuit 21,
Read to the multiplier 24.

The multiplier 24 is for the synchronization control circuit for the image data for one line sent from the line memory 23.
Multiplier value K1 from 21 (0≤K1≤1, K1 + K2 = 1)
And the image data that is the product is output to the adder 26.

In the adder 26, the image data for one line subjected to the multiplication process sent from the multiplier 24 and the image data for one line subjected to the multiplication process sent from the multiplier 25 are added to each other. Image data for one line is newly generated, and the generated image data is sent to the segment electrode drive circuit 17. The segment electrode drive circuit 17 drives each segment electrode of the liquid crystal display panel 18 by gradation based on the timing signal from the synchronization control circuit 21 based on the image data from the adder 26.

At this time, the common electrode drive circuit 16 uses the timing signal from the synchronization control circuit 21 to drive the liquid crystal display panel 18
The common electrodes of are selectively driven. Next, in the configuration of the above-mentioned embodiment, all the cinema size image data is converted to NTSC.
The operation of displaying on the display screen of the liquid crystal display panel 18 of the system will be described.

FIG. 2 mainly shows the processing contents of each data from the frame memory 22 to the adder 26. The sync control circuit 21 extracts a horizontal sync signal from the composite sync signal sent from the television linear circuit 13, and uses the extracted horizontal sync signal as a timing signal for the common electrode drive circuit 16
Then, as shown in FIG. 2A, the common electrodes of the liquid crystal display panel 18 are sequentially driven to scan one line unit from the uppermost line on the display screen.

At this time, the frame memory 22 for storing the image data for one frame stores the image data for each line in sequence in the line memory 23 and the line memory 23 according to the timing signal of the synchronization control circuit 21, as shown in FIG. It is output to the multiplier 25, and is particularly “1 + 3n (n = 0, 1, 2, ...)”
The second line, ie 1st, 4th, 7th, 10th
The image data of the second line is output continuously twice.

As shown in FIG. 2C, the line memory 23 delays the image data for one line output from the frame memory 22 by one horizontal period according to the timing signal from the synchronization control circuit 21 and multiplies it. Output to 24.

However, in the multiplier 24 to which the image data for one line delayed by one horizontal period is input via the line memory 23, the synchronous control circuit as shown in FIG.
Multiplier value K1 input from 21 is "0""0.25"
"0.5""0.75""0""0.25""0.5"
This multiplier value K changes cyclically to "0.75" ...
In 1, the image data for one line is multiplied and the image data as a product obtained as a result of the operation is output to the adder 26.

On the other hand, in the multiplier 25 to which the image data for one line is directly input from the frame memory 22, the multiplier 25 shown in FIG.
As shown in, the multiplier value K2 input from the synchronous control circuit 21 is "1""0.75""0.5""0.25""1".
Since it cyclically changes to "0.75", "0.5", "0.25", etc., the image data for one line is multiplied by this multiplier value K2, and the product obtained as the result of the operation is multiplied. The image data is similarly output to the adder 26.

Therefore, the addition output of the adder 26 is as shown in FIG.
As shown in (6), the image data of the "1" th line (hereinafter referred to as "line 1") is directly superimposed, and the image data of "line 1" and "line 2" are superposed at appropriate ratios. , Image data of "line 2" and "line 3" superimposed at an appropriate ratio, image data of "line 3" and "line 4" superimposed at an appropriate ratio,
The image data of the "4" th line is as it is. The image data for each line output from the adder 26 is sequentially sent to the segment electrode drive circuit 17 to drive the segment electrodes of the liquid crystal display panel 18 in gradation.

As a result, as shown in FIG. 3, in the liquid crystal display panel 18, the total number of lines is about 4 / from the original image data.
With the image data increased three times, it is possible to perform display by using the entire display screen, and it is possible to stretch the image in the vertical direction and perform display in which the screen is effectively used.
In particular, it is effective when the input image is an image such as characters. Needless to say, the multiplier values K1 and K2 are not limited to those in this embodiment.

[0029]

As described above, according to the present invention, all the images to be displayed have a larger aspect ratio than that of the images, as in the case of displaying all the cinema size images on the NTSC display screen. Even when it is displayed on a display screen (horizontally short), it is possible to provide an image processing apparatus that can effectively use the display screen to obtain a large display image.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a diagram mainly showing the content of each data from a frame memory to an adder in FIG.

FIG. 3 is a diagram showing an original image and image data after conversion according to the embodiment in comparison.

FIG. 4 is a diagram exemplifying a display state when an entire cinema size image is displayed on an NTSC display screen.

FIG. 5 is a block diagram showing a circuit configuration of a general liquid crystal television receiver.

[Explanation of symbols]

11 ... Antenna, 12 ... Tuner, 13 ... Television linear circuit,
14, 21 ... Synchronous control circuit, 15 ... A / D conversion circuit, 16 ... Common electrode drive circuit, 17 ... Segment electrode drive circuit, 18 ... Liquid crystal display panel, 19 ... Audio detection circuit, 20 ... Speaker, 22 ...
Frame memory, 23 ... Line memory, 24, 25 ... Multiplier,
26 ... Adder.

Claims (1)

[Claims] 1. An image storage unit for storing image data for one frame, a reading unit for sequentially reading out two consecutive lines from the image data for one frame stored in the image storage unit, and the reading unit. Multiplying means for multiplying the image data for two lines read in step 1 by a constant for each one line, multiplication control means for determining a constant value that is a multiplier in this multiplying means, and multiplying by a constant respectively output from the multiplying means. An image processing apparatus comprising: an addition unit that adds the generated image data of two lines to obtain the image data of one line.