JPH06339081A - Driving method for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To obtain a driving method for solid-state image pickup element where the voltage of a reading pulse for reading the signal charge from a photosensor to a vertical transfer register is lowered without lowering an antiblooming characteristic and the making a low voltage of a device is possible. CONSTITUTION:A CCD solid-state image pickup element has a vertical OFD (overlow drain) structure. When signal charge is read from a photosensor 21 to a vertical transfer register 23, clock voltage phiOFB impressed on a P well 8 functioning as an overflow barrier is made to be a low level by synchronizing with the reading pulse of signal charge and the potential of the photosensor 21 is made shallow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state image pickup device, and more particularly to a method for driving a solid-state image pickup device having an overflow drain (OFD) structure when reading signal charges from each sensor unit to a vertical transfer unit.

[0002]

2. Description of the Related Art FIG. 7 is an overall configuration diagram showing a typical configuration example of an interline transfer CCD solid-state image pickup device.
In FIG. 7, a large number of photosensors (sensor portions) 21 that are two-dimensionally arranged in a matrix and perform photoelectric conversion, and signals that are arranged in each vertical column of these photosensors 21 and that are read out through a read gate 22. An image pickup unit 24 is configured by a vertical transfer register (vertical transfer unit) 23 that transfers charges in the vertical direction. The vertical transfer register 23 is
For example, transfer is driven by four-phase vertical transfer clocks φV1 to φV4.

The signal charges read out to the vertical transfer register 23 are sequentially transferred to the horizontal transfer register 25 in units corresponding to one scanning line. The signal charge for one scan line is
The charges are sequentially transferred in the horizontal direction by the horizontal transfer register 25 and supplied to the charge detection unit 26. Horizontal transfer register 25
Are driven by, for example, two-phase horizontal transfer clocks φH1 and φH2. The charge detection unit 26 is composed of, for example, a floating diffusion amplifier, detects the signal charge transferred by the horizontal transfer register 25, converts the signal charge into a signal voltage Vout, and outputs the signal voltage Vout.

In this type of CCD solid-state image sensor, the gate electrode of the read gate 22 is connected to the vertical transfer register 23.
Of the first phase (φV1) and the third phase (φV3) transfer electrodes, the four-phase vertical transfer clocks φV1 to φV are used as shown in the timing chart of FIG.
Of the four vertical transfer clock .phi.V1, .phi.V3 ternary level _{(V L, V H, V} T) taking. Then, the highest voltage pulse V _T is sent from the photo sensor 21 to the vertical transfer register 2
3 is used as a read pulse for reading the signal charge. By applying this read pulse to the gate electrode of the read gate 22, the signal charge accumulated in the photosensor 21 is read to the vertical transfer register 23 via the read gate 22.

[0005]

[SUMMARY OF THE INVENTION However, in the CCD solid-state imaging device having the above configuration, the vertical transfer clock .phi.V1, by φV3 takes three values levels, forced to set the voltage V _T of the read pulse to a high level In the normal case, it is difficult to lower the voltage V _{T of the} read pulse without lowering the anti-blooming characteristic.
There was a problem that power consumption would be high. In particular, in a CCD solid-state image sensor having an insufficient anti-blooming characteristic, under the condition that the anti-blooming characteristic is ensured, the voltage V _{T of the} read pulse is set high in order to sufficiently read the signal charge accumulated in the photosensor 21. Power consumption will increase.

The present invention has been made in view of the above problems, and an object thereof is to reduce the voltage of a read pulse for reading a signal charge from a photosensor to a vertical transfer register to reduce the anti-blooming characteristic. Another object of the present invention is to provide a method for driving a solid-state image sensor, which is capable of lowering the voltage of the device.

[0007]

In order to achieve the above object, a method of driving a solid-state image pickup device according to the present invention comprises a large number of sensor units arranged two-dimensionally in a matrix for photoelectric conversion, and these sensor units. In a solid-state imaging device including an image pickup unit having a vertical transfer unit arranged in each vertical column and vertically transferring the signal charge read from the sensor unit, when reading the signal charge from the sensor unit to the vertical transfer unit It is characterized in that the signal charge is read out and driven while the potential of the sensor section is made shallow.

[0008]

In the solid-state imaging device having the OFD structure, when the signal charge is read from the sensor unit to the vertical transfer unit, the clock voltage applied to the P well functioning as the overflow barrier is lowered in synchronization with the signal charge read pulse. Level. As a result, the potential of the overflow barrier becomes shallower due to the modulation, and the potential of the sensor section becomes shallower accordingly. As a result, the potential difference between the sensor unit and the vertical transfer unit becomes large, and the electric field from the sensor unit to the vertical transfer unit becomes strong. Therefore, even if the voltage of the read pulse is lower than the conventional one, the signal charge is sufficiently read. Is possible.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a cross-sectional structure diagram around a sensor portion in a CCD solid-state imaging device having a vertical OFD (overflow drain) structure. In the figure, the same parts as those in FIG. 7 are denoted by the same reference numerals. In FIG. 1, a photosensor 21 that performs photoelectric conversion includes a hole storage layer 2 made of a P ⁺ -type impurity and shallowly formed on the surface side of an N-type silicon substrate 1.
And a signal charge storage layer 3 made of N ⁺ type impurities formed under the hole storage layer 2. Further, a channel stop region 4 made of a P ⁺⁺ type impurity is formed adjacent to the hole storage layer 2.

The vertical transfer register 23 includes a signal charge transfer region 5 made of N ⁺ -type impurities formed on the substrate surface side,
A transfer electrode 6 is formed thereabove with an insulating layer (not shown) made of a silicon oxide film SiO ₂ interposed therebetween. P ⁺ impurity region 7 is provided between the photo sensor 21 and the vertical transfer register 23 are formed, the P ⁺ -type impurity region 7 acts as a readout gate 22. The gate electrode of the read gate 22 is the vertical transfer register 23.
, The transfer electrodes 6 of the first phase (φV1) and the third phase (φV3) are also used. Further, a P-well 8 is formed as an overflow barrier in the intermediate region of the N-type silicon substrate 1, and a vertical overflow drain structure for sweeping out signal charges accumulated in the photosensor 21 via the P-well 8 to the substrate side. Is taking.

FIG. 2 is a timing chart of vertical transfer clocks .phi.V1 to .phi.V4 for driving the vertical transfer register 23 in four phases and a clock voltage .phi.OFB applied to the P well 8 functioning as an overflow barrier (OFB). Of the four-phase vertical transfer clocks φV1 to φV4,
As described above, the vertical transfer clocks φV1 and φV3 have three levels of V _L , V _H , and V _T because the transfer electrodes 6 of the first and third phases also serve as the gate electrodes of the read gate 22.
Taking the value level, the voltages V _L and V _H become transfer pulses for vertical transfer, and the highest voltage V _T is the photosensor 21.
Is a read pulse for reading the signal charge from the vertical transfer register 23 to the vertical transfer register 23.

FIG. 3A shows the channel potential in the cross section of FIG. 1 during charge accumulation, and FIG. 3B shows the potential of the sensor portion 21 in the depth direction. In this charge storage state, the incident light is photoelectrically converted into a charge and stored in the signal charge storage layer 3 of the photosensor 21. The accumulated signal charges are transferred to the vertical transfer clock φV.
When the read pulse of 1, φV3 is applied to the transfer electrode 6, the potential of the read gate 22 becomes deeper, and the read gate 22 reads the potential to the vertical transfer register 23.

The present invention is characterized by the driving method at the time of reading the signal charge. That is, P well 8
The clock voltage .phi.OFB applied to is set to the low level in synchronization with the read pulses of the vertical transfer clocks .phi.V1 and .phi.V3. FIG. 4 (A) shows the channel potential in the cross section of FIG. 1 and FIG. 4 (B) shows the potential in the depth direction of the sensor portion 21 during the charge reading. Figure 4
As is clear from the above, when the signal charge is read out, the P well 8
By setting the clock voltage φOFB applied to the low level to a low level, the potential of the overflow barrier (P well 8) becomes shallow due to the modulation, and as a result, the photosensor 2
The potential of 1 also becomes shallow.

As described above, when the signal charge is read from the photosensor 21 to the vertical transfer register 23, the photosensor 21 and the vertical transfer register 23 are read by driving the signal charge while making the potential of the photosensor 21 shallow. The potential difference between the two becomes larger than before. If this potential difference is large, the photo sensor 2
Since the electric field from 1 to the vertical transfer register 23 becomes strong, the signal charge can be sufficiently read even if the voltage V _{T of the} read pulse is lower than that of the conventional one.

According to this, the voltage of the read pulse V _T can be lowered without deteriorating the anti-blooming characteristic, so that the device voltage can be lowered.
In FIG. 4, the broken line indicates the case where the voltage V _{T of the} read pulse is lowered without reading the potential of the photosensor 21 shallow when reading the signal charge. In this case, the potential of the read gate 22 becomes shallower than the potential of the photosensor 21, which causes the signal charge from the photosensor 21 to be left unread, and a higher read pulse voltage V _T is obtained. It must be applied and requires a voltage higher than the voltage V _T of the read pulse in the driving method according to the present invention.

In the above embodiment, the clock voltage .phi.OFB applied to the P well 8 functioning as an overflow barrier is set to a low level at the read pulse generation timing, as is clear from the timing chart of FIG. As shown in the timing chart of FIG. 5, the first
The third phase (φV1) is synchronized with the phase (φV1) read pulse.
3) A certain period T including the read pulse generation timing
However, the same effect as the above case can be obtained. In the above-described embodiment, in the overflow drain structure, the potential of the photo sensor 21 is made shallow by applying the clock voltage φOFB to the P well 8. The voltage of the substrate pulse φSUB to be applied may be set to the low level in synchronization with the read pulse V _T , and the same effect as the above case can be obtained.

Furthermore, in the above-mentioned embodiment, the case where the present invention is applied to the CCD solid-state image pickup device having the vertical type OFD structure has been described, but the present invention is similarly applied to the CCD solid-state image pickup device having the horizontal type OFD structure. obtain. In Figure 6,
FIG. 3 is a cross-sectional structure diagram around a sensor unit in a CCD solid-state imaging device having a horizontal OFD structure. In the figure, the overflow barrier region 11 is formed continuously by the P-type impurities next to the photosensor 21, and the overflow drain region 12 is further formed next by the N-type impurities.

In the solid-state image pickup device having the horizontal OFD structure having the above structure, when the signal charge is read from the photosensor 21 to the vertical transfer register 23, the signal charge is arranged above the overflow barrier region 11 in synchronization with the read pulse. A negative clock voltage is applied to the gate electrode 13. According to this, the potential of the overflow barrier region 11 becomes shallow due to the modulation, and the potential of the photosensor 21 can be made shallow when the signal charge is read from the photosensor 21, so that it is similar to the case of the above embodiment. The effect can be obtained.

[0019]

As described above, according to the present invention,
In the solid-state imaging device having the OFD structure, when the signal charge is read from the sensor unit to the vertical transfer unit, the signal charge is read out and driven while the potential of the sensor unit is made shallow. Since the potential difference between the two becomes large and the electric field from the sensor section to the vertical transfer section becomes strong, it is possible to sufficiently read the signal charge even when the voltage of the read pulse is lower than the conventional one, and as a result, the device The voltage can be achieved.

[Brief description of drawings]

FIG. 1 is a cross-sectional structural diagram around a sensor unit in a vertical OFD structure.

FIG. 2 is a timing chart (No. 1) for explaining the operation of the driving method according to the present invention.

FIG. 3 is a channel potential diagram during charge storage.

FIG. 4 is a channel potential diagram at the time of reading charges.

FIG. 5 is a timing chart (No. 2) for explaining the operation of the driving method according to the present invention.

FIG. 6 is a cross-sectional structural diagram around a sensor unit in a horizontal OFD structure.

FIG. 7 is an overall configuration diagram showing a typical configuration example of an interline transfer CCD solid-state imaging device.

FIG. 8 is a timing chart of vertical transfer pulses φV1 to φV4.

[Explanation of symbols]

 2 hole storage layer 3 signal charge storage layer 5 signal charge transfer region 6 transfer electrode 8 P well (overflow barrier) 21 photosensor 22 read gate 23 vertical transfer register 24 image pickup unit 25 horizontal transfer register

Claims (3)

[Claims] 1. A plurality of sensor units arranged two-dimensionally in a matrix to perform photoelectric conversion, and vertical transfer for vertically transferring signal charges read from the sensor units arranged in each vertical column of these sensor units. A method of driving a solid-state image sensor including an image pickup unit having a sensor unit, wherein when the signal charge is read from the sensor unit to the vertical transfer unit, the signal charge is read and driven while the potential of the sensor unit is made shallow. A method for driving a solid-state imaging device, which is characterized by being performed. 2. A solid-state imaging device having an overflow drain structure for sweeping out signal charges of the sensor section through an overflow barrier section, wherein the signal charge is read from the sensor section to the vertical transfer section in synchronization with the readout pulse. The method for driving a solid-state imaging device according to claim 1, wherein a clock voltage is applied to the overflow barrier section. 3. The method for driving a solid-state image pickup device according to claim 2, wherein a clock voltage is applied to the substrate in synchronization with a read pulse of signal charges from the sensor unit to the vertical transfer unit.