JPH0633431Y2 - Aging device for IC - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to an aging device for an IC, particularly in an oven.
The present invention relates to an IC aging device for aging.

[Conventional technology]

As shown in FIG. 3, the conventional IC aging apparatus has a plurality of substrates 4-1 to 4-n (n is an integer of 2 or more) in the constant temperature bath 1.
And a plurality of ICs to be aged are mounted on each of the boards 4-1 to 4-n, and the power source 5 and the signal source 6 and the main board connectors 7-1 to 7-1 of each board 4-1 to 4-n. -N was connected via the main power supply wiring 11, the main signal wiring 12, and the main ground wiring 13 to supply power and signals.

[Problems to be solved by the invention]

In the conventional IC aging device described above, the connection between each board and the power supply and signal source is only one system of the main connection system, so if a connection failure occurs in the main board connector of each board, The IC mounted on the board has a drawback that it is not aged.

[Means for solving problems]

The IC aging device of the present invention comprises a constant temperature bath, a plurality of substrates on which ICs to be aged accommodated in the constant temperature bath are mounted, a power source and a signal source supplied to the substrate from outside the constant temperature bath, and the substrate. It has a main connection system including a main wiring for connecting the power supply and the signal source, and a sub connection system for connecting the power supply line and the signal line of each substrate in parallel.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention.

As shown in FIG. 1, a constant temperature bath 1 capable of controlling the temperature inside the bath and a plurality of sockets CN _{1 to} CN _m (m ≧ 2 integers) housed in the constant temperature bath 1 and mounted with ICs to be aged. From the outside of the constant temperature bath 1 to the substrates 2-1 to 2-n
A power source 5 and a signal source 6 for supplying power and signals to 2-n;
Main board connector 7-1 provided on boards 2-1 to 2-n
To 7-n, sub-board connectors 8-1 to 8-n, power supply 5, signal source 6 and main board connectors 7-1 to 7-n, main power supply wiring 11, main symbol wiring 12 and main ground The wiring 13 includes a sub-power supply wiring 14, a sub-signal wiring 15 and a sub-ground wiring 16 which connect the sub-board connectors 8-1 to 8-n in parallel and connect the power source 5 and the signal source 6.

As shown in FIG. 1, each of the boards 2-1 to 2-n, the power supply 5 and the signal source 6 is connected to each of the main board connectors 7-1 to 7-n, the main power supply wiring 11, the main signal wiring 12 and the main ground. The boards are connected in parallel by the main connection system consisting of the wiring 13, and the boards 2-1 to 2-n, the power source 5 and the signal source 6 are connected to the sub-board connectors 8-1 to 8-n, the sub-power supply wiring 14, and the sub-signal wiring. They are connected in parallel by a sub-connection system consisting of 15 and sub-ground wiring 16.

Therefore, even if a contact failure occurs in any of the main board connectors 7-1 to 7-n in the main connection system, power and signals are supplied to the aged IC by the sub connection system, and aging is performed. be able to.

Next, FIG. 2 is a circuit diagram of a second embodiment of the present invention.

As shown in FIG. 2, in the second embodiment, the sub-board connectors of the first embodiment shown in FIG.
The sockets CN ₁ of -1 to 3-n are connected in parallel by the sub power supply wiring 17, the sub signal wiring 18, and the sub ground wiring 19.

The sub-power supply wiring 17, the sub-signal wiring 18, and the sub-ground wiring 19 are not directly connected to the power supply 5 and the signal source 6, but they are connected in parallel between the respective boards, which is the same as in the first embodiment. It can cope with poor contact of the board connector.

The second embodiment has an advantage that the sub-board connector can be omitted.

[Effect of device]

As described above, according to the present invention, by connecting a plurality of boards in parallel by a sub connection system other than the main connection system, even if a connection failure occurs in the main connection system, power and signals are supplied by the sub connection system. Therefore, there is an effect that aging can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional IC aging device. 1 ... Constant temperature bath, 2-1 to 2-n, 3-1 to 3-n, 4-1 to 4
-N ... Substrate, 5 ... Power supply, 6 ... Signal source, 7-1 to 7
-N ... Main board connector, 8-1 to 8-n ... Sub board connector, 11 ... Main power supply wiring, 12 ... Main signal wiring, 13 ...
Main ground wiring, 14, 17 …… Sub power supply wiring, 15, 18 …… Sub signal wiring, 16, 19 …… Sub ground wiring, CN _{1 to} CN _m …… Socket.

Claims (1)

[Scope of utility model registration request] 1. A constant temperature bath, a plurality of substrates mounted with ICs to be aged accommodated in the constant temperature bath, a power source and a signal source supplied to the substrate from outside the constant temperature bath, the substrate, the power source and signals. An aging device for an IC, comprising: a main connection system including a main wiring for connecting a power source; and a sub connection system for connecting a power supply line and a signal line of each of the substrates in parallel.