JPH06332933A - Method and circuit for discrete cosine transformation - Google Patents

Abstract

PURPOSE:To provide a method for enabling discrete cosine transformation(DCT) at high speed with small circuit scale. CONSTITUTION:Plural cosine functions contained in respective transforming formulas for calculating a DCT coefficient from pixel data f0-f7 are replaced with plural coefficients. The respective coefficients contain the square power form of '2' as much as possible. The ratio of plural coefficients in the respective transformation formulas after the replacement is set equally to the ratio of plural cosine functions in the respective transformation formulas before the replacement. Transformation data F0'-F7' are calculated by calculating the sum of products between respective pixel data and respective coefficients in the respective transformation formulas while using the shift and addition of data. The DCT coefficient is provided by multiplying a constant to the respective transformed data F0'-F7'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a discrete cosine transform method and a discrete cosine transform circuit used for image data compression.

[0002]

2. Description of the Related Art Image data contains a very large amount of information. Therefore, it is not practical to process the image data as it is in terms of memory capacity and communication speed. Therefore, image data compression technology is important.

J is one of the international standards for image data compression.
There is PEG (Joint Photographic Expert Group). J
In PEG, a discrete cosine transform (hereinafter referred to as DCT) method that performs lossy encoding and DPCM in a two-dimensional space
A lossless coding method that performs (Differential PCM) is adopted. The DCT method image data compression will be described below.

FIG. 18 is a block diagram showing the basic structure of a system for executing the DCT method.

On the encoding side, the DCT device 100 performs DCT processing on the input original image data and outputs DCT coefficients. The quantizer 200 has a quantization table 400.
, The DCT coefficient is quantized and a quantized DCT coefficient (hereinafter referred to as a quantized DCT coefficient) is output. The entropy encoder 300 refers to the encoding table 500, performs entropy encoding processing on the quantized DCT coefficient, and outputs compressed data. The Huffman coding method is used as the entropy coding method.

On the decoding side, the entropy decoder 600
Performs entropy decoding processing on the compressed data with reference to the encoding table 500, and outputs the quantized DCT coefficient. The inverse quantizer 700 refers to the quantization table 400 to perform inverse quantization processing on the quantized DCT coefficient,
Output the T coefficient. The inverse DCT device 800 performs inverse DCT processing on the DCT coefficient and outputs reproduced image data.

Next, the DCT method will be described. First, Fig. 1
As shown in FIG. 9, the image data is divided into a plurality of 8 × 8 pixel blocks. As shown in FIG. 20, the value of each pixel data in one 8 × 8 pixel block is set to P _XY (X, Y = 0,
…, 7). Here, X and Y represent the position of the pixel data in the block.

Two-dimensional DCT according to equation 1 is performed on each of the divided 8 × 8 pixel blocks.

[Equation 1]

Here, S _UV (U, V = 0, ..., 7) represents the DCT coefficient, and U and V represent the position of the DCT coefficient. When U = V = 0, C _U = C _V = 1 / √2, and in other cases, C _U = C _V = 1. further,
If the bit precision of the pixel data P _XY is 8 bits, L
_S = 128 and the bit precision of pixel data P _XY is 1
In the case of 2 bits, L _S = 2048.

As a result of the DCT processing, 64 DCT coefficients S
_UV is obtained. The DCT coefficient S _{0 0} is called a DC coefficient, and the remaining 63 DCT coefficients are called AC coefficients. D
The C coefficient represents the average value (DC component) of the 8 × 8 pixel data. As shown in Expression 1, the expected value of the DC coefficient is level-shifted to 0 by subtracting L _S from each pixel data P _XY .

As shown in FIG. 20, the upper left and lower right of the DCT processed block are DCT coefficients S _{0 0} and
Corresponds to the S _{7 7.} As the DCT-processed block progresses from left to right, it contains many high-frequency horizontal frequency components, and as it progresses from top to bottom, it contains many high-frequency vertical frequency components.

On the other hand, by the inverse DCT processing shown in equation 2, DC
64 pixel data P _XY (X, Y = from the T coefficient S _UV
0, ..., 7) can be obtained.

[Equation 2]

As shown in equation 2, each pixel data has L
By adding _S , the level shift amount is restored.

As shown in FIG. 21, the two-dimensional DCT is 2
One one-dimensional DCT circuit 110, 130 and a transport tension memory 120. One-dimensional D
The CT circuit 110 performs the one-dimensional DCT by the equation 3 on the pixel data f _X , and writes the one-dimensional DCT coefficient F _U indicating the result in each row of the transport tension memory 120.

[Equation 3]

In Expression 3, X = 0, 1, 2, ..., 7 and U = 0, 1, 2 ,. If U = 0,
C _U = 1 / √2, and when U ≠ 0, C _U = 1.

The one-dimensional DCT circuit 130 is a one-dimensional DCT circuit stored in each column of the transport tension memory 120.
One-dimensional DCT is performed on the T coefficient F _U , and the result is output as the DCT coefficient S _UV . Inverse one-dimensional DC
T is represented by Equation 4.

[Equation 4]

The DCT coefficient S _UV is linearly quantized by the equation (5) using the quantization table Q _UV different for each coefficient position, and the quantized DCT coefficient r _UV is obtained.

## EQU00005 ## r _UV = round (S _UV / Q _UV ) round means integerization to the nearest integer.

On the decoding side, inverse quantization is performed. When the quantized DCT coefficient obtained by the Huffman decoding is r _UV , inverse quantization is performed by the equation 6.

[Equation 6] S _UV = r _UV × Q _UV

The image quality can be controlled by changing the value of the quantization table Q _UV . If the value of the quantization table Q _UV is set small, the quantized DCT coefficient r
_{The UV} value becomes large, and it is possible to encode a high-quality image. On the contrary, when the value of the quantization table Q _UV is set to be large, the value of the quantized DCT coefficient r _UV becomes small and the amount of encoded information decreases, but the image quality deteriorates. In this way, by changing the value of the quantization table Q _UV , the image quality and the coding information can be freely controlled.

Here, the Chen algorithm for calculating the one-dimensional DCT coefficient F _U shown in Equation 3 will be described with reference to FIGS.

Equation 3 can be expanded into eight conversion equations (E1) to (E8) shown in FIG. In FIG. 22, F _{0 to} F ₇ are one-dimensional DCT coefficients (hereinafter referred to as DCT coefficients).
(Referred to as coefficients), and f _{0 to} f ₇ represent pixel data.

In the conversion equations (E1) to (E8), the coefficients C1 to C7 are ¼ · cos (1 · π / 16), respectively.
.About.1 / 4.cos (7..pi. / 16) is shown. Figure 2
The conversion equations (E1) to (E8) of No. 2 are represented by the determinant shown in FIG. As is clear from FIGS. 22 and 23, f ₀ + f ₇ , f ₁ + f ₆ , f ₂ + f ₅ , f ₃ + f
_{4, f 0 -f 7, f} 1 -f 6, f 2 -f 5, f 3 -f 4
, The DCT coefficient F ₀
Each of ~ F ₇ is represented by the sum of products of four coefficients and four sets of variables. Therefore, 32 multipliers are required to calculate the DCT coefficients F _{0 to} F ₇ .

Further, C3 = C4 (C1 + C7), C5 =
C4 (C1-C7), C1 = C4 (C3 + C5), C7
= C4 (C3-C5), the conversion equations (E5) to (E8) shown in FIG. 22 are transformed into the conversion equations (E5 ′) to (E8 ′) shown in FIG.

Conversion equations (E1) to (E) shown in FIG.
4) and conversion formulas (E5 ') to (E5') shown in FIG.
8 ') is represented by the flow bluff (butterfly chart) of FIG. In FIG. 25, a circle indicates addition. The coefficient attached to each line represents multiplication of the coefficient.

G ₀ = f ₀ + f ₇ , G ₁ = f ₁ + f ₆ , G
₂ = f ₂ + f ₅ , G ₃ = f ₃ + f ₄ , G ₄ = f ₃ −
_{f 4, G 5 = f 2} -f 5, G 6 = f 1 -f 6, G 7 = f
It is ₀ -f _7. In addition, H ₀ = G ₀ + G ₃ , H ₁ = G ₁
+ G ₂ , H ₂ = G ₁ -G ₂ , and H ₃ = G ₀ -G ₃ .
_{H 4 = G 4, H 5} = -C4 · G 5 + C4 · G 6, H 6 =
_{C4 · G 5 + C4 · G} 6, H 7 = a G _7.

Further, F ₀ = C4 · H ₀ + C4 · H ₁ ,
_{F 4 = C4 · H 0 -C4} · H 1, F 2 = C6 · H 2 + C
2 · H _3, an _{F 6 = -C2 · H 2 +} C6 · H 3. I
_{4 = H 4 + H 5,} I 5 = H 4 -H 5, I 6 = -H 6 + H
₇ , I ₇ = H ₆ + H ₇ . Finally, F ₁ = C7 · I
₄ + C1 · I ₇ , F ₅ = C3 · I ₅ + C5 · I ₆ , F _{3
= -C5 · I 5 + C3 ·} I 6, F 7 = -C1 · I 4 + C
7 · I ₇ .

As is apparent from FIG. 25, the pixel data f
₀ When ~f ₇ and inputs the same time, the data G ₀ ~G ₇ is obtained at the same time, then the data H ₀ to H ₇ are obtained simultaneously. Further, the DCT coefficients F ₀ , F ₄ , F ₂ , F ₆ and the data I _{4 to} I ₇ are obtained at the same time, and finally the DCT coefficients F ₁ , F
₅ , F ₃ and F ₇ are obtained at the same time. By thus inputting the pixel data f _{0 to} f ₇ at the same time, the DCT coefficients F _{0 to} F ₇ can be obtained almost at the same time.

[0028]

If the Chen algorithm is used as described above, the pixel data f _{0 to} f ₇ to D can be obtained.
The CT coefficients F _{0 to} F ₇ can be obtained at high speed. Therefore, 1
The dimensional DCT can be executed at high speed. However, as described above, 32 times of multiplication is required to calculate the DCT coefficients F _{0 to} F ₇ for one row, and the DCT coefficients for eight rows are required.
256 multiplications are required to calculate the coefficients. Since the circuit scale of the multiplier is large, even if the Chen algorithm is used, the circuit scale of the one-dimensional DCT circuit becomes very large.

An object of the present invention is to provide a method and a circuit capable of performing discrete cosine transform at high speed with a small circuit scale.

[0030]

[Means for Solving the Problems]

(1) First Invention A discrete cosine transform method according to the first invention is X and K.
A discrete cosine transform method for obtaining the DCT coefficient F _K from the input data f _X by the sum of products of the cosine function C (K, X) with respect to the input data f _X and including the following steps. Here, X represents an integer from 0 to N-1, and K represents an integer from 0 to N-1.

Replace the cosine function C (K, X) with the coefficient C _KX . The coefficient C _KX satisfies the relationship C (K, X) / C _KX = S _K for all K values for each K value and contains a power of two. Here, S _K represents a constant. The product sum of the coefficient C _KX and the input data f _X is obtained by shifting and adding the data to obtain F _K /
To calculate the value of S _K.

(2) Second Invention A discrete cosine transform circuit according to a second invention is X and K.
A discrete cosine transform circuit that obtains the DCT coefficient F _K from the input data f _X by the sum of products of the cosine function C (K, X) with respect to the input data f _X, and includes a plurality of adding means. Here, X represents an integer from 0 to N-1, and K
Represents an integer from 0 to N-1.

The plurality of adding means calculates the value of F _K / S _K for each value of K by obtaining the product sum of the coefficient C _KX and the input data f _X by using data shift and addition. The coefficient C _KX satisfies the relationship C (K, X) / C _KX = S _K for all X values for each K value and 2
Including exponentiation of. Here, S _K represents a constant.

(3) Third Invention The discrete cosine transform circuit according to the third invention is F _K / S _K.
It further comprises multiplication means for multiplying the value of S by S _K.

(4) Fourth Invention A discrete cosine transform circuit according to a fourth invention is X and K.
A discrete cosine transform circuit that obtains a DCT coefficient F _K from the input data f _X by the sum of products of the cosine function C (K, X) with respect to the input data f _X, and includes a plurality of processing blocks. Here, X represents an integer from 0 to N-1, and K represents an integer from 0 to N-1.

The input data f _X
Is obtained in time series, and the value of F _K / S _K is calculated by calculating the product sum of the coefficient C _KX and the input data f _X by pipeline processing. Here, S _K represents a constant. Coefficient C _KX
For all K values for each K value, C
The relationship (K, X) / C _KX = S _K is satisfied and the power of 2 is included.

(5) Fifth Invention In the discrete cosine transform circuit according to the fifth invention, each of the processing blocks of a plurality of stages outputs one or a plurality of adding means and a plurality of data given in time series from the preceding stage. It includes a holding unit that sequentially shifts and holds the data, and a selection unit that selectively applies the plurality of data held by the holding unit to one or a plurality of addition units.

[0038]

The discrete cosine transform method and the discrete cosine transform circuit according to the first to fifth aspects of the invention are made by paying attention to the following points. That is, multiplication of certain data by 2 ⁿ can be performed by shifting the data to the left by n bits, and multiplication of certain data by 1/2 ⁿ can shift the data by n bits to the right. It can be done by doing. Here, n represents a positive integer. Also, all integers can be represented by addition or subtraction of power-of-two terms.

Therefore, the cosine function C (K, X) is converted into the coefficient C.
By replacing with _KX , coefficient C _KX and input data f _X
The multiplication with and can be performed by shifting and adding data. Moreover, since each coefficient C _KX includes a power of 2 as much as possible, the number of additions may be small.

Therefore, in the discrete cosine transform method and the discrete cosine transform circuit according to the first to fifth inventions, the DCT coefficient can be obtained at high speed by using the minimum number of adders without using the multipliers. it can.

Particularly, in the discrete cosine transform circuit according to the second and third aspects, the DCT coefficient can be obtained at a higher speed. Further, in the discrete cosine transform circuit according to the fourth and fifth aspects of the invention, the number of adding means is reduced.

[0042]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a D according to an embodiment of the present invention.
It is a figure which shows the conversion formula used for a CT method.

In FIG. 1, conversion formulas (F1) to (F8)
To convert pixel data f _{0 to} f ₇ to converted data F ₀ ′ to F
₇ 'is obtained. The conversion formulas (F1) to (F shown in FIG.
8) is different from the conversion formulas (E1) to (E8) shown in FIG. 22 in that the coefficients of the respective terms are different. However, the ratio of the four coefficients in each conversion formula (F1) to (F8) is the same as the ratio of the four coefficients in each conversion formula (E1) to (E8). That is, the following relationship holds.

2: 2: 2: 2 = C4: C4: C4: C4 2: -2: -2: 2 = C4: -C4: -C4: C4 3: 159/2 ⁷ : -159/2 ⁷ : -3 = C2: C6: -C6:-
C2 159/2 ⁷ : -3: 3: -159/2 ⁷ = C6: -C2: C2:-
C6 (161/2 ⁵ ) ・ (181/2 ⁸ ): 193/2 ⁶ : 129/2 ⁶ : 181/2 ⁸ = C1:
^{C3: C5: C7 181/2 7:} -639/2 8: 127/2 8: (181/2 8) · (383/2 7) =
C5: -C1: C7: C3 ( 181/2 8) · (383/2 7): - 127/2 8: -639/2 8: -181/2 7 =
C3: -C7: -C1: -C5 181/2 8: -129/2 6: 193/2 6: (-181/2 8) · (161 /
²⁵ ) = C7: -C5: C3: -C1

Therefore, between the DCT coefficients F _{0 to} F ₇ and the converted data F ₀ ′ to F ₇ ′, equations (G1) to
There is a relationship represented by (G8). Here, S _{0 to} S ₇ represent constants. Therefore, the conversion formula (F1) of FIG.
The DCT coefficients F _{0 to} F ₇ are obtained by multiplying the converted data F ₀ ′ to F ₇ ′ calculated by (F8) by constants S _{0 to} S ₇ , respectively.

Each coefficient in the conversion formulas (F1) to (F8) contains a power of 2 as much as possible. The multiplication of a certain data by 2 ⁿ can be performed by shifting the data to the left by n bits. Further, multiplication of a certain data by 1/2 ⁿ can be performed by shifting the data to the right by n bits. Here, n represents a positive integer.

Further, all integers can be represented by addition or subtraction of power-of-two terms. For example, 3 = 2
¹ +2 ⁰ , 129 = 2 ⁷ +2 ⁰ , 159 = 2 ⁷ +2 ⁵ −
2 is ^0. Also, 161 = 5 · 2 ⁵ +2 ⁰ = (2 ² +
2 ⁰ ) · 2 ⁵ +2 ⁰ , 383 = 3 · 2 ⁷ −2 ⁰ = (2 ²
-2 ⁰⁾ 2 ⁷ -2 ^0.

Therefore, each conversion formula (F1)-
The multiplication of the coefficient and the data in (F8) can be performed by shifting and adding the data. In this embodiment, since each coefficient includes a power of 2 as much as possible, the number of additions may be small.

Conversion formulas (F1) to (F8) shown in FIG.
Is represented by the flow graph (butterfly chart) of FIG. Also in FIG. 3, as in FIG. 25, the circles represent addition, and the coefficient attached to each line represents multiplication of that coefficient. Also, α = 3, β = 159, γ = 181, δ = 38
3, ε = 161.

In FIG. 3, g ₀ = f ₀ + f ₇ , g ₁ =
f ₁ + f ₆ , g ₂ = f ₂ + f ₅ , g ₃ = f ₃ + f ₄ , g
_{4 = f 3 -f 4, g} 5 = f 2 -f 5, g 6 = f 1 -
f _6, is a g ₇ = f ₀ -f _7. Also, h ₀ = g ₀ + g
₃ , h ₁ = g ₁ + g ₂ , h ₂ = g ₁ −g ₂ , h ₃ = g ₀
-G _3. h ₄ = (γ / 2 ⁸ ) · g ₄ , h ₅ = (-
1/2) · g ₅ + (1/2) · g ₆ , h ₆ = (1/2)
・ G ₅ + (1/2) ・ g ₆ , h ₇ = (γ / 2 ⁸ ) ・ g ₇
Is.

Further, F ₀ ′ = 2 · h ₀ + 2 · h ₁ , F
₄ ′ = 2 · h ₀ −2 · h ₁ , F ₂ ′ = (β / 2 ⁷ ) · h
₂ + α · h ₃ , F ₆ ′ = −α · h ₂ + (β / 2 ⁷ ) · h
_{Is 3} . _{i 4 = h 4 + h 5} , i 5 = h 4 -h 5, i 6
_{= -H 6 + h 7, i} 7 = a h ₆ + h _7. Finally, F
₁ ′ = i ₄ + (ε / 2 ⁵ ) · i ₇ , F ₅ ′ = (δ /
2 ⁷ ) · i ₅ + 2 · i ₆ , F ₃ ′ = −2 · i ₅ + (δ /
2 ⁷ ) · i ₆ and F ₇ ′ = − (ε / 2 ⁵ ) · i ₄ + i ₇ .

As is clear from FIG. 3, the pixel data f ₀
When ~ f ₇ are input at the same time, data g _{0 to} g ₇ are obtained at the same time, and then data h _{0 to} h ₇ are obtained at the same time. Further, converted data F ₀ ′, F ₄ ′, F ₂ ′, F ₆ ′ and data i _{4 to} i ₇ are obtained at the same time, and finally converted data F
_{1 ', F 5', F} 3 ', F 7' is obtained at the same time. Thus, by inputting the pixel data f _{0 to} f ₇ at the same time, the conversion data F ₀ ′ to F ₇ ′ can be obtained almost at the same time.

FIG. 4 is a diagram showing the number of multiplications in the image data compression system using the DCT method and the DCT circuit according to this embodiment in comparison with the number of multiplications in the image data compression system using the conventional DCT method.

As shown in FIG. 4A, in the conventional system, 256 multiplications are required to perform the two-dimensional DCT, and 64 multiplications are required to perform the quantization. Become.

On the other hand, as shown in FIG. 4B, in the system according to this embodiment, no multiplication is required to perform the two-dimensional DCT, and 64 times are required to perform the quantization. Multiplication is required. Equations (G1) to (G
The multiplication in 8) does not need to be performed in the two-dimensional DCT, and can be included in the quantization process by considering the constants S _{0 to} S ₇ in the quantization table.

Next, a DCT circuit according to an embodiment of the present invention will be described. As shown in the flow graph of FIG. 3, six blocks BK1, BK2-1, BK are used to calculate the conversion data F ₀ ′ to F ₇ ′ from the pixel data f _{0 to} f _7.
2-2, BK3-1, BK3-2, BK4.

In the block BK1, pixel data f _{0 to} f
Data g ₀ to g ₃ are calculated from ₇ . Block BK2
In -1, data h ₀ to h ₃ are calculated from the data g _{0 to} g ₃ , and in block BK2-2, data h ₄ to h ₇ are calculated from the data g _{4 to} g ₇ . Block BK3-1
Then, from the data h _{0 to} h ₃ , the converted data F ₀ ′,
F ₄ ′, F ₂ ′ and F ₆ ′ are calculated. Block BK3
In -2, data i ₄ through i ₇ from the data h ₄ to h ₇ is calculated. In the block BK4, converted data F ₁ ′, F ₅ ′, F ₃ ′, F ₇ ′ are calculated from the data i _{4 to} i ₇ .

FIG. 5 is a diagram showing a circuit for executing the operation of the block BK1, and FIG. 6 is a timing chart for explaining the operation of the circuit of FIG.

The block BK1 includes registers Reg00 to Reg08 and buffers B00 to B0 connected in series.
4, including an inverter I04 and an adder ADD00.

Select signals SEL00 to SEL03 are applied to the output enable terminals of the buffers B00 to B03, respectively. The output enable terminal of the inverter I04 is provided with the selection signal SEL04, and the output enable terminal of the buffer B04 is provided with the selection signal / SEL04. The selection signal / SEL04 is an inverted signal of the selection signal SEL04. An adder / subtractor signal A / S00 having the same phase as the selection signal SEL04 is applied to the carry input terminal of the adder ADD00.

Each buffer and each inverter are activated when the selection signal applied to the output enable terminal is "H". Further, the carry input terminal of the adder is given a signal of "L" at the time of addition and a signal of "H" at the time of subtraction.

Pixel data f _{0 to} f ₇ are sequentially applied to the input terminal f _X and sequentially shifted to the registers Reg00 to Reg08.

As shown in FIG. 6, in the cycles t0 to t3, the selection signal SEL04 becomes "H". As a result, the data f ₄ sequentially given to the register Reg00
.About.f ₇ are sequentially applied to one input terminal of the adder ADD00 through the inverter I04. In addition, the selection signal SE
L00 to SEL03 sequentially rise to "H". Accordingly, the registers Reg01, Reg03, Reg05,
Data f ₃ of _{Reg07, f 2, f 1,} f 0 respectively buffers B00, B01, B02, it is sequentially applied to the other input terminal of the adder ADD00 through B03. As a result, the data g ₄ is output from the adder ADD00 to the output terminal g _X.
(= F ₃ −f ₄ ), g ₅ (= f ₂ −f ₅ ), g ₆ (= f
_{1 -f 6), g 7 (} = f 0 -f 7) are sequentially output.

In the cycles t4 to t7, the selection signal SEL04 becomes "L". As a result, the register Re
Data f _{0 to} f ₃ sequentially given to g08 are stored in the buffer B.
It is sequentially applied to one input terminal of the adder ADD00 via 04. Further, the selection signals SEL00 to SEL03 sequentially rise to "H". As a result, the register Reg
Data f of 01, Reg03, Reg05, Reg07
₇ , f ₆ , f ₅ , and f ₄ are buffers B00 and B0, respectively
1, B02, B03 are sequentially applied to the other input terminal of the adder ADD00. As a result, the adder ADD0
From 0 to the output terminal g _X , data g ₀ (= f ₀ + f ₇ ), g
₁ (= f ₁ + f ₆ ), g ₂ (= f ₂ + f ₅ ), g ₃ (=
f ₃ + f ₄ ) are sequentially output.

FIG. 7 is a diagram showing a circuit for executing the operation of the block BK2-1, and FIG. 8 is a timing chart for explaining the operation of the circuit of FIG.

The block BK2-1 includes registers Reg10 to Reg14 and buffers B10 to B connected in series.
12, an inverter I12 and an adder ADD10.

Select signals / SEL10 and SEL10 are applied to the output enable terminals of the buffers B10 and B11, respectively. Select signals SEL12 and / SEL are applied to the output enable terminals of the inverter I12 and the buffer B12, respectively.
SEL12 is provided. An adder / subtractor signal A / S10 having the same phase as the selection signal SEL12 is applied to the carry input terminal of the adder ADD10.

The register Reg10 is connected to the output terminal g _X of the block BK1. As a result, the register Reg
Data g supplied from the output terminal g _X in _{10~Reg14 4 ~g 7, g 0 ~g} 3 are sequentially shifted.

As shown in FIG. 8, in the cycle t10, the selection signal SEL10 becomes "L" and the selection signal S
EL12 becomes "H". As a result, the register Reg
The data g _{2 of} 10 is added to the adder A via the inverter I12.
It is applied to one input terminal of DD10. Further, the data g _{1 of the} register Reg11 is given to the other input terminal of the adder ADD10 via the buffer B10. As a result, the data h is output from the adder ADD10 to the output terminal h _X.
2 (= g ₁ −g ₂ ) is output.

In cycle t11, the selection signal SE
L10 becomes "H", and the selection signal SEL12 also becomes "H". Thereby, the data g ₃ of the register Reg10 is given to one input terminal of the adder ADD10 via the inverter I12. The data g _{0 of the} register Reg13 is given to the other input terminal of the adder ADD10 via the buffer B11. As a result, the adder ADD1
The data h ₃ (= g ₀ −g ₃ ) is output from 0 to the output terminal h _X.

In cycle t12, the selection signal SE
L10 becomes "L" and the selection signal SEL12 also becomes "L". As a result, the data g ₃ of the register Reg11 is given to one input terminal of the adder ADD10 via the buffer B10. The data g _{0 of the} register Reg14 is given to the other input terminal of the adder ADD10 via the buffer B12. As a result, the adder ADD10
The data h ₀ (= g ₀ + g ₃ ) is output from the output terminal h _X.

In cycle t13, the selection signal SE
L10 becomes "H" and the selection signal SEL12 becomes "L". As a result, the data g ₂ of the register Reg13 is given to one input terminal of the adder ADD10 via the buffer B11. Further, the data g _{1 of the} register Reg14 is given to the other input terminal of the adder ADD10 via the buffer B12. As a result, the adder ADD10
The data h ₁ (= g ₁ + g ₂ ) is output from the output terminal h _X.

FIG. 9 is a diagram showing a circuit for executing the operation of the block BK2-2, and FIG. 10 is a timing chart for explaining the operation of the circuit of FIG.

The block BK2-2 has registers Reg30 to Reg33 and a register Reg34 connected in series.
-Reg36, buffers B30-B34, inverter I
30 and adders ADD30 to ADD33. Adders ADD31 to ADD33 and register Reg34
-Reg36 comprises the arithmetic block BL30.

The select signal SEL30 is applied to the output enable terminals of the buffer B30 and the inverter I30, and the select signal / SEL30 is applied to the output enable terminals of the buffers B31 and B32. Buffer B33,
The selection enable signal SE is applied to the output enable terminals of B34.
L31 and / SEL31 are provided. Adder ADD30
An addition / subtraction signal A / S30 having the same phase as the selection signal SEL30 is applied to the carry input terminal of the. Adder ADD3
Signals of "L" are given to the carry input terminals of 1, ADD32, and ADD33.

In FIG. 9, 2LS, 4LS, and 5LS indicate that data is shifted to the left by 2 bits, 4 bits, and 5 bits, respectively. Also, 1RS,
8RS indicates that the data is given by shifting to the right by 1 bit and 8 bits, respectively. Adder ADD31
Performs multiplication of γ '(= 5), and adders ADD31, A
The DD 32 performs multiplication by γ ″ (= 21), and the operation block BL30 performs multiplication by γ (= 181).

The register Reg30 is connected to the output terminal g _X of the block BK1. As a result, the register Reg
Data g supplied from the output terminal g _X in _{30~Reg33 4 ~g 7, g 0 ~g} 3 are sequentially shifted.

As shown in FIG. 10, in cycle t30, the data γ'g ₄ × ²⁵ is supplied from the register Reg35 to one input terminal of the adder ADD33, and the other input terminal of the adder ADD33 is supplied from the register Reg36. Is supplied with the data γ ″ g _4. Therefore, the adder A
Data h ₄ (= γ / from DD33 to output terminal h2 _X
2 ⁸ ) is output. At this time, the selection signal SEL31 is "L". Therefore, the data h ₄ of the output terminal h2 _X is output to the output terminal h _X via the buffer B34.

In cycle t31, the selection signal SE
L30 becomes "H". Thereby, the register Reg3
The data g _{6 of} 1 is added to the adder ADD via the buffer B30.
30 is applied to one input terminal. Also, register R
The data g ₅ of the eg32 is supplied to the other input terminal of the adder ADD30 via the inverter I30. As a result, the data h ₅ is output from the adder ADD30 to the output terminal h1 _X.
(= (G ₆ −g ₅ ) / 2) is output. At this time, the selection signal SEL31 is "H". Therefore,
The data h ₅ of the output terminal h1 _X is output to the output terminal h _X via the buffer B33.

In cycle t32, the selection signal SE
L30 becomes "L". Thereby, the register Reg3
The data g _{6 of} 2 is added via the buffer B31 to the adder ADD
30 is applied to one input terminal. Also, register R
The data g ₅ of eg33 is supplied to the other input terminal of the adder ADD30 via the buffer B32. as a result,
Data h ₆ (= from the adder ADD30 to the output terminal h1 _X
(G ₅ + g ₆ ) / 2) is output. At this time, the selection signal SEL31 is "H". Therefore, the data h ₆ of the output terminal h1 _X is output to the output terminal h _X via the buffer B33.

In cycle t33, the register Re
The data γ′g ₇ × ²⁵ is supplied from g35 to one input terminal of the adder ADD33, and the data γ ″ g ₇ is supplied from the register Reg36 to the other input terminal of the adder ADD33. The data h ₇ (= γ / 2 ⁸ ) is output from the output terminal h2 _X. At this time, the selection signal SEL31 is “L.” Therefore, the data h _{7 at the} output terminal h2 _X is the buffer B34.
Is output to the output terminal h _X via.

FIG. 11 is a diagram showing a circuit for executing the operation of the block BK3-1, and FIG. 12 is a timing chart for explaining the operation of the circuit of FIG.

The block BK3-1 includes registers Reg20 to Reg22 connected in series, registers Reg23 to Reg25 connected in series, and register Reg26,
Reg27, buffers B20 and B21, inverter I2
0 to I22, and adders ADD20 to ADD24. The adder ADD21 constitutes the operation block BL20. In addition, the adders ADD22 and ADD23 and the register Reg26 form a calculation block BL21.

The output enable terminals of the inverter I20 and the buffer B20 have selection signals SEL20,
/ SEL20 is applied, and select signals SEL21 and / SEL21 are applied to the output enable terminals of the buffer B21 and the inverter I21, respectively. Adder ADD
An adder / subtractor signal A / S20 having the same phase as the selection signal SEL20 is applied to the carry input terminal of the adder 20 to adder ADD2.
The addition / subtraction signal A / S21 having the same phase as the selection signal SEL21 is applied to the carry input terminal of No. 4. Adder ADD2
1, a carry input terminal of the ADD 23 is supplied with an "L" signal. An "H" signal is applied to the carry input terminal of the adder ADD22.

In FIG. 11, 1LS, 5LS, 7LS
Indicates that the data is shifted to the left by 1 bit, 5 bits, and 7 bits, respectively. The operation block BL20 performs multiplication of α (= 3), and the adder ADD2
2 performs multiplication of β '(= 31), and the calculation block BL
21 performs multiplication of β (= 159).

The register Reg20 is a block BK2-1.
Is connected to the output terminal h _X of. As a result, the register R
The data h ₀ to h ₃ given from the output terminal h _X are sequentially shifted to eg20 to Reg22.

As shown in FIG. 12, in the cycle t20, the selection signal SEL21 becomes "H". As a result, the data αh ₃ of the register Reg23 is transferred to the buffer B2
1 to one input terminal of the adder ADD24. In addition, the register Reg27 to the adder ADD24
The other input data βh _2/2 ⁷ to the terminal of the given.
As a result, the conversion data F ₂ ′ (= β / 2 ⁷ · h ₂ + αh ₃ ) is output from the adder ADD24 to the output terminal F1 _X.

In cycle t21, the selection signal SE
L20 becomes "H". Thereby, the register Reg2
The data h _{1 of} 0 is added via the inverter I20 to the adder AD
It is applied to one input terminal of D20. Further, the data h _{0 of the} register Reg21 is given to the other input terminal of the adder ADD20. As a result, the converted data F ₄ ′ (= 2h ₀ −2) is output from the adder ADD20 to the output terminal F0 _X.
h ₁ ) is output.

At this time, the selection signal SEL21 is "L".
(Selection signal / SEL21 is "H"). As a result, the data αh ₂ of the register Reg25 is given to one input terminal of the adder ADD24 via the inverter I21. Also, from the register Reg27 to the adder AD
The other input terminal of the D24 data βh _3/2 ⁷ is applied to. As a result, the output terminal F1 _{X is} output from the adder ADD24.
The converted data F ₆ ′ (= −αh ₂ + β / 2 ⁷ · h ₃ ) is output to.

In cycle t22, the selection signal SE
L20 becomes "L". Thereby, the register Reg2
2 data h ₀ is added to the adder ADD via the buffer B20.
20 is applied to one of the input terminals. Also, register R
The data h ₁ of eg21 is given to the other input terminal of the adder ADD20. As a result, the conversion data F ₀ ′ (= 2h ₀ + 2h ₁ ) is output from the adder ADD20 to the output terminal F0 _X.
Is output.

FIG. 13 is a diagram showing a circuit for executing the operation of the block BK3-2, and FIG. 14 is a timing chart for explaining the operation of the circuit of FIG.

The block BK3-2 has registers Reg40 to Reg42 and buffers B40 to B connected in series.
42, an inverter I40 and an adder ADD40.

Select signals SEL40 and / SEL40 are applied to the output enable terminals of the buffers B40 and B42, respectively. The output enable terminals of the buffer B41 and the inverter I40 have selection signals SEL41,
/ SEL41 is provided. An adder / subtractor signal A / S40 having the same phase as the select signal / SEL41 is applied to the carry input terminal of the adder ADD40.

The register Reg40 is a block BK2-2.
Is connected to the output terminal h _X of. As a result, the register R
The data h ₄ to h ₇ given from the output terminal h _X are sequentially shifted to the eggs _{40 to} Reg 42.

As shown in FIG. 14, in cycle t40, select signal SEL40 and select signal SEL41.
Becomes "H". As a result, the data h ₅ of the register Reg40 is given to one input terminal of the adder ADD40 via the buffer B40. In addition, the register Reg4
The data h _{4 of} 1 is added to the adder ADD via the buffer B41.
40 to the other input terminal. As a result, the data i ₄ (= h ₄ + h) is output from the adder ADD40 to the output terminal i _X.
5 ) is output.

In cycle t41, the selection signal SE
L40 and the selection signal SEL41 become "L". As a result, the data h ₅ of the register Reg41 is given to one input terminal of the adder ADD40 via the inverter I40. Further, the data h _{4 of the} register Reg42 is given to the other input terminal of the adder ADD40 via the buffer B42. As a result, the data i ₅ (= h ₄ −h ₅ ) is output from the adder ADD40 to the output terminal i _X.

In cycle t42, the selection signal SE
L40 becomes "H" and the selection signal SEL41 becomes "L". As a result, the data h ₇ of the register Reg40 is given to one input terminal of the adder ADD40 via the buffer B40. Further, the data h _{6 of the} register Reg41 is given to the other input terminal of the adder ADD40 via the inverter I40. As a result, the adder ADD4
Data i ₆ (= h ₇ −h ₆ ) is output from 0 to the output terminal i _X.

In cycle t43, the selection signal SE
L40 becomes "L" and the selection signal SEL41 becomes "H". As a result, the data h ₇ of the register Reg41 is given to one input terminal of the adder ADD40 via the buffer B41. Further, the data h _{6 of the} register Reg42 is given to the other input terminal of the adder ADD40 via the buffer B42. As a result, the adder ADD40
The data i ₇ (= h ₆ + h ₇ ) is output from the output terminal i _X.

FIG. 15 is a diagram showing a circuit for executing the operation of the block BK4, and FIG. 16 is a timing chart for explaining the operation of the circuit of FIG.

The block BK4 has registers Reg50 to Reg56 and registers Reg57 to R connected in series.
eg60, buffers B50 to B53, inverter I50
-I53 and adders ADD50-ADD55. Adders ADD50, ADD51 and register Re
g57 constitutes the operation block BL50, and the adder ADD
53, the ADD 54, and the register Reg 59 form a calculation block BL51.

The select signal SEL50 is applied to the output enable terminals of the buffers B50 and B51, and the inverter I
A selection signal / SEL50 is applied to the output enable terminals of 50 and the buffer B52. Selection signals SEL50 and / SEL50 are applied to the output enable terminals of the inverter I53 and the buffer B53, respectively.

The carry input terminal of the adder ADD52 has an addition / subtraction signal A / S50 in phase with the selection signal / SEL50.
And a carry input terminal of the adder ADD55 is provided with the addition / subtraction signal A / S51 having the same phase as the selection signal SEL50. Adders ADD50, ADD53, ADD5
The carry input terminal of No. 4 is given a signal of "L", and the carry input terminal of the adder ADD51 is given a signal of "H".

The adder ADD50 multiplies δ '(= 3), and the operation block BL50 multiplies δ (= 383). The adder ADD53 performs multiplication by ε '(= 5), and the operation block BL51 performs multiplication by ε (= 161).

The register Reg50 is a block BK3-2.
Connected to the output terminal i _X of. As a result, the register R
The data i _{4 to} i ₇ given from the output terminal i _X are sequentially shifted to eg 50 to Reg 56.

As shown in FIG. 16, in cycle t50, the selection signal SEL50 becomes "H". As a result, the data i ₇ of the register Reg50 is transferred to the buffer B50.
To the one input terminal of the adder ADD55. Further, the data εi is input from the register Reg60 to the other input terminal of the adder ADD55 via the inverter I53.
_4/2 ⁵ is given. As a result, the adder into an output terminal F3 _X from ADD55 data _{F 7 '(= -ε / 2} 5 ·
i ₄ + i ₇ ) is output.

Also in the cycle t51, the selection signal SE
L50 is "H". As a result, the register R
adder ADD52 from eg52 via buffer B51
Data 2i ₆ is applied to one of the input terminals. Also,
Data .delta.i _5/2 ⁷ is provided to the other input terminal of the adder ADD52 from the register Reg58. As a result, the converted data F ₅ ′ is output from the adder ADD52 to the output terminal F2 _X.
(= Δ / 2 ⁷ · i ₅ + 2i ₆ ) is output.

In cycle t52, the selection signal SE
L50 becomes "L". Thereby, the register Reg5
The data 2i ₅ is supplied from 4 to the one input terminal of the adder ADD52 via the inverter I50. The data .delta.i _6/2 ⁷ is supplied from the register Reg58 the other input terminal of the adder ADD 52. As a result, the conversion data F ₃ '(= from the adder ADD52 to the output terminal F2 _X
-2i ₅ + δ / 2 ⁷ · i ₆ ) is output.

Also in the cycle t53, the selection signal SE
L50 is "L". As a result, the register R
The data i ₄ of eg56 is applied to one input terminal of the adder ADD55 via the buffer B52. Further, the adder AD is added from the register Reg60 via the buffer B53.
The other input terminal of the D55 data .epsilon.i _7/2 ⁵ is applied to. As a result, the output terminal F3 _{X is} output from the adder ADD55.
The converted data F ₁ ′ (= i ₄ + ε / 2 ⁵ · i ₇ ) is output to.

As described above, in the DCT circuit according to this embodiment, the one-dimensional DCT is performed using 18 adders.

Blocks BK1 and BK in this embodiment
2-1, BK2-2, BK3-1, BK3-2, BK4
Can also be used in the inverse DCT circuit shown in FIG. In the inverse DCT circuit, the pixel data f ₀ ~f ₇ is determined from the transformed data F ₀ '~F _7'.

The converted data F ₁ ′,
If F ₅ ′, F ₃ ′ and F ₇ ′ are given, the data i _{4 to} i ₇
Is obtained. Converted data F ₀ ′ to block BK3-1,
Given F ₄ ′, F ₂ ′ and F ₆ ′, the data h _{0 to} h ₃
Is obtained. Given a data i ₄ through i ₇ in block BK3-2, data h ₄ to h ₇ is obtained. Block BK
When data h ₀ to h ₃ are given to 2-1 data g _{0 to} g
You get ₃ . Data to block BK2-2 h ₄ ~h ₇
Is given, data g _{4 to} g ₇ are obtained. Block B
When data g ₀ to g ₇ are given to K1, pixel data f ₀ to
f ₇ is obtained.

Therefore, FIG. 5, FIG. 7, FIG. 9, FIG.
An inverse DCT circuit can be constructed using the circuits shown in FIGS. 13 and 15.

[0113]

According to the first aspect of the present invention, it is possible to obtain the discrete cosine transform method capable of performing the discrete cosine transform at high speed with a small circuit scale. According to the second to fifth inventions, it is possible to obtain the discrete cosine transform circuit capable of performing the discrete cosine transform at high speed with a small circuit scale.

In particular, the discrete cosine transform circuits according to the second and third inventions can execute the discrete cosine transform at a higher speed. The discrete cosine transform circuit according to the fourth and fifth aspects of the invention is configured with a smaller circuit scale.

[Brief description of drawings]

FIG. 1 is a diagram showing a conversion formula used in a DCT method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between converted data and DCT coefficients.

FIG. 3 is a diagram showing a flow graph for executing the conversion formula of FIG.

FIG. 4 is a diagram showing the number of multiplications in the DCT method according to an embodiment of the present invention in comparison with the number of multiplications in the conventional DCT method.

FIG. 5 is a diagram showing a circuit for realizing one block in the DCT circuit according to the embodiment of the present invention.

6 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 7 is a diagram showing a circuit for realizing one block in a DCT circuit according to an embodiment of the present invention.

8 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 9 is a diagram showing a circuit for realizing one block in the DCT circuit according to the embodiment of the present invention.

FIG. 10 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 11 is a diagram showing a circuit for realizing one block in the DCT circuit according to the embodiment of the present invention.

12 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 13 is a diagram showing a circuit for realizing one block in the DCT circuit according to the embodiment of the present invention.

FIG. 14 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 15 is a diagram showing a circuit for realizing one block in a DCT circuit according to an embodiment of the present invention.

16 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 17 is a diagram showing a flow graph for realizing an inverse DCT circuit.

FIG. 18 is a block diagram showing a basic configuration of a DCT image data compression system.

FIG. 19 is a diagram showing how image data is divided into blocks.

FIG. 20 is a diagram showing an 8 × 8 pixel block and a DCT-transformed block.

FIG. 21 is a block diagram showing a configuration for performing two-dimensional DCT.

FIG. 22 is a diagram showing a conversion formula used in the Chen algorithm.

23 is a diagram in which the conversion formula of FIG. 22 is represented by a determinant.

FIG. 24 is a diagram showing a modified expression of the conversion expression of FIG. 22.

FIG. 25 is a diagram showing a flow graph for executing the conversion expressions of FIGS. 22 and 24.

[Explanation of symbols]

f _{0 to} f ₇ pixel data F ₀ ′ to F ₇ ′ conversion data F _{0 to} F ₇ DCT coefficient S _{0 to} S ₇ constants ADD00, ADD10, ADD20 to ADD24, A
DD30 to ADD33, ADD40, ADD50 to AD
D55 adder Reg00 to Reg08, Reg10 to Reg14, R
eg20 to Reg27, Reg30 to Reg35, Re
g40 to Reg42, Reg50 to Reg60 registers B00 to B04, B10 to B12, B20 to B21, B
30-B31, B40-B42, B50-B53 Buffers I04, I12, I20-I22, I30, I31, I
40, I50 to I53 inverters BK1, BK2-1, BK2-2, BK3-1, BK3
-2, BK4 block In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/133 Z

Claims (5)

[Claims] 1. A cosine function C (K, K with respect to X and K
X) and the input data f _X , the input data f
A discrete cosine transform method for obtaining the DCT coefficients F _K from _X, the X represents an integer from 0 to N-1, wherein K is an integer from 0 to N-1, the cosine function C (K , replace X) with coefficients C _KX, the coefficient C _KX, to the values of all of X for each value of K, C (K, X) / C KX = relationship satisfaction vital 2 S _K Including exponentiation, S _K represents a constant, and the value of F _K / S _K for each value of K is obtained by finding the sum of products of the coefficient C _KX and the input data f _X using data shift and addition. A discrete cosine transform method for calculating. 2. A cosine function C (K, K with respect to X and K
X) and the input data f _X , the input data f
A discrete cosine transformation circuit for obtaining a DCT coefficient F _K from _X, the X represents an integer from 0 to N-1, wherein K is an integer from 0 to N-1, the input and coefficient C _KX A plurality of adding means for calculating the value of F _K / S _K for each value of K by obtaining the sum of products with the data f _X using shift and addition of the data, and the coefficient C _KX is Discrete cosine transform circuit, which satisfies the relation of C (K, X) / C _KX = S _K and includes a power of 2, where S _K represents a constant for all X values in terms of values. Wherein further comprising a multiplying means for multiplying the S _K to the value of the F _K / S _K, discrete cosine transformation circuit as claimed in claim 2. 4. A cosine function C (K, K, for X and K
X) and the input data f _X , the input data f
A discrete cosine transform circuit from _X determine the DCT coefficients F _K, wherein X represents an integer from 0 to N-1, wherein K is an integer from 0 to N-1, the input data f _X when receiving the sequence, includes a processing block in a plurality of stages of calculating the value of F _K / S _K by the product-sum with the coefficient C _KX and the input data f _X obtained by pipeline processing, the S _K is a constant The coefficient C _KX is a discrete cosine transform circuit that satisfies the relationship of C (K, X) / C _KX = S _K for all K values for each K value and includes a power of 2. . 5. Each of the plurality of processing blocks has one or a plurality of adding means, a holding means for sequentially shifting and holding a plurality of data given in time series from the previous stage, and a holding means. 5. The discrete cosine transform circuit according to claim 4, further comprising: selecting means for selectively applying the plurality of data to the one or more adding means.