JPH06327831A - Microprocessor for game machine - Google Patents

Abstract

PURPOSE:To prevent the unjust action by giving a recognition code to a program given a type qualification, giving a recognition code to a microprocessor for controlling the machine after reading the above-described recognition code, and starting operation after the accordance of the recognition code is confirmed. CONSTITUTION:A work RAM 4 for control is put into a usable state by a mode controller 9 according to the instruction supplied from a CPU 1, and a program for stopping the device according to the algorithm for calculating the type recognition code, key code, existence of the recognition code, or the fact that an application program(AP) address region is within a range or not is read into the CPU 1 from a built-in ROM 10. As for this CPU 1, the recognition code is calculated on the basis of the key code, and compared with the recognition code read-in from a user memory means (outside ROM) 14. If each result of the comparison does not accord with each other, the device is made to stop after the execution time of AP lapses over a prescribed time, and when the result of the comparison accords with each other, AP is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an application program (equipment control program or equipment control program which is mounted on a pachinko gaming machine, a spinning-type gaming machine, an arrange ball, a jean ball gaming machine, etc. (Data) related to a semiconductor chip for activating, which is configured to prevent the program from being modified so that the semiconductor chip will operate outside the legal standards after being certified.

A gaming machine such as a pachinko machine is a product that cannot be sold unless the gaming machine is certified and the model is certified in accordance with the rules of the National Public Safety Commission based on the rules of the Business Act of Customs, and uses a microprocessor. Things must pass the type test of the Security Electronics and Communication Technology Association,
Those that have obtained this type approval can be used for sales at pachinko halls.

However, it is conceivable that after the model is approved, the manufacturer or the hall side may take various measures to modify the microprocessor or modify the program to use it as an illegal game machine. Preventing post-approval modification is a challenge today.

[0004]

2. Description of the Related Art A conventional game machine of this type includes a device that continuously operates an electric accessory, a device that electrically controls the electric accessory, and a circuit that is integrated with a microprocessor. It is known to control the rotation of a rotating drum in a torso-type game machine.In these circuits, those that pass the type test of the Security Electronics and Communication Technology Association emit a winning ball to the user with a certain probability. Is configured to. In the case of gaming machines, it is obligatory to store programs and data in a predetermined address area.

[0005]

However, in the case of such a conventional circuit, if the control program and data in the circuit are modified after the type approval is obtained, it is difficult to distinguish it from the approved product, and the product is approved only by appearance. It is likely to be handled as a product. Therefore, there is an inconvenience that such fraud cannot be sufficiently prevented. If such fraud is left unchecked, the player will be at a disadvantage, and the credibility of the person handling the type-approved product will be impaired, and the significance of performing the type test may be diminished. Therefore, the present invention has been made in view of the above-mentioned drawbacks of the prior art. In order to prevent tampering with programs and data in the microprocessor in the gaming machine, a mechanism for making illegal modification in the gaming machine difficult is provided. The purpose is to have a function.

[0006]

That is, the present invention provides an application program stored in a predetermined area and a user storage means in which an authentication code or the like encrypted from the application program based on a predetermined algorithm is stored. An algorithm for calculating an authentication code from the application program and a chip built-in storage means storing one or more key codes for calculating the authentication code, and an application program work for reading and storing user data etc. from the user storage means An authentication code is calculated from the storage means, the application program input from the user storage means, the authentication code calculation program and the key code stored in the chip built-in storage means, and the authentication code is read from the user storage means in advance. A central processing unit (CPU) for comparing the authentication code with the authentication code, and a means for monitoring the execution address of the application program or the execution time of the application program when the authentication code does not match as a result of the comparison by the central processing unit. This object is achieved by a microprocessor for gaming machines configured to activate the means and to execute the application program and to execute the application program when the authentication codes match by comparison. According to a second aspect of the present invention, the central processing unit activates the means for monitoring the execution address of the application program when the authentication codes match with each other, and stops the operation of the device when the program exceeds a predetermined area. It is configured to execute a program so as to reset the CPU.

In the device according to the present invention, Nippon Telegraph and Telephone is used as a means for encrypting the authentication code C calculated from the application program stored in the user storage means in the state where the predetermined encryption key code K is given. An encryption device and an encryption method developed by a corporation (commonly known as a field patent (JP-A-62-109083, JP-A-63-204289, JP-A-0-29289).
1-147585))), and the encryption method may be stored in the chip built-in storage means. The encryption method is not limited to these methods.

In order to prevent the modification of the application program in the user storage means after the authentication code is decrypted and the key code is decrypted, the key code and the authentication are stored in the user storage means and the chip built-in storage means as shown below. If the codes are stored as follows, and the authentication code is calculated from these and compared, the cipher becomes more complicated and cannot be easily deciphered. A plurality of authentication codes stored in the user storage means are calculated based on a plurality of key codes K ₁ , K ₂ , K ₃ , ... K _i , ... K _n C ₁ , C ₂ , C ₃ ,. It consists of C _i , ... C _n ,
The key code stored in the chip built-in storage means is any one of the plurality of key codes K ₁ , K ₂ , K ₃ , ... K _i , ... K _n.
It is K _i , and the authentication code of the user storage means that the central processing unit compares is the authentication code C _i calculated based on the key code K _i . Authentication code stored in the user storage means, a plurality of first primary key code _{K 1, K 2, K 3} , ... K i, ..., primary authorization code of the plurality which are respectively calculated based on K _n C ₁ , C ₂ , C ₃ ,
... C _i , ..., C _n and the primary authentication codes C ₁ , C ₂ , C ₃ , ...
C _i, ..., C _n and second consists primary authentication code C _20, primary key code keycode of the plurality stored in the chip built-in storage unit which is calculated on the basis of the secondary key code K _{b
K 1, K 2, K 3} , ... K i, ..., is any one K _i and the secondary key code K _b of the K _n, the authentication code of the user storage means by the central processing unit compares An arbitrary primary authentication code C _i calculated based on the primary key code K _i and a secondary authentication code C ₂₀ . Authentication code stored in the user storage unit, an intermediate authentication code C ₀ calculated based on one of the intermediate key codes K ₀
And a plurality of primary key codes K ₁ , K ₂ , K ₃ , ... K _i , ..., K _n
Primary authentication code C ₁ , C ₂ , C ₃ , ... Encrypted based on
C _i, ..., C _n and, said primary authentication code _{C 1, C 2, C 3} , ... C i,
..., C _n and the second calculated based on the secondary key code K _b
The next authentication code C ₂₀ is stored, and the key code stored in the chip built-in storage means is the intermediate key code K ₀ and the plurality of primary key codes K ₁ , K ₂ , K ₃ , ... K _i , ..., K. An arbitrary one of _n K _i and a secondary key code K _b , and the authentication code of the user storage means to be compared by the central processing unit is an arbitrary first key code K _i calculated based on the primary key code K _i . Primary authentication code C
_i and the secondary authentication code C ₂₀ .

[0009]

With the above-described structure, the microprocessor according to the present invention controls the apparatus as follows by reading the application program (referred to as AP) and the authentication code stored in the user storage means.
The following are patterns of data stored in the user storage means. There is a regular and regular authentication code in the program address area. There is a format error in the data area of the user storage. Program address area is regular and there is no authentication code. The program address area is not legitimate and there is a legitimate authentication code. The program address area is not legitimate and there is no legitimate authentication code.

Part or all of the program management data and the authentication code in these user storage means are stored in the work storage means. If there is no error in the address area of the stored application program, check whether the authentication code is stored in the user storage means.If the authentication code is not recorded or there is a format error in the address, Is stopped because it is not a legitimate device.

Next, in the case of having the authentication code C, the same method as the regular type inspection from the read application program (the authentication code calculation algorithm and the calculation key code K stored in the chip built-in storage means) is used.
Then, the authentication code c is calculated. The authentication code c calculated thereafter and the authentication code C read from the user storage means
Compare with and check whether the read authentication code is legitimate (match). As a result of the confirmation, if the authentication code is confirmed to be authentic, the application program is executed with or without the execution address monitoring means activated. When the authentication codes do not match, the application program is executed while the execution time monitoring means or the execution address monitoring means are activated.

Even when the application program is executed in a state where the authentication codes match, when the program tries to execute over a predetermined address area while the execution address monitoring means is operating, the device should be stopped. Trap or reset CPU,
Reboot the device. Further, when the application program is executed in a state where the authentication codes do not match, the operation of the device is stopped when the application program tries to control over the address area or after a lapse of a predetermined time from the start of execution of the application program. To trap. As described above, the contents of the program are checked for the cases such as ~ stored in the user storage means, and the device is operated. Hereinafter, the present invention will be described in detail according to the illustrated embodiments.

[0013]

1 is a block diagram showing an outline of an embodiment of a microprocessor according to the present invention. In the microprocessor according to the present invention, an application connected to a central processing unit 1 (CPU) via a system bus. Illegal address trap generator 2 (hereinafter referred to as IAT) as a means for monitoring the execution address of the program.
G), a boot watchdog timer 3 (hereinafter referred to as BWDT) as a means for monitoring the execution time of the application program, a control work RAM 4 as a system control work storage means, and an application program work storage means. Application program work RAM 5, RAM size limiter 6 for limiting the application program work RAM 5 in correspondence with the application program, CPU 1
Program memory bank switching device 7 for switching the input to IATG2, BWDT3, and control work RA
M4, the program memory bank selector 7, and a mode controller 9 for issuing an execution mode (Md) to the external bus gate 8, and the program memory bank selector 7
Built-in ROM 10 and external bus gate 8 as chip built-in storage means storing a control program connected to
And a program memory input / output device 12 connected to the external bus gate 8 and the CPU 1, and the processor (chip) A in which the work RAM 5 for application program is connected to the RAM size limiter 6 and the external bus of the chip A. It is composed of an application program connected to the gate 8, an authentication code of the application program, and an external ROM 14 as user storage means for storing data for the application program.

The relationship between the concrete connection of each means with the CPU 1 and the mode issued from the mode controller is as shown in FIG. 2, and the boot watchdog timer 3 for monitoring the execution time of the application program.
4 is activated when a mode signal is transmitted from the mode controller 9 as shown in FIG. 4, the operating time of the application program is started to be counted by the counter 16, and the time given by the CPU 1 (predetermined time: 1-2
Minute) and the time of the counter 16 are compared by the comparator 18, and when a predetermined time has elapsed, a stop signal is transmitted to the CPU 1.

Illegal address trap generator 2 for monitoring execution addresses of application programs
As shown in FIG. 5, the upper limit address and the lower limit address of the address area given from the CPU 1 are stored in the address registers 20 and 21, respectively, and are activated when a mode signal is transmitted from the mode controller 9. , CPU
The running address of the program of 1 is constantly monitored by the comparators 23 and 24, and when the address is exceeded in either one, the CP
Send a stop command to U1.

The built-in ROM 10 stores an algorithm for calculating the authentication code (expected value) of the application program in the type authentication and a key code for the calculation. The key code and the algorithm are actually used by the certification body. Use the same one used for. In addition, in order to stop the operation depending on the presence or absence of the data and the authentication code regarding the address area of the application program read from the external ROM 14, the ROM 1
A control program is stored in 0.

The program memory input / output device 12 mainly reads an application program memory stored in the external ROM 14 as an external I / O. In this embodiment, other stored data is an authentication code,
RAM size data and resource management data are included. still,
When the ROM 14 as the user storage means is mounted on the chip A, these program memory input / output devices 12
It goes without saying that the program memory bank switching device 7 can be used for switching without the need for the external bus gate 8.

In the above-described configuration, in the microprocessor according to the present invention, the mode controller 9 outputs a mode in response to an instruction from the CPU 1 and a control work RAM.
No. 4 is in the usable state, and an apparatus for calculating the type authentication code (expected value) and the key code (single or plural) from the built-in ROM 10 and the presence or absence of the authentication code or whether the application program address area is within the range A program for stopping the is read into the CPU 1.

After that, the mode controller 9 switches the mode for the program memory bank switching unit 7 according to an instruction from the CPU 1, and the resource management data such as the RAM size and the like from the external ROM 14 via the external bus gate 8 and the input / output device 12. Read the authentication code, CPU1
, The mode controller 9 switches the RAM size limiter 6 to a predetermined size. The user work data of the application program is the RAM 5 for application program work, and the authentication code is C
It is stored in the memory of PU1. By the way, for pachinko machines, it is defined as 256 bytes, and for pachislot machines as 512 bytes.

On the other hand, the CPU 1 reads all the data in the ROM 14 and performs an address scan to check whether the address area of the program is larger than a predetermined area and whether or not there is any authentication code data other than the resource management data. Therefore, when the program address area is out of regulation or when the authentication code is not stored, a device stop command is automatically issued. Further, the CPU 1 confirms the data address area from the scanning result and stores the selected data in the memory.

When the presence / absence of the resource management data and the authentication code data is cleared, the mode is switched and all the data including the application program stored in the external ROM 14 and the authentication code calculation stored in the internal ROM 10 are stored. The algorithm and the key code stored in the built-in ROM 10 are read, and the authentication code of the application program is calculated.

The calculated authentication code and the external ROM 14
The CPU 1 collates with the authentication code read from the device, and if they match as a result of the collation, the mode of the device is switched to the external bus 8, the switch 7, and the external ROM to shift to the application program execution mode. If the results of the comparison do not match, the registers 20 and 21 of the address of the execution address IATG2 are provided with data regarding the upper limit and the lower limit, and this is activated, and the data regarding the execution time of the program is provided to the counter 16 to the BWDT3. To activate it and to execute the application program.

Since this application program does not conform to the authentication code, IATG2 and BW
The DT3 constantly monitors the execution state of the program, and when the application program tries to execute the program over the work area and when it tries to execute the program over the set time, the device stop command sends CP.
It is issued to U1 and the device is stopped. In the present embodiment, there is an illegal program that occasionally operates beyond the address area even if it is a properly authenticated application program. Although such a program is a legitimate program even if it is a legitimate program, the IATG is stored in the address registers 20 and 21 with the address area scanned in advance when the application program is transferred.
2 is operating.

The input of the authentication code to the external ROM and the determination of the consistency of the authentication code by the microprocessor according to the present embodiment based on the application program and the authentication code input to the external ROM are as shown in FIG. This is done as in the block diagram. That is, the authentication code (security code) issuing machine B, the external ROM 1
4 and the issuer B, the encryption program of the field 8 and the key code K for encryption that have been input in advance are input, and the application program is scanned when the external ROM 14 is connected. However, the authentication code C is calculated on the basis of the key code K, and the calculated authentication code C is written in the external ROM 14 to complete the inspected external ROM 14.

The completed external ROM 14 is a processor (element) A when actually mounted on a game machine and operated.
Connected to. When the external ROM 14 is connected, the processor A, based on the same key code K and the encryption program as the issuer B stored in the internal ROM 10,
The application program is scanned to calculate the authentication code c. Then, the authentication code C stored in the external ROM 14 is compared with the authentication code c calculated by the processor A, and when they match, the application program program is executed, and when they do not match, the application program program is stopped without being executed. . Note that the authentication code issuing system and the authentication code calculation / comparison system are not limited to those shown in FIG. 8, and it is more difficult to decipher if the system shown in FIGS. 9, 10, and 11 is used. Become. Each issuing system and comparison system will be described below.

FIG. 7 shows a second embodiment, in which the issuing machine B has a plurality of primary authentication key codes K ₁ , K ₂ ,
K ₃ , ... K _i , K _n and the encryption program are entered,
When the external ROM 14 is connected, the application programs are scanned based on the respective key codes to calculate the authentication codes C ₁ , C ₂ , C ₃ , ... C _i , C _n , and these are external RO
Tested external ROM14 by writing to M14
Is completed. When the external ROM 14 is connected to the processor A, a predetermined key code is previously stored in the processor.
K _i and the encrypted program is input, whether the key scans the application program based on the code K _i is calculated authentication code c _i, which is consistent with the stored authentication code C _i to i-th If they do not match, the application program is executed, and if they do not match, the application program is stopped without being executed.

FIG. 9 shows a third embodiment, in which the issuing machine B has a plurality of primary authentication key codes K ₁ , K ₂ ,
K ₃ , ... K _i , K _n , the secondary authentication key code K _b and the encryption program are input, and when the external ROM 14 is connected, the application program is scanned based on each key code and the authentication code C ₁ , C ₂ , C ₃ , ... C _i , C _n are calculated, these are written in the external ROM ₁₄ , and the written authentication codes C ₁ , C ₂ , C ₃ , ... C _i , C _n are scanned, An inspected external ROM is completed by calculating the secondary authentication code C ₂₀ based on the key code K _b and writing the secondary authentication code C ₂₀ in the external ROM 14. When this external ROM 14 is connected to the processor A, one of the primary authentication key codes K _i , the second
Next authentication key code K _b and are encrypted program is input, the secondary authentication key code K calculates a first-order authentication code c _i scans the application program on the basis of the primary authorization key code K _i External ROM 14 based on _b
Primary authentication code C ₁ , C ₂ , C ₃ , ... C _i , C _{n written in}
To calculate the secondary authentication key code c ₂₀ . Then, the written i-th primary authentication code C _i is compared with the calculated primary authentication code c _i and the written secondary authentication code C ₂₀ is compared with the calculated secondary authentication code c _20. If both match, the application program is executed, otherwise it is stopped and not executed.

FIG. 9 shows a fourth embodiment in which the issuing machine B calculates a plurality of primary intermediate key codes K ₀ and an intermediate authentication code C ₀ based on the intermediate key codes K _0. And a primary key code K ₁ , K ₂ , K ₃ , ... K _i , K _n for encrypting the calculated intermediate authentication code C ₀ ,
The primary authentication calculated code _{C 1, C 2, C 3} , ... C i, is input and a secondary authentication key code K _b for encrypting by scanning the C _n, the external ROM14 When connecting, first the intermediate authentication code C ₀ is calculated while scanning the application program, and the calculated intermediate authentication code C ₀ and the primary authentication key codes K ₁ , K ₂ , K ₃ , ... K _i , K _n The primary authentication codes C ₁ , C ₂ , C ₃ , ... C _i , C _n are calculated by encryption based on the above, and these are written in the external ROM 14 and the primary authentication code C ₁ , written in the external ROM ₁₄ , An inspected external ROM is completed by calculating an authentication code C ₂₀ based on the secondary authentication key code K _b and writing it in the external ROM 14 while scanning C ₂ , C ₃ , ... C _i , C _n . This external ROM 14
When is connected to the processor A, the primary authentication intermediate key code K ₀ , the primary authentication key code K _i, the secondary authentication key code K _b , and the encryption program are input to the processor A in advance. scans the application program on the basis of the primary intermediate keycode K ₀ calculates a first-order authentication code c _0, the primary authentication code c _i is further encrypted based on a first order keycode K _i calculate. Next, the secondary authentication code c ₂₀ is scanned by scanning the primary authentication codes C ₁ , C ₂ , C ₃ , ... C _i , C _n written in the external ROM 14 based on the secondary authentication key code K _b. To calculate. Then, only when the primary authentication code and the secondary authentication code match, execute the application program,
At other times, stop the program without executing it.

The significance of encryption of those shown in FIGS. 6 to 9 will be described. In FIG. 6 (first embodiment), there is one encryption key code, and the authentication code is encrypted by a predetermined algorithm based on this, but when the processor key code is decrypted Requires changing the key code, in which case all ROMs of the user need to be changed. In FIG. 7 (second embodiment), there are a plurality of (n) encryption key codes, and any one key code is used for the processor. For this reason, even if one key code is decrypted, it does not mean that all the key codes are decrypted, and it is difficult to modify the program to match this. In FIG. 8 (third embodiment), the key code is encrypted using a plurality of keys, and the secondary authentication code is calculated based on the primary authentication code. Therefore, all the key codes are decrypted. It is very difficult to modify the program so that the authentication number matches from the decrypted key code. However, encryption is performed n times in order to create the authentication code in the issuing machine, and the encryption takes too long. The one shown in FIG. 9 (fourth embodiment) is designed so that the encryption does not take too long, and the authentication code can be calculated in almost the same time as in the case of the first embodiment.
Moreover, it becomes difficult to decipher the key code and modify the program as in the second and third embodiments. Next, an algorithm (16 bits) for creating an authentication code will be briefly described.

(Authentication code creating algorithm 1) As shown in FIG. 10, 16-bit data of each address of the user area and control area stored in the external ROM 14 is spread to 8-bit data 8A _i and 8B _i on the left and right. Then, as shown in FIG. 6, scanning is performed in order from the youngest address, and the authentication codes 8A " _i-1 and 8B" _i-1 (initial value: stored key code) immediately before are given respectively in the state of 8 bits. Authentication code 8
A _'i, 8B' calculates the _i. Further, the calculated one 8-bit data (example 8A ' _i ) is given to the calculated 8-bit data (example 8B' _i ) as the key code, and the authentication code 8A " _i ,
Calculate 8B " _i . Authentication code 8A" _i , 8B " _i obtained here
8 bit data 8A _{i + 1} , 8B _{i + 1} scanned next is sequentially spread using the key code for data spreading as described above, and finally the left and right 8-bit data 8A " _n ，
8B " _n is fused to form a final authentication code as 16-bit data.

(Authentication Code Algorithm 2) As shown in FIG. 12, 16-bit data of each address of the user area and control area stored in the external ROM 14 is spread to 8-bit data 8A _i , 8B _i on the left and right sides. , The address is scanned in order from the youngest one, and the key 8 is given the key code K, and the authentication code 8'A _i , 8'B _i is calculated, and the next address 8A _{i + 1} , 8B _{i + 1} is calculated. Exclusive OR (E
Called as X-OR), the key code K is given again to the field 8, and the authentication code 8'A _{i + 1} ,
By repeating the operation of calculating 8'B _{i + 1} , the authentication code
Calculate 8'A _n and 8'B _n . Finally, the values obtained with 8'A _n and 8'B _n are applied to the field 8 with 8'A _n or 8'B _n as a key code, and authentication codes 8 "A _n and 8" B _n are obtained.

(Authentication code algorithm 3 (8 bits)) As shown in FIG. 11, the 8-bit authentication code algorithm inputs 8-bit data 8 ₁ with an initial value of 0 and passes through the EX-OR circuit. while it is given a predetermined key code after diffusing 8 _'1 and calculates the authentication code 8 _"1. the resulting input to EX-OR circuit for successive data spreading the authentication code, the authentication code The calculated and finally obtained authentication code 8 " _n is used as the authentication code.

(Encryption Algorithm) As shown in FIGS. 12 and 13, the encryption algorithm is the authentication code 8'applied to the field 8 with a predetermined key code K given to the data to be encrypted, for example 8A _n , 8B _n. a _n, to calculate the 8'b _n, further these data 8'A _n, 8'A _n or 8'b _n as a key code 8'b _n
Feeling 8 and then authenticating code 8 "
Get A _n , 8 "B _n .

As described above, the recognition code calculated by the type approval is such that the encryption code of the final data is used as the authentication code while sequentially encrypting the data of each address, so that most of the data of each address is Even if they match, if there is an error in one piece of data, the calculated authentication code will be different, making it extremely difficult to modify the program.

[0035]

[Effect] As described above, the microprocessor for a gaming machine according to the present invention calculates for the first time an application program that has received type approval, while encrypting the bit data of the program and the entire data based on a predetermined algorithm. Then, the authentication code is added, and the microprocessor that controls the machine by reading it calculates the authentication code in advance, and it is configured to operate normally only when they match. It is possible to sufficiently prevent the modification of the program, the modification of the data, and the like, which often occur in the processor. Also, for the pachinko machine manufacturer, only the non-volatile storage means that stores the application program and the authentication code that have been certified in the model application for one device need only be copied, so each model is certified. There is no need.

Further, since the modification of the program is prevented, the player can always play with a healthy game machine, and the player's expectation value is not betrayed. Although there is an unauthorized program that fails the check even if it is authenticated and operates beyond a predetermined program area, the microprocessor according to the present invention is configured to constantly monitor the address area even if it is a legitimate one. Therefore, it is possible to eliminate fraud caused by omission of checks.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a microprocessor according to the present invention.

FIG. 2 is a block diagram showing an operation relationship of a microprocessor.

FIG. 3 is a flowchart showing the operation of the microprocessor.

FIG. 4 is a block diagram showing a configuration example of an AP execution time monitor.

FIG. 5 is a block diagram showing a configuration example of an AP execution address monitor.

FIG. 6 is a schematic diagram showing the encryption of the external ROM by the issuing machine and the operation of the processor when determining the suitability of the AP.

FIG. 7 is a schematic diagram of a second embodiment showing the encryption of the external ROM by the issuing machine and the operation of the processor when determining the suitability of the AP.

FIG. 8 is a schematic diagram of a third embodiment showing the encryption of the external ROM by the issuer and the operation of the processor when determining the suitability of the AP.

FIG. 9 is a schematic diagram of a fourth embodiment showing the encryption of the external ROM by the issuing machine and the operation of the processor when determining the suitability of the AP.

FIG. 10 is a block diagram showing an algorithm 1 for calculating an authentication code of 16-bit data.

FIG. 11 is a block diagram showing an algorithm 2 for calculating an authentication code of 8-bit data.

FIG. 12 is a block diagram showing an algorithm 3 for calculating an authentication code of 16-bit data.

FIG. 13 is a block diagram showing an encryption algorithm for 16-bit data.

[Explanation of symbols]

 1 CPU 2 AP execution address monitor (IATG) 3 AP execution time monitor (BWDT) 4 Work RAM for control 5 Work RAM for AP 6 RAM size limiter 7 Program memory bank switch 8 External bus gate 9 Mode controller 10 Built-in ROM 12 Program memory I / O device 14 External ROM 16 Counter 18 Comparator 20, 21 Address register 23, 24 Comparator

Claims (6)

[Claims] 1. A user storage unit storing an application program stored in a predetermined area and an authentication code encrypted from the application program based on a predetermined algorithm, and an authentication code calculated from the application program. A built-in chip storage means in which one or more key codes for algorithm and authentication code calculation are stored, an application program input from the user storage means, an authentication code calculation program and key code stored in the chip built-in storage means A central processing unit (C) for calculating the authentication code from the CPU and comparing the authentication code with the authentication code read in advance from the user storage means.
PU) and activates the means for observing the execution address of the application program or the means for observing the execution time of the application program when the authentication code does not match as a result of comparison by the central processing unit, and executes the application program, A microprocessor for a gaming machine configured to stop the operation of the device when the program exceeds the area or when the program execution time has passed a predetermined time, and execute the application program when the authentication codes match by comparison. 2. An application program stored in a predetermined area, a user storage unit storing an authentication code and the like encrypted from the application program based on a predetermined algorithm, and an authentication code calculated from the application program. From the chip built-in storage means that stores the algorithm and one or more key codes for calculating the authentication code, the application program input from the user storage means, and the authentication code calculation program and the key code stored in the chip built-in storage means A central processing unit (CPU) that calculates the authentication code and compares the authentication code with the authentication code read in advance from the user storage means. An application when the authentication code does not match as a result of the comparison by the central processing unit. Prog The system monitors the execution address of the system or the means for monitoring the execution time of the application program and executes the application program, and stops the operation of the device when the program exceeds the area or when the program execution time elapses for a predetermined time. And activating means for monitoring the execution address of the application program when the authentication codes match by comparison, and stopping the operation of the device or resetting the CPU and executing the program when the program exceeds a predetermined area. Microprocessor for gaming machines. 3. The plurality of authentication codes stored in the user storage means are C ₁ , C ₂ calculated based on a plurality of key codes K ₁ , K ₂ , K ₃ , ... K _i , ... K _n , respectively. , C ₃ , ... C _i , ...
C _n consists, the key code stored in the chip built-in storage means the plurality of key codes _{K 1, K 2, K 3} , ... K i, ... is any one K _i of the K _n, the central 3. The microprocessor for gaming machine according to claim 1 or 2, wherein the authentication code of the user storage means to be compared by the processing device is the authentication code C _i calculated based on the key code K _i . 4. The authentication code stored in the user storage means, a plurality of first primary key code _{K 1, K 2, K 3} , ... K i, ...,
Multiple primary authentication codes calculated based on K _n
C ₁ , C ₂ , C ₃ , ... C _i , ..., C _n and the primary authentication code C ₁ ,
_{C 2, C 3, ... C} i, ..., C n and consists secondary authentication code C _20, which is calculated based on second-order key code K _b, the key code stored in the chip built-in storage means the plurality primary key code K _1, K _2, K ₃ of, ... K _i, ..., any one of the K _n K _i
And the secondary key code K _b , and the authentication code of the user storage means to be compared by the central processing unit is an arbitrary primary authentication code C _i calculated based on the primary key code K _i and the secondary key code K _b. The gaming machine microprocessor according to claim 1 or 2, wherein the authentication code is C ₂₀ . 5. The authentication code stored in the user storage unit, an intermediate authentication code C ₀ and a plurality of first primary key code K ₁ calculated based on one of the intermediate key codes _{K 0, K 2, K 3} ,
... K _i, ..., the primary authentication code encrypted based on K _n
C ₁ , C ₂ , C ₃ , ... C _i , ..., C _n and the primary authentication code C ₁ ,
The secondary authentication code C ₂₀ calculated based on C ₂ , C ₃ , ... C _i , ..., C _n and the secondary key code K _b , and the key code stored in the chip built-in storage means is the intermediate key. Code K
_0, and the plurality of primary key codes K ₁ , K ₂ , K ₃ , ... K _i ,
, An arbitrary one of K _n , K _i , and the secondary key code K _b , the authentication code of the user storage means to be compared by the central processing unit was calculated based on the primary key code K _i . The microprocessor for gaming machine according to claim 1 or 2, wherein the primary authentication code C _i and the secondary authentication code C ₂₀ are arbitrary. 6. The microprocessor for a gaming machine according to claim 1, wherein the user storage means is a readable / writable non-volatile storage means, and the chip built-in storage means is a non-volatile read-only storage means. .