JPH06326890A - Synchronizing signal generating circuit - Google Patents

Abstract

PURPOSE:To provide the synchronizing signal generating circuit with simple configuration and less power consumption by devising the circuit such that a rising waveform and a falling waveform of a synchronizing signal used for a video equipment are formed with high accuracy in compliance with standards. CONSTITUTION:A ternary waveform generating circuit 1 generates a ternary waveform in which a gradient of both a rising and falling waveforms is steep and a ternary waveform being an output from the ternary waveform generating circuit 1 is delayed by delay elements 2-5 for prescribed time and the ternary waveform being an output from the ternary waveform generating circuit 1 and the waveform obtained by the delay circuits 2-5 are added by a prescribed ratio, then the ternary waveform with a stepwise waveform that the rising and falling portions are divided is obtained. The ternary waveform is given to a low pass filter 7, in which a high frequency component is eliminated to generate a ternary synchronizing signal satisfying the prescribed rising and falling characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal generating circuit used in video equipment, and more particularly to a synchronizing signal generating circuit capable of defining rising and falling waveforms of the synchronizing signal.

[0002]

2. Description of the Related Art In connection with video equipment such as a VTR, a TV and a camera, a synchronization signal is used in an image transmission system to synchronize the reproduction operation on the receiving side with that on the transmitting side. The types of sync signals are black burst, binary signal, and 3
Value signals and the like are known, and the standard is set for each synchronization signal according to the intended use. For example, in the three-valued sync signal of the BTA standard used for high-definition, the low-level and high-level pulse widths of the sync signal and the rising and falling times are defined by the standard. Then, the slope of the waveform is determined by the prescribed rise / fall time, and the reference signal phase such as the horizontal synchronization reference phase at the zero cross point where the rising waveform of the ternary waveform crosses the pedestal level is obtained.

To generate a ternary waveform, for example, in a circuit having a relatively simple structure as shown in FIG. 2, voltages of "high" level, "middle" level and "low" level are input to a control terminal. It can be obtained by switching according to the control signal (FIG. 3 (a)). However, in general, the slope of rising and falling of the ternary waveform (FIG. 3A) obtained by the above circuit is steep, and the slope of time defined in the standard cannot be formed. Moreover, the accuracy is not guaranteed. Therefore, conventionally, a highly accurate ternary signal has been obtained by forming the rising and falling waveforms with digital data.

FIG. 6 shows an example of the configuration of the conventional ternary sync signal generating circuit. A counter 60 and a decoder 61 are used to generate several-bit digital data for forming a ternary signal waveform based on a basic clock inside the video equipment. At this time,
The waveforms at the rising and falling portions are digital data finely divided according to the number of bits used. A waveform obtained by D / A converting the digital data by the D / A (digital / analog) converter 62 is shown in FIG.

The rising and falling portions of the waveform are stepwise waveforms that are finely divided according to the number of bits. After that, the high-pass component is removed by the low-pass filter 63,
A ternary synchronization signal without jaggedness as shown in FIG. 7B was obtained. In addition, the digital data of the ternary synchronization signal is RO
In some cases, digital data stored in a memory such as M and read from a ROM at a required timing is D / A converted to obtain a ternary synchronization signal.

[0006]

However, in the above-mentioned conventional synchronizing signal generating circuit, circuits such as a counter and a decoder for generating digital data and a high-speed D /
The A converter is required, the circuit becomes complicated, and the power consumption increases. Further, the method using a memory also has problems in terms of circuit scale and power consumption.

The present invention solves such a problem, and has a simple circuit structure for a rise time at a time specified in the standard.
It is an object of the present invention to provide a synchronizing signal generation circuit that can form a ternary signal having a falling waveform and consumes less power.

[0008]

In order to achieve the above object, the synchronizing signal generating circuit of the present invention has a plurality of delay means for delaying an input signal, and outputs the input signal or an output from each delay means. It is characterized by comprising an adding means for adding and a low-pass filter for attenuating the high frequency component of the output signal from the adding means.

[0009]

In the synchronizing signal generating circuit of the present invention having the above structure, the rising and falling waveforms of the synchronizing signal waveform are added with the signal waveform obtained by the delay means, and the high frequency component of the waveform is removed by the low pass filter. To be formed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a synchronization signal generation circuit according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 is a 3 for generating a ternary waveform.
A ternary waveform generation circuit which is a value waveform generation means, 2 to 5 are delay elements which are delay means which delay the ternary waveform generated by the ternary waveform generation circuit 1 for a predetermined period, 6 is a ternary waveform and each delay An adder, which is an adding means for adding the output waveforms from the elements at a predetermined ratio, 7 is a low-pass filter that attenuates high-frequency components of the output signal from the adder 6, and 8 is an output terminal.

Next, the operation of the synchronizing signal generating circuit in this embodiment will be described. First, the ternary waveform generation circuit 1 can be realized by, for example, a circuit having a relatively simple configuration as shown in FIG. The ternary waveform has "high" level, "medium" level,
By switching the "low" level voltage according to the control signal input to the control terminal, a ternary rectangular wave as shown in FIG. 3 (a) can be obtained. Generally, a circuit as described above is used. It has been described in the prior art that the rising and falling waveforms of the generated ternary waveform (FIG. 3A) have steep slopes and are not formed at the slopes of time defined in the standard.

Such a ternary waveform (FIG. 3A) generated by the ternary waveform generating circuit 1 is input and delayed by delay elements 2 to 5 for a predetermined time, and output from the ternary waveform generating circuit 1. And the waveforms obtained from the respective delay circuits 2 to 5 are added at a predetermined ratio, a ternary waveform having a stepwise waveform in which the rising and falling portions are divided is obtained (Fig. 3 (b)). This ternary waveform is applied to the low pass filter 7
By removing the high frequency component through the signal, a ternary sync signal (Fig.
(C)) is generated.

The number of divisions of the rising / falling waveform of the ternary synchronizing signal at this time is determined by the number of delay elements, and the rising / falling time t1 (FIG. 3 (c)).
Is determined by the total delay time of each delay element. Therefore, by setting the delay time of the delay element appropriately, the desired rising / falling waveform conforming to the standard can be obtained.
A value sync signal can be formed.

Next, FIG. 4 is a circuit configuration diagram of another embodiment of the present invention in which a binary signal is used as an input signal and a ternary signal having rise and fall times defined by the standard is generated.
Shown in.

In FIG. 4, 9 and 10 are input terminals for inputting a binary signal, 11 is a clock input terminal, and 12
˜19 are shift registers operated by a clock, 20
˜29 are resistors for adding the input signal and the output from the shift register at a predetermined ratio, 30 is a low pass filter for attenuating the high frequency components of the added signals, and 31 is an output terminal. In this embodiment, a shift register is used as the delay means, and a resistance ratio addition is used as the addition means.

First, as one method of generating a ternary signal from a binary signal, the ternary waveform is converted from the "middle" level to the "high" level waveform portion (FIG. 5A) and from the "low" level to the "low" level. There is a method in which the waveform is divided into waveform portions of medium level (FIG. 5B), the respective waveforms are formed by binary signals and then synthesized (FIG. 5C). Based on the above method, the synchronizing signal generation circuit of this embodiment generates a ternary signal having rise and fall times defined by the standard.

Below, FIG. 4 and the waveform diagram (FIG. 5A,
The circuit operation will be described with reference to (b), (d) and (e). The input terminals 9 and 10 are respectively connected to the input terminals (Fig. 5 (a),
A binary digital signal as shown in (b)) is input.
The waveform input to the input terminal 9 (FIG. 5 (a)) is the waveform from the “medium” level to the “high” level of the ternary sync signal, and the waveform input to the input terminal 10 (FIG. 5 (b)) is It is a digital signal that forms a "low" to "medium" level waveform.

The binary digital signal input to each of the input terminals 9 and 10 is delayed by a clock cycle according to the clock input from the input terminal 11, and output from each of the shift registers 12 to 19. By adding the output waveforms from the respective shift registers according to a predetermined resistance ratio of the resistors 20 to 29, a ternary waveform having a stepwise waveform in which the rising and falling portions are divided is obtained (FIG. 5 ( d)). This ternary waveform is passed through the low pass filter 30
By removing the high frequency component, the ternary sync signal (Fig.
(E)) is generated.

At this time, the number of divisions of the rising / falling waveform of the ternary synchronizing signal is determined by the number of shift registers, and the rising / falling time t2 (see FIG. 5).
(E)) is determined by the delay time generated by each shift register. Therefore, by adjusting the clock frequency input to the shift register and setting an appropriate delay time, it is possible to form a ternary synchronization signal having desired rising and falling waveforms according to the standard.

[0021]

As described above, the synchronizing signal generating circuit of the present invention can form the rising and falling waveforms of the synchronizing signal of high precision according to the standard with a simple circuit configuration, and the D /
Since it does not require an A converter, a memory, etc., it has a great effect that it can be realized with a simple configuration and power consumption can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a ternary waveform generation circuit.

FIG. 3 is a waveform diagram illustrating the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of a synchronization signal generation circuit according to another embodiment of the present invention.

5 is a waveform diagram illustrating the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing an example of a conventional synchronization signal generation circuit.

FIG. 7 is a waveform diagram illustrating the operation of the conventional example of FIG.

[Explanation of symbols]

 1 Tri-level waveform generation circuit 2-5 Delay element 6 Adder 7 Low-pass filter 8 Output terminal 9, 10 Input terminal 11 Clock input terminal 12-19 Shift register 20-29 Resistor 30 Low-pass filter 31 Output terminal

Front page continued (72) Inventor Hideo Nagao 4-3-1, Tsunashima-higashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.

Claims (2)

[Claims] 1. A ternary waveform generating means for generating a ternary waveform in response to an input, and a plurality of delay means for delaying the generated ternary waveform, wherein output waveforms from the respective delay means are provided. Adder means for adding or for adding the ternary waveform obtained from the ternary waveform generating means and the output waveform from each of the delay means, and a low band for attenuating the high frequency component of the output signal from the adding means. A synchronization signal generation circuit including a pass filter. 2. A waveform having at least one input terminal, a plurality of delay means for delaying a binary input signal input to each of the input terminals, and an output waveform from each of the delay means. Or adding means for adding the binary input signal and the output waveform from each of the delay means, and a low-pass filter for attenuating the high frequency component of the output signal from the adding means. Synchronous signal generation circuit.