JPH06314977A - Current output type d/a converter circuit - Google Patents

Current output type d/a converter circuit

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Publication number
JPH06314977A
JPH06314977A JP10255193A JP10255193A JPH06314977A JP H06314977 A JPH06314977 A JP H06314977A JP 10255193 A JP10255193 A JP 10255193A JP 10255193 A JP10255193 A JP 10255193A JP H06314977 A JPH06314977 A JP H06314977A
Authority
JP
Japan
Prior art keywords
output
current
resistor
circuit
mirror circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10255193A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Nakajima
光啓 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP10255193A priority Critical patent/JPH06314977A/en
Publication of JPH06314977A publication Critical patent/JPH06314977A/en
Withdrawn legal-status Critical Current

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To set the variable range of the output current optional by connecting a reference current source to a 1st current mirror circuit, using an output of a 1st amplifier for a reference potential application point and giving 1st to n-th outputs of a 2nd current mirror circuit to n-sets of weighting terminals of an R-2R resistor ladder circuit. CONSTITUTION:A current of a reference current source 1 is given to a 1st current mirror circuit comprising transistors(TRs) 2-3 and resistors 5-7, its 1st output is inputted to a current-voltage circuit comprising a resistor 9 and an amplifier 8, in which the output is converted into a voltage and it is used for a reference voltage for an R-2R ladder circuit comprising resistors 24-29. A 2nd output of the 1st current mirror circuit is given to a 2nd current mirror circuit having n-sets of outputs comprising TRs 10-14 and resistors 15-19 and n-sets of outputs are given to n-sets of control current terminals to the R-2R resistor ladder circuit via switches 20-23 to decide an output voltage of the R-2R resistor ladder circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はデジタル/アナログ変換
回路に関し、特に電流出力型デジタル/アナログ変換回
路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog conversion circuit, and more particularly to a current output type digital / analog conversion circuit.

【0002】一般に、電流出力型デジタル/アナログ変
換回路として入力された基準電流をもとにし、デジタル
入力信号で出力電流を制御する回路がある。
Generally, there is a circuit that controls an output current by a digital input signal based on a reference current input as a current output type digital / analog conversion circuit.

【0003】従来の電流出力型デジタル/アナログ変換
回路の一例を図2に示す。
An example of a conventional current output type digital / analog conversion circuit is shown in FIG.

【0004】図において同一形状のトランジスタ36と
トランジスタ37,同一抵抗値の抵抗38と抵抗39で
構成し、抵抗38と抵抗39の一方の端子は電源端子に
接続した第1のカレントミラー回路で、前記カレントミ
ラー回路の入力は基準電流源1に接続し、出力は第2の
カレントミラー回路の入力に接続する。
In the figure, transistors 36 and 37 of the same shape, resistors 38 and 39 of the same resistance value are formed, and one terminal of the resistors 38 and 39 is a first current mirror circuit connected to the power supply terminal. The input of the current mirror circuit is connected to the reference current source 1, and the output is connected to the input of the second current mirror circuit.

【0005】第2のカレントミラー回路は、カレントミ
ラー回路の入力となるトランジスタ40と抵抗45を通
し接地し、第1の出力はトランジスタ40と同一のトラ
ンジスタ41と抵抗45と同一抵抗値の抵抗46とデジ
タル入力信号の第1のビットで制御するスイッチ20で
接地した回路で構成する基準電流源と同じ電流を出力
し、第2の出力はトランジスタ40の2倍の面積のトラ
ンジスタ42と抵抗45の1/2の値の抵抗47とデジ
タル入力信号の第2のビットで制御するスイッチ21で
接地した回路で構成し、基準電流源の2倍の電流を出力
し、第3の出力はトランジスタ40の4倍の面積を持つ
トランジスタ43と抵抗45の1/4の抵抗値の抵抗4
8とデジタル入力信号の第3のビットで制御するスイッ
チ22で接地した回路で構成し基準電流源の4倍の電流
を出力し、同様に第nの出力はトランジスタ40の2
n-1 倍の面積を持つトランジスタ44と抵抗45の2
n-1 分の1の抵抗値の抵抗49とデジタル入力信号の第
nのビットで制御するスイッチ23で接地した回路で構
成し基準電流源の2n-1 倍の電流を出力する回路で構成
し、第2のカレントミラー回路の第1の出力から第nの
出力までを全てに接続する出力端子を有している。
The second current mirror circuit is grounded through a transistor 40 and a resistor 45 which are inputs to the current mirror circuit, and a first output is the same transistor 41 as the transistor 40 and a resistor 46 having the same resistance value as the resistor 45. And the same current as the reference current source configured by the circuit grounded by the switch 20 controlled by the first bit of the digital input signal, and the second output of the transistor 42 and the resistor 45 having a double area of the transistor 40 and the resistor 45. It is composed of a circuit grounded by a resistor 47 having a value of ½ and a switch 21 controlled by the second bit of the digital input signal, and outputs a current twice as high as that of a reference current source. The third output is a transistor 40. A transistor 43 having a quadruple area and a resistor 4 having a resistance value ¼ that of the resistor 45
8 and a switch 22 which is controlled by the third bit of the digital input signal, which is grounded to output a current four times as high as that of the reference current source.
2 of transistor 44 and resistor 45 with n-1 times the area
It is composed of a circuit which is grounded by a resistor 49 having a resistance value of 1 / n-1 and a switch 23 which is controlled by the n-th bit of a digital input signal, and which outputs a current of 2 n-1 times that of a reference current source. However, it has an output terminal for connecting all of the first output to the nth output of the second current mirror circuit.

【0006】次に、従来例の動作について説明する。Next, the operation of the conventional example will be described.

【0007】n個のビットで構成するデジタル入力信号
を各々のスイッチに入力し、第1のビットの信号のみが
Hになるとスイッチ20がONして出力端子に基準電流
源と同じ電流が流れ、第2のビットの信号のみがHにな
るとスイッチ21がONして出力端子に基準電流源の2
倍の電流が流れ、第1のビットと第2のビットが同時に
ONすれば出力端子に基準電流源の3倍の電流が流れ
る。同様にn個のビットの全てがONすれば2n −1倍
の電流が出力端子に流れるデジタル/アナログ変換回路
である。
When a digital input signal composed of n bits is input to each switch and only the signal of the first bit becomes H, the switch 20 is turned on and the same current as the reference current source flows to the output terminal. When only the signal of the second bit becomes H, the switch 21 is turned on and the output terminal has the reference current source 2
A double current flows, and if the first bit and the second bit are turned on at the same time, a current three times that of the reference current source flows to the output terminal. Similarly, if all of the n bits are turned on, a current of 2 n -1 times flows in the output terminal, which is a digital / analog conversion circuit.

【0008】したがって出力端子に流れる電流をIOUT
とし、基準電流源の電流値をIrefとすると次式で表
わすことができる。
Therefore, the current flowing through the output terminal is represented by I OUT
And the current value of the reference current source is Iref, it can be expressed by the following equation.

【0009】IOUT =Iref (Z1 +2Z2 +4Z3
…+2n-1 n ) Zn は第nのビットがON時1、OFF時0を代入す
る。
I OUT = I ref (Z 1 + 2Z 2 + 4Z 3 +
... + 2 n-1 Z n ) Z n is substituted with 1 when the n-th bit is ON and 0 when it is OFF.

【0010】[0010]

【発明が解決しようとする課題】この従来の電流出力型
デジタル/アナログ変換回路では、基準電流源の電流値
を元に整数倍の電流値の制御しかできず、可変範囲を任
意に選べず、また可変する電流値は基準電流源の電流値
により限定される問題がある。
In this conventional current output type digital / analog conversion circuit, only the current value of an integral multiple can be controlled based on the current value of the reference current source, and the variable range cannot be arbitrarily selected. Further, there is a problem that the variable current value is limited by the current value of the reference current source.

【0011】又、出力電流のリニアリティを得る為に
は、カレントミラー回路を構成するトランジスタの面積
比が重要となり、デジタル入力信号のビットが多くなる
とカレントミラー回路を構成するトランジスタが指数的
に増加し、又微少な範囲を可変する為には、基準電流源
の電流値が少なくする必要があり、カレントミラー回路
を構成する抵抗値が大きくなると言う問題がある。
Further, in order to obtain the linearity of the output current, the area ratio of the transistors forming the current mirror circuit is important, and when the number of bits of the digital input signal increases, the transistors forming the current mirror circuit exponentially increase. Further, in order to change the minute range, it is necessary to reduce the current value of the reference current source, which causes a problem that the resistance value forming the current mirror circuit becomes large.

【0012】次に実際の値を入れて詳細に説明すると、
4個のビットのデジタル入力信号により出力電流値を1
5μAから30μAの間で可変する電流入力−電流出力
型デジタル/アナログ変換回路を考える。
[0012] Next, the actual value will be described in detail.
Output current value is set to 1 by digital input signal of 4 bits
Consider a current input-current output type digital / analog conversion circuit that is variable between 5 μA and 30 μA.

【0013】4個のビットのデジタル入力信号は16ス
テップの設定となる為、可変する電流値を可変ステップ
で割ると1ステップ当り1μAの変化が必要となり、こ
れを基準電流源の電流値とするが、このままだと0μA
から15μAまでの可変しかできない為、基準電流源以
外に15μAの電流源を出力端子に接続する必要があ
り、この2個目の電流源を使用することにより15μA
から30μAまでの可変が可能となる。
Since the 4-bit digital input signal is set in 16 steps, if the variable current value is divided by the variable step, a change of 1 μA is required per step, and this is taken as the current value of the reference current source. However, if this is left, 0 μA
It is necessary to connect a current source of 15μA to the output terminal in addition to the reference current source because it is only possible to change from 15μA to 15μA. By using this second current source,
It is possible to change from 1 to 30 μA.

【0014】次にカレントミラー回路を構成する抵抗値
について考えると、ICの内部で使用する場合、トラン
ジスタや抵抗のバラツキを考えると抵抗の両端に発生す
る電圧を0.3V程度に設定する必要があり、基準電流
源の電流値が1μAとすると第1のカレントミラー回路
では300KΩの抵抗が2本必要となる。
Considering the resistance value of the current mirror circuit, when used inside the IC, it is necessary to set the voltage generated at both ends of the resistor to about 0.3 V in consideration of variations in transistors and resistors. If the current value of the reference current source is 1 μA, the first current mirror circuit requires two 300 KΩ resistors.

【0015】又、第2のカレントミラー回路でも300
KΩの抵抗が2本、150KΩの抵抗が1本、など高抵
抗値の抵抗が数多く必要となり、ICでの使用には無理
がある。
In addition, the second current mirror circuit also has 300
A large number of resistors having high resistance values, such as two KΩ resistors and one 150 KΩ resistor, are required, and it is impossible to use them in ICs.

【0016】[0016]

【課題を解決するための手段】本発明の電流出力型デジ
タル/アナログ変換回路は基準電流源を、2つの出力を
持つ第1のカレントミラー回路の入力となる第1のトラ
ンジスタのコレクタに接続し、前記第1のカレントミラ
ー回路を構成する3個のトランジスタのエミッタは抵抗
を介して電源端子に接続され、第1の出力は第1の増幅
器と第1の抵抗とで構成される電流−電圧変換回路の入
力に接続され、前記第1の抵抗は接地され基準電流と抵
抗値を乗算した電圧を発生し、増幅率1倍の第1の増幅
器を通してR−2R抵抗ラダー回路の等電位端子として
入力される。
In the current output type digital-analog converter circuit of the present invention, a reference current source is connected to a collector of a first transistor which is an input of a first current mirror circuit having two outputs. , The emitters of the three transistors forming the first current mirror circuit are connected to a power supply terminal via a resistor, and the first output is a current-voltage composed of a first amplifier and a first resistor. The first resistor is connected to the input of the conversion circuit and is grounded to generate a voltage obtained by multiplying the reference current and the resistance value. The first resistor serves as an equipotential terminal of the R-2R resistance ladder circuit through the first amplifier having a gain of 1. Is entered.

【0017】前記第1のカレントミラー回路の第2の出
力はn個の出力を持つ第2のカレントミラー回路の入力
となる第2のトランジスタのコレクタに接続され、前記
第2のカレントミラー回路の入力を構成する前記第2の
トランジスタのエミッタは第2の抵抗を介して接地さ
れ、第1の出力を構成する第3のトランジスタは第3の
抵抗とデジタル入力信号の第1のビットで制御する第1
のスイッチで接地し、第2の出力を構成する第4のトラ
ンジスタは第4の抵抗と前記デジタル入力信号の第2の
ビットで制御する第2のスイッチで接地し、同様に第n
の出力を構成する第5のトランジスタは第5の抵抗と前
記デジタル入力信号の第nのビットで制御する第nのス
イッチで接地され前記第2のカレントミラー回路の第1
の出力から第nの出力までは前記R−2R抵抗ラダー回
路のn個の重み付け端子に入力される。
The second output of the first current mirror circuit is connected to the collector of the second transistor which is the input of the second current mirror circuit having n outputs, and the second output of the second current mirror circuit is connected. The emitter of the second transistor forming the input is grounded via the second resistor, and the third transistor forming the first output is controlled by the third resistor and the first bit of the digital input signal. First
The fourth transistor which constitutes the second output is grounded by the fourth switch and the second switch which is controlled by the second bit of the digital input signal.
Is connected to the fifth resistor and the n-th switch controlled by the n-th bit of the digital input signal to ground and the first transistor of the second current mirror circuit.
From the output to the nth output are input to the n weighting terminals of the R-2R resistance ladder circuit.

【0018】前記R−2R抵抗ラダー回路の出力は第2
の増幅器の非反転入力に接続し、前記第2の増幅器は、
出力を第6のトランジスタのベースに入力し、前記第6
のトランジスタのエミッタは、前記第2の増幅器の反転
入力に接続するのと第6の抵抗を介して接地し、電圧−
電流変換回路を構成し、前記トランジスタのコレクタは
出力端子に接続する電圧−電流変換回路を備えている。
The output of the R-2R resistance ladder circuit is the second
Connected to the non-inverting input of an amplifier of
The output is input to the base of the sixth transistor,
The emitter of the transistor is connected to the inverting input of the second amplifier and is grounded via a sixth resistor,
A current conversion circuit is provided, and the collector of the transistor is provided with a voltage-current conversion circuit connected to the output terminal.

【0019】[0019]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0020】図1は本発明の一実施例を示す回路図であ
る。
FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【0021】基準電流源1の電流をトランジスタ2,
3,4と抵抗5,6,7で構成する2個の出力を持つ第
1のカレントミラー回路の入力に接続し、前記第1のカ
レントミラー回路の第1の出力より抵抗9と増幅器8で
構成する電流−電圧回路に入力して電圧に変換し、抵抗
24から抵抗29で構成するR−2R抵抗ラダー回路の
基準電圧とする。
The current of the reference current source 1 is supplied to the transistors 2 and 2.
3 and 4 and resistors 5, 6 and 7 are connected to the input of a first current mirror circuit having two outputs, and a resistor 9 and an amplifier 8 are connected from the first output of the first current mirror circuit. The voltage is input to the current-voltage circuit to be converted and converted into a voltage, which is used as the reference voltage of the R-2R resistance ladder circuit composed of the resistors 24 to 29.

【0022】基準電流源1の電流値をIref とし、電流
−電圧回路の出力の電圧をVref とすると Vref =R9×Iref となる。
[0022] The current value of the reference current source 1 and I ref, current - becomes the voltage of the output of the voltage circuit to V ref and V ref = R9 × I ref.

【0023】次に、前記第1のカレントミラー回路の第
2の出力はトランジスタ10からトランジスタ14と抵
抗15から抵抗19で構成するn個の出力を持つ第2の
カレントミラー回路の入力に接続し、そのn個の出力は
デジタル入力信号で制御されるスイッチ20からスイッ
チ23によって前記R−2R抵抗ラダー回路へのn個の
コントロール電流端子に入力し、R−2R抵抗ラダー回
路の出力電圧を決める。
Next, the second output of the first current mirror circuit is connected to the input of a second current mirror circuit having n outputs composed of transistors 10 to 14 and resistors 15 to 19. , The n outputs are input to the n control current terminals to the R-2R resistance ladder circuit from the switch 20 controlled by the digital input signal by the switch 23 to determine the output voltage of the R-2R resistance ladder circuit. .

【0024】R−2R抵抗ラダー回路の基準抵抗値をR
とするとR−2R抵抗ラダー回路の出力電圧VR-2Rは VR-2R=Vref −R×Iref ×(Zn +…+Z2 /2
n-1 +Z1 /2n ) Zn は第nのビットがON時1、OFF時0を代入す
る。となる。
The reference resistance value of the R-2R resistance ladder circuit is R
When the output voltage V R-2R of R-2R resistor ladder circuit is V R-2R = V ref -R × I ref × (Z n + ... + Z 2/2
n-1 + Z 1/2 n) Z n substitutes bit time ON 1, OFF time 0 in the n. Becomes

【0025】R−2R抵抗ラダー回路の出力は増幅器3
0,トランジスタ31と抵抗32で構成する電圧−電流
回路の入力に接続され、トランジスタ31のコレクタは
出力端子に接続し電流出力型デジタル/アナログ変換回
路を構成する。
The output of the R-2R resistance ladder circuit is the amplifier 3
0, connected to the input of the voltage-current circuit composed of the transistor 31 and the resistor 32, and the collector of the transistor 31 is connected to the output terminal to form a current output type digital / analog conversion circuit.

【0026】この回路の出力電流Iout は次の式で求ま
る。
The output current I out of this circuit is obtained by the following equation.

【0027】IOUT =VR-2R/R32 =(R9/R32)Iref −(R/R32)Iref (Z
n +…+Z2/2n-1 +Z1 /2n ) 従来例で説明した、4個のビットのデジタル入力信号に
より、出力電流値を15μAから30μAの間で可変す
る電流出力型デジタル/アナログ変換回路を考える。
I OUT = V R-2R / R32 = (R9 / R32) I ref- (R / R32) I ref (Z
n + ... + Z 2/2 n-1 + Z 1/2 n) described in the conventional example, the four-bit digital input signal, the current output type digital / analog variable between the output current value from 15μA to 30μA Consider a conversion circuit.

【0028】まず出力電流の最大電流値30μAは、次
の式で求まる。
First, the maximum current value 30 μA of the output current is obtained by the following equation.

【0029】Iout =(R9/R32)Iref ここで基準電流源の電流値を60μAとし、電流−電圧
変換回路の出力電圧を3.6Vとすると R9=60KΩ,R32=120KΩ となる。
I out = (R9 / R32) I ref If the current value of the reference current source is 60 μA and the output voltage of the current-voltage conversion circuit is 3.6 V, then R9 = 60 KΩ and R32 = 120 KΩ.

【0030】次に出力電流の最小電流値15μAは、次
の式で求まる。
Next, the minimum current value 15 μA of the output current is obtained by the following equation.

【0031】Iout =(R9/R32)Iref −(R/
R32)Iref (8/15) R=16KΩ となる。又カレントミラー回路を構成する抵抗は、5K
Ωとなり、ICでの使用でも問題ない値である。
I out = (R9 / R32) I ref − (R /
R32) I ref (8/15) R = 16 KΩ. Also, the resistance that constitutes the current mirror circuit is 5K.
Ω, which is a value that can be used in an IC without any problem.

【0032】[0032]

【発明の効果】以上説明したように本発明は、基準電流
源の電流値に関係なく、出力端子の電流値を決めること
ができる様にしたので、出力電流の可変範囲を任意に設
定することができ、又、デジタル入力信号のビット数が
増えても、微少な範囲の可変に対しても、トランジスタ
の個数や抵抗の値を小さくすることができ、IC化にお
いてチップの縮小に対して効果があるという結果を有す
る。
As described above, according to the present invention, the current value of the output terminal can be determined regardless of the current value of the reference current source. Therefore, the variable range of the output current can be set arbitrarily. Moreover, even if the number of bits of the digital input signal is increased, the number of transistors and the resistance value can be reduced even if the range is changed in a minute range, which is effective for reducing the size of a chip in an IC. Have the result that there is.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例の回路図FIG. 1 is a circuit diagram of an embodiment of the present invention.

【図2】従来の例の回路図FIG. 2 is a circuit diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1 基準電流源 2〜4,10〜14,31,36〜37,40〜44
トランジスタ 5〜7,9,15〜19,24〜29,32,38,3
9,45〜49 抵抗 8,30 増幅器 20〜23 スイッチ 33 入力端子 34 電源端子 35 出力端子
1 Reference current source 2 to 4, 10 to 14, 31, 36 to 37, 40 to 44
Transistors 5-7, 9, 15-19, 24-29, 32, 38, 3
9,45-49 Resistance 8,30 Amplifier 20-23 Switch 33 Input terminal 34 Power supply terminal 35 Output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 基準電流源を、2つの出力を持つ第1の
カレントミラー回路の入力に接続し、前記第1のカレン
トミラー回路の第1の出力は他端が接地された第1の抵
抗の一端と第1の増幅器の入力に接続し、該第1の増幅
器の出力を基準電位供給点となし、R−2R抵抗ラダー
回路の等電位端子を前記、基準電位供給点に接続し、前
記第1のカレントミラー回路の第2の出力は、n個の出
力を持つ第2のカレントミラー回路の入力に接続し、該
入力はエミッタが第2の抵抗を介して接地された第2の
トランジスタで構成され、前記第2のカレントミラー回
路の第1の出力を構成する第3のトランジスタは第3の
抵抗とデジタル入力信号の第1のビットで制御する第1
のスイッチを介して接地し、第2の出力を構成する第4
のトランジスタは第4の抵抗と前記デジタル入力信号の
第2のビットで制御する第2のスイッチを介して接地
し、同様に第nの出力を構成する第5のトランジスタは
第5の抵抗と前記デジタル入力信号の第nのビットで制
御する第nのスイッチを介して接地され、前記第2のカ
レントミラー回路の第1の出力から第nの出力までは前
記R−2R抵抗ラダー回路のn個の重み付け端子に入力
され、前記R−2R抵抗ラダー回路の出力は、第6のト
ランジスタのベースが出力に接続され、エミッタが他端
が接地された第6の抵抗の1端とともに反転入力に接続
された第2の増幅器の非反転入力に接続し、前記第6の
トランジスタのコレクタを電流出力端となすことを特徴
とした電流出力型デジタル/アナログ変換回路。
1. A reference current source is connected to an input of a first current mirror circuit having two outputs, and a first output of the first current mirror circuit has a first resistor whose other end is grounded. Connected to one end of the first amplifier and the input of the first amplifier, the output of the first amplifier serves as a reference potential supply point, the equipotential terminal of the R-2R resistance ladder circuit is connected to the reference potential supply point, and The second output of the first current mirror circuit is connected to the input of a second current mirror circuit having n outputs, the input of which is a second transistor whose emitter is grounded through a second resistor. And a third transistor constituting the first output of the second current mirror circuit is controlled by a third resistor and a first bit of the digital input signal.
Grounded via the switch of the 4th, which constitutes the 2nd output
Transistor is grounded via a fourth resistor and a second switch controlled by the second bit of the digital input signal, and a fifth transistor which similarly constitutes an nth output is connected to the fifth resistor and the fifth resistor. It is grounded via an nth switch controlled by the nth bit of the digital input signal, and n pieces of the R-2R resistance ladder circuit are provided from the first output to the nth output of the second current mirror circuit. Of the R-2R resistor ladder circuit, the output of the R-2R resistor ladder circuit is connected to the output, and the emitter is connected to the inverting input together with one end of the sixth resistor whose other end is grounded. Current output type digital / analog conversion circuit connected to the non-inverting input of the second amplifier, and the collector of the sixth transistor serves as a current output terminal.
JP10255193A 1993-04-28 1993-04-28 Current output type d/a converter circuit Withdrawn JPH06314977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10255193A JPH06314977A (en) 1993-04-28 1993-04-28 Current output type d/a converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10255193A JPH06314977A (en) 1993-04-28 1993-04-28 Current output type d/a converter circuit

Publications (1)

Publication Number Publication Date
JPH06314977A true JPH06314977A (en) 1994-11-08

Family

ID=14330386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10255193A Withdrawn JPH06314977A (en) 1993-04-28 1993-04-28 Current output type d/a converter circuit

Country Status (1)

Country Link
JP (1) JPH06314977A (en)

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