JPH06314239A - Processor system - Google Patents

Abstract

PURPOSE:To provide a system whose performance does not depend upon the number of processors or memory capacity. CONSTITUTION:In the system provided with the processors 11/12 provided with a cache memory 14, two or more storage devices 16 to 19, and nodes 1 to 9, the nodes 2/3 send a read-out instruction to a transmission line at the time of reading out information, and each corresponding node 4 to 7 sends the information stored in the storage device to the transmission line when it receives the read-out instruction, and each node 2/3 stores the read out information in a cache memory, and when another node sends the read-out instruction to a corresponding address, it sends the information stored in the cache memory corresponding to the address to the node having issued the read-out instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, a memory, a memory controller for controlling the memory, and an I / O.
The present invention relates to a processor system including an O device and an I / O controller that controls the I / O device, and relates to a method of transmitting and receiving information in the system and a method of updating the information.

[0002]

2. Description of the Related Art At present, there are various demands for a processor system such as high speed, large address space and memory capacity, or high reliability (multiplexing). A typical conventional processor system is Todd Lynch: "The SPAR
Csystem-600 Series Multiprocessors ", 1992 IEEE COMP
There are technologies described in CON. In the prior art, a plurality of processors, a memory controller and an I / O bus controller are connected to a multiprocessor bus. The memory controller connects a memory such as a magnetic disk device and controls access to the memory from each processor, and the I / O bus controller connects the I / O bus and the I / O bus. Control access to I / O devices. Each processor can be provided with a cache memory, and the data read out by designating an address from the memory is stored in the cache memory. Thereafter, the data at the address is read and written to the cache memory for high speed. Is being processed. Regarding the address stored in this cache memory, if another processor or controller accesses the memory,
The data at the address stored in the cache memory and the data at the address stored in the memory may not match. Therefore, in order to guarantee that they match, each processor The data transferred on the multiprocessor bus is monitored (hereinafter, this monitoring operation is called snoop). By this snoop, when another processor or controller accesses the address of the memory, each processor transfers the data of the address stored in the cache memory to the other processor, or the other processor. Before accessing the memory such as the above, the data of the address stored in the cache memory is transferred to and stored in the memory. The processor erases the data of the address from the cache memory after transferring the data of the address stored in the cache memory. This manages the cache memory.

However, in the conventional bus-coupled system, the number of processors, memory controllers, and I / O controllers accommodated on one bus is limited. Since this is affected by the propagation delay of the bus, the length of the bus is limited, and as a result, the number of processors and the like is limited. Therefore, if the bus transmission speed is increased, the number of processors and the like is further limited, and the bus transmission speed cannot be increased. Therefore, if a large-capacity memory is to be accommodated, a large number of memory controllers cannot be provided, so the degree of memory integration must be improved. Also, if an attempt is made to increase the number of I / O devices controlled by the I / O controller, I / O
The buses need to be multi-tiered, which significantly slows down access speed to I / O devices. Furthermore, when constructing a complete multiplexing system including memory and I / O devices, it is often necessary to sacrifice data transmission speed, memory capacity, and the number of I / O devices accommodated.

Another problem is that since the memory accommodated in one memory controller can be accessed only by one processor, it cannot be accessed by a plurality of devices at the same time, and the addresses are duplicated. Access conflict will occur even if it is not done. Furthermore, it is difficult to build a scalable system with a bus-coupled system.

To solve the above problem, a ring-shaped processor system can be constructed. For a ring-shaped processor system, see David B. Gustavson: "Th
e Scalable Coherent Interface and Related Standard
s Projects ", 1992 IEEE Micro. In the prior art, a plurality of processors, a memory controller, and an I / O controller are connected to a ring for unidirectional transmission, and a directory is used to store the cache memory. The management of the cache memory using the directory is the identification number of the cache memory or the memory having the data of the same address, instead of allowing the data of the same address to be stored in a plurality of cache memories. Each processor updates the cache memory having the address of the data and the memory each time the data in the cache memory is updated in order to guarantee the consistency of each data.

[0006]

However, in the processor system connected in the ring shape, each time the data in the cache memory is updated, the cache memory having the address of the data and the memory are updated.
The communication for cache management deteriorates the effective transmission performance of the ring.

Further, when the snoop function in the conventional bus-coupled system is applied to a processor system connected in a ring shape, when monitoring a transmission line, as in monitoring data transferred on the bus, The processing is complicated because it is not possible to monitor all transfer data.
For example, in a processor system connected in a ring,
The access from one processor to the memory controller to be connected next may not be monitored by another processor. Therefore, when accessing the data stored in the cache memory of the other processor, Consistency may not be guaranteed.

An object of the present invention is to provide a processor system which guarantees the consistency of data in the cache memory without any limitation on the number of devices such as processors.

[0009]

In order to solve the above problems, the present invention allocates a plurality of processors each provided with a cache memory for storing information and an address space in which each of the plurality of processors can read and write. Or 2
In a processor system having the above storage device and a node provided corresponding to each of the plurality of processors and the storage device, each node is connected to another node in a ring shape by a transmission line, Each node corresponding to the storage device monitors an address added to the information, and when the address matches the address assigned to the storage device, the reception means that receives the information and the reception means. If the received information is a read instruction based on the received information received in step 1, the information stored in the storage device corresponding to the address is sent to the node that issued the read instruction, and the received information is In the case of a write instruction, a transfer processing unit that writes the received information in the storage device corresponding to the address is provided, and the plurality of processors Each corresponding node stores the read information in the cache memory provided in the processor when the processor instructs the address and reads the information corresponding to the address by the read instruction, and the cache memory stores the read information. Management means for managing the address of the information to be stored in the storage device, sending means for sending the information including the address of the storage device and the read / write instruction to the address, and the address added to the information to monitor the address. Receiving means that uses the information as received information when the address matches the address managed by the managing means,
If the received information is a read instruction based on the received information received by the receiving means, instead of the read information of the address from the node corresponding to the storage device, the information is stored in the cache memory corresponding to the address. Sending information to the node that issued the read instruction,
When the received information is a write instruction, there is provided a transfer processing unit that performs a process of writing the received information in the cache memory corresponding to the address.

The transfer processing means of each node corresponding to the plurality of processors stores in the cache memory corresponding to the address instead of the read information of the address from the node corresponding to the storage device. When sending information to the node that issued the read instruction, if the read instruction is received before the node corresponding to the storage device receives the read instruction,
The information stored in the cache memory corresponding to the address is transmitted, a reception flag is set in the information so that the node corresponding to the storage device does not receive the read instruction, and the node corresponding to the storage device is set. In step 1, after receiving the read instruction, the reception flag is set in the information so that the node that issued the read instruction does not receive the information stored in the storage device corresponding to the address, and the information corresponding to the address is set. When the reception means of each node corresponding to the plurality of processors and the storage device sends out the information stored in the cache memory and detects that the reception flag is set in the reception information, May not use the received information as the received information.

Further, one of the nodes is a master node that manages information transmitted on the transmission line,
When the master node receives the information, the master node adds the master node reception information indicating that the master node has received the information, and when the master node reception information is added, discards the information.

The master node generates a cell having a predetermined fixed length and sends it to the transmission line, and the transmitting means detects the cell on the transmission line and sends the information. When the cell is not in use, the address of the storage device for reading and writing, information indicating that the cell is in use, and transmission information are added to a predetermined position of the cell and transmitted. You can Alternatively, the master node generates a token for permitting transmission of a predetermined information and transmits it to the transmission path, and the transmission means, when transmitting the information, transmits the token on the transmission path. Information indicating the capacity of the information to be detected, acquired, and transmitted, the address of the storage device for reading and writing, and the transmission information are added and transmitted.

Furthermore, priorities are assigned to the plurality of processors in advance, and in each node corresponding to the plurality of processors, the management means holds the priorities, and the transmission means includes the storage device. The write request is sent with the address of the write request added, and the transfer processing means receives the received information to which the information indicating that the write request has been received is received from the time when the write request is sent by the transmission means. , If a write request is sent to the address from another node, the priority of the management means is referred to, and if the own node has a higher priority than the other node, the request is retransmitted from the other node. If the priority is low, a write request from another node to the address as a received information may be performed as write information. Kill.

Further, the plurality of processors are assigned priorities in advance, and in each node corresponding to the plurality of processors, the management means holds the priorities, and the transmission means holds the storage device. The address is added to send the write permission request, and the transfer processing means, when the sending means sends the write permission request,
If the write permission request is sent to the address from another node by the time the reception information added with the information indicating that the write permission request is received is received,
Referring to the priority of the management means, if the own node has a higher priority than other nodes, it is instructed that the write permission request is not permitted from the other node, and if the priority is low, another Writing may be permitted from the node to the address using the write permission request as reception information, and the transmission unit may add the address of the storage device and send the write request when the writing is permitted.

When the transfer processing means sends out the information stored in the cache memory corresponding to the address, the managing means erases the address managed by itself. As a result, the information corresponding to the address of the storage device can be granted to only one cache memory in the processor system.

[0016]

Since each node is connected to another node by a transmission line and configured in a ring shape, there is no limit to the number of processors, memory controllers, and I / O controllers to be accommodated. When the processor instructs an address to the storage device and reads the information of the address, the management unit stores the read information in a cache memory provided in the processor, and stores the information to be stored in the cache memory. Manage addresses.

In each of the nodes corresponding to the plurality of processors, when the information in the storage device is read and written, the sending means sends the information including the address of the storage device and the read / write instruction to the address. . The transmitted information is received by the receiving means of another node. The receiving means monitors the address added to the information, and when the address matches the address managed by the managing means, the information is used as the received information. When the received information is a read instruction, the transfer processing means reads the information stored in the cache memory corresponding to the address instead of the read information of the address from the node corresponding to the storage device. When the instruction is sent to the node that issued the instruction, and the received information is a write instruction, a process of writing the received information in the cache memory corresponding to the address is performed.

That is, the management means manages the address stored in the cache memory, and when the reception means reads / writes the same address as the address managed by the management means, the information stored in the cache memory. Is output. When the read information corresponding to the address is sent from the node connected to the storage device and the address is the same as the address managed by the managing means, this information is processed as the received information and the cache memory Output the information to be stored in.

By performing the processing as described above, if the number of packets circulating on the transmission line and the transmission speed of the transmission line are increased or decreased in accordance with the increase or decrease in the number of devices accommodated in the transmission line, the processor, memory, and The I / O throughput of the I / O device does not change much. Since the ring type system is easier to increase the transmission speed of the transmission line than the bus type system, it is possible to easily construct a system in which the I / O throughput does not depend on the number of processors, the memory capacity, and the number of I / O devices.

Further, since the broadcast transmission and the transmission between other devices are constantly monitored, it is possible to easily construct a multiplexing system including a memory and an I / O device.

Furthermore, since there is no limit to the number of memory controllers and I / O controllers that can be accommodated in the transmission path on the ring, memory controllers and I / Os with different address ranges can be used.
By connecting multiple controllers, it is possible to build a system with highly independent access to different addresses.
Further, since the physical scale of the system is not limited, it is possible to provide a scalable system. Furthermore,
Since it does not have a directory, communication for directory search does not occur.

[0022]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 shows a multiprocessor system to which the present invention is applied. In FIG. 1, the multiprocessor system according to the present embodiment includes a plurality of processors 11 and 12 each having a cache memory for storing information, and one or more storage devices to which an address space readable and writable by each of the plurality of processors is assigned. 16, 17, 18, 19
And nodes 1 to 9 provided corresponding to each of the plurality of processors and the storage device and controlling communication with other devices. Each node is connected to another node by a transmission line 10 in the short direction to form a ring. Nodes 1 and 2 have a cache control function,
The node 1 is connected to the processor 11 and the cache 13, and the node 2 is connected to the processor 12 and the cache 14.
Respectively connected to. Each node corresponding to the storage device monitors an address added to the information, and when the address matches the address assigned to the storage device, the reception means that receives the information and the reception means. If the received information is a read instruction based on the received information received in step 1, the information stored in the storage device corresponding to the address is sent to the node that issued the read instruction, and the received information is In the case of a write instruction, a transfer processing unit that writes the received information in the storage device corresponding to the address is provided, and each node corresponding to the plurality of processors has an address of the storage device and Sending means for sending information including a read instruction / write instruction to an address, and the processor instructing the address to send information corresponding to the address. When read by the read instruction of, the read information is stored in the cache memory provided in the processor, and the management means for managing the address of the information stored in the cache memory and the address added to the information are monitored. If the received information is a read instruction based on the receiving means that receives the information when the address matches the address managed by the managing means, and the receiving information received by the receiving means, Instead of the read information of the address from the node corresponding to the storage device, the information stored in the cache memory corresponding to the address is sent to the node that issued the read instruction, and the received information is the write instruction. In the case of, a transfer processing means for writing the received information in the cache memory corresponding to the address Provided. The node 3 has a function of controlling the entire system, and is connected to the monitoring device 15. Hereinafter, this node 3 will be referred to as a master node. One of the nodes is a master node that manages information transmitted on the transmission path. The master node has a function of adding, when receiving the information, master node reception information indicating that the information has been received by the master node, and discarding the information when the master node reception information is added. . Further, the nodes 4 to 7 have a memory control function of controlling the storage device and are connected to the memories 16 to 19, respectively. The nodes 8 and 9 have an I / O control function of controlling an input / output device (hereinafter, referred to as I / O). The node 8 is a LAN 21 via a LAN controller 20, and the node 9 is an I / O.
The disks 23 and 24 are connected via a bus 22, respectively.

A node ID for identifying the node is assigned to each node. This allocation may be fixed in advance, or may be appropriately instructed by the master node 3. Table 1 shows an example of node ID allocation.

[0025]

[Table 1]

As shown in Table 1, in this embodiment,
Nodes 1 to 9 in order of 10H, 11H, 01H, 20
Assign H, 21H, 22H, 23H, 31H and 30H. It can be assigned regardless of the transmission direction of the transmission path and also discontinuously. Although not shown in Table 1, multiple IDs may be assigned to one node.

Nodes 4 to 7 having a memory control function
Address ranges are assigned in advance to the storage devices controlled by the nodes 8 and 9 having the I / O control function.
(The system of this embodiment is a memory-mapped I / O system.) This allocation may be fixed in advance, or may be appropriately performed by the master node 3. Table 1 shows an example. As shown in Table 1, in the order of nodes 4 to 9,
00000000H to 00FFFFFFH, 01000
000H ~ 01FFFFFFH, 02000000H ~
027FFFFFH, 02800000H to 02FFF
FFFH, F0000000H to F0000FFFH and FE000000H to FE007FFFH, and F
0001000H ~ F0001FFFH and FE0000
00H to FE007FFFH are assigned. This address range can be assigned logically and discontinuously regardless of the physical memory capacity. Also, overlapping address ranges may be assigned as shown in nodes 8 and 9. This enables broadcast transfer to transfer information simultaneously to a plurality of addresses.

A cacheable address range is set for the nodes 1 and 2 having the cache control function. This setting may be fixed in advance, or may be appropriately set by the master node 3 or the processor 11 or 12.
Table 1 shows an example. 00000 for both nodes 1 and 2
000H to EFFFFFFFH was set. When the cache is a direct mapping, the cacheable address space is allocated to each node in consideration of the cache size, so that the system can be operated efficiently. Table 2 shows an example.

[0029]

[Table 2]

In Table 2, the cache size is 100
If 0H bytes, 00000000H and 0000
Although 1000H is duplicated in the entry of the cache, the cache can be efficiently replaced by allocating these two addresses to different nodes. (As shown in Table 2, when one line of the cache is 10 H bytes, an exclusive OR of 2 12 bits and 2 4 5 bits may be calculated. For example, node 4
Assigns the address of which the exclusive OR of the 2 12th bit of the address and the 4th and 5th bits is 00B. ) A predetermined frame is used for exchanging data between nodes. The frame is first generated by the master node, and each node (including the master node) relays it to circulate in the system. Therefore, in order to effectively utilize the transmission path, it is desirable that the transmission distance around the system is the frame length or an integral multiple thereof, and the master node guarantees it. FIG. 2 shows an example of a frame. As shown in FIG. 2, the frame is composed of a predetermined frame synchronization pattern and one or more cells. The frame sync pattern is
This is a pattern for each node to recognize the beginning of the frame. In this embodiment, it is set to F6F62828H in accordance with the CCITT SDH standard. A cell is a fixed-length container that carries information. The structure is shown in FIG. In FIG. 3, one cell is made up of 24 bytes,
Busy flag, type, receive flag, retry flag,
It consists of a monitor flag, a transmission ID, a reception ID, auxiliary information, an address and data. Table 3 shows the meaning of each area.

[0031]

[Table 3]

In the case of this embodiment, each node is functionally
Master node 3, nodes 1 and 2 that are connected to the cache and are not assigned an address space, nodes 4 to 7 that are not connected to the cache and are assigned a cacheable address space, and are connected to the cache It can be classified into nodes 8 and 9 to which uncacheable address space is allocated. Further, FIG. 27 shows a conceptual diagram of processing in the node. Figure 2
As shown in FIG. 7, each node, at the time of transmission, sends the information by adding the destination information and the address of the storage device to read and write, and at the time of reception, when the destination information is addressed to itself, the information concerned. And a transfer processing unit that adds information indicating that the received information has been received, sends the received information, and performs a corresponding transfer process based on the received information. Each node 2 or 3 corresponding to the processor stores the read information in the cache memory provided in the processor when the processor instructs the memory device to read the information at the address. Management means for managing the address of the information stored in the cache memory is provided. This management means may be provided in the transfer processing means. Receiving means of each node corresponding to the processor monitors the address added to the transmitted information when the information indicating reception is not added to the transmitted information, and the address is When the address matches the address managed by the managing means, the information is used as received information, and the transfer processing means of each node 2 or 3 corresponding to the plurality of processors has the same address at the receiving means. In this case, the received information is added with information indicating that it has been received, and the received information is sent out. When the received information is read out, it is stored in the cache memory corresponding to the address as a transfer process. If the received information is written, the received information is written in the cache memory. The transfer processing means of each node differs in processing depending on the processor, I / O, memory, or the like connected to the node. Node 4 to which the memory connects,
As the transfer processing of 5, 6, and 7, a memory control function is provided to control the access to the memory corresponding to the address space. Also, nodes 8 and 9 connected to the input / output device
Has an I / O control function to control the input / output of the input / output device.

Next, detailed block diagrams of each node are shown in FIGS. 4, 5, 6 and 7. FIG. 4 shows a block diagram of the master node 3, FIG. 5 shows a block diagram of the nodes 1 and 2, FIG. 6 shows a block diagram of the nodes 4 to 7, and FIG. 7 shows a block diagram of the nodes 8 and 9. Node 4-
7 does not actively read / write. In this embodiment, the address space is assigned to the nodes 1 and 2,
Connect a cache to nodes 4-9 or nodes 4-7
Does not prevent active read / write.

The operation will be described with reference to the above block diagram. The master node generates a cell having a predetermined fixed length and sends it to the transmission line, and the transmitting means detects the cell on the transmission line, and when the information is sent, the cell is used by the cell. If not, the destination information, the address of the storage device for reading and writing, the information indicating that the cell is in use, and the transmission information are added to a predetermined position of the cell and transmitted. In FIG. 4, first, the master node 3 generates an initial frame with a transmission clock of its own node clock. In addition, frame synchronization patterns are generated at predetermined intervals. All the remaining cells are set to 0. The interval of the frame synchronization pattern is called the frame length. It is fixed in advance to the frame synchronization pattern length (4 bytes) + {integer multiple of 1 cell length (24 bytes)}. Then, the initial frame is scrambled 44 in the cell portion and transmitted to the next node 4. Scramble has two effects. The effect of facilitating the extraction of the clock component from the signal on the transmission line by the next node and the ratio of 0 and 1 of the data on the transmission line are made almost the same, and the fluctuation of the voltage due to the change of the data and the transmission line The effect is to reduce crosstalk. In particular, the latter
It is effective in a device with a low voltage power supply. The structure of the scramble circuit is shown in FIG. It can comply with the SDIT standard of CCITT. As shown in FIG. 8, the scramble circuit includes an n-stage linear feedback shift register (7 stages in FIG. 8) for a random pattern generation circuit of a maximum long-period sequence and an exclusive OR of the random pattern and data. And output means for outputting the scrambled scrambled data. The scramble circuit is initialized at the beginning of the frame and starts scrambling from the beginning cell after the frame synchronization pattern. The descrambling circuit is also constructed in the same manner. At the node 4 shown in FIG. 6, a clock component is extracted from the signal on the transmission path and multiplied by a PLL to obtain an operation clock. This is called a reception clock. Nodes other than the master node use the reception clock as the node clock. Next, frame synchronization is established. The state transition of frame synchronization establishment is shown in FIG. The first frame synchronization pattern detected from the initial state is the first frame synchronization pattern, the next detected frame synchronization pattern is the second frame synchronization pattern, and the length between the first frame synchronization pattern and the second frame synchronization pattern is the frame length. To do. Whether or not the frame synchronization pattern is detected for each frame length from the second frame synchronization pattern is monitored. Frame synchronization is established when the frame synchronization pattern is detected five times in a row. If not, it returns to the initial state. After frame synchronization is established, it is monitored for each frame length whether or not a frame synchronization pattern is detected. If the frame synchronization pattern is not detected five times in a row, the frame is out of synchronization and the initial state is restored. During frame synchronization establishment, processing is performed assuming that a frame is received at each frame length cycle regardless of whether or not a frame synchronization pattern is detected. Next, descrambling is performed to restore the data before the scramble by the master node 3. Then, it is scrambled again and transmitted to the next node 5. At the timing of transmitting the frame synchronization pattern, the pattern is generated and overwritten. Until the frame goes around
The cell cannot be processed. Other nodes 6-9, 1 and 2
Can similarly relay the frame. In FIG. 4, the frame returned to the master node 3 is
Similarly, clock extraction, frame synchronization establishment and descrambling are performed, and the results are stored in the round delay guarantee buffer.
The loop delay guarantee buffer has two functions. There is a function of holding the transmission distance that goes around the system at an integral multiple of the frame length, and a function of transferring data from the reception clock extracted from the signal on the transmission path to the node clock by the master node. The cyclic delay guarantee buffer shown in FIG. 10 has a FIFO (First in
First out). The master node starts writing the frame in which the frame synchronization is first established from the head address, and when the write pointer is within the read startable range, the read is started from the head in accordance with the timing of frame generation. The read startable range is a range of a little over one frame centered on the center of the FIFO. Thereafter, writing and reading are continuously continued until the frame synchronization is lost. As described above, the frame circulates in the system. Only when the frame goes around, each node can use the cell to exchange information. As described above, the cell processing of each node is provided with the transmitting means, the receiving means, and the transfer processing means for performing the transfer processing determined for each node. Details will be described later.

Further, the clock may be transmitted between the nodes by another line or may be distributed to each node. In this case, scrambling and descrambling are not essential, there is no need to mix digital circuits and analog circuits in one LSI, and the logic becomes simple. Further, a signal indicating a frame or a cell delimiter may be exchanged between the nodes on another line.
The frame synchronization pattern and the procedure for establishing frame synchronization are not necessary, and the logic is simple. Next, the function of the master node will be described. The master node firstly assigns a node ID or address range to each node as described above. Second, it generates the clock for the entire system. However, this applies only to the clock of the part that transmits the frame. For example, processors 11 and 12 may operate on different clocks. In this case, the send request buffer,
The reception request buffer and the response buffer also have the function of changing the clock. Thirdly, a frame is generated according to a predetermined frame length. The format of this frame allows the performance of the system to be easily adjusted. Generally, when the number of cells in one frame is small, the latency is good but the throughput is sacrificed. Conversely, when the number of cells is large, the throughput is good but the latency is sacrificed. Alternatively, a dedicated cell may be fixedly assigned to each node. For this, for example, the transmission ID part and the reception ID part may be fixed or may be assigned according to the position from the beginning of the frame.

A frame format such as the token passing system of LAN may be selected. Of course, when cells are fixedly assigned or a frame format such as the token passing method is selected, it is necessary to change the algorithms shown in FIGS. 23 to 26 and 28 to 30 according to the protocol. is there. In any case, the system to which this embodiment is applied can have various characteristics by changing the frame format according to its configuration. Fourth, it guarantees the round-trip delay of the frame.
Fifth, monitor the cell. First, the monitor flags of all cells that pass the mast node and have a busy flag = 1 (hereinafter referred to as busy cells) are set to 1. Normally, a busy cell is returned to an empty cell at the node that made it a busy cell after going around the system. Therefore, when the master node receives a busy cell with the monitor flag = 1, it can be seen that it is an abnormally circling cell. It also monitors access to address ranges that are not actually allocated. Furthermore, parity may be added to each byte, or a check sequence may be added to a cell or frame to monitor it. Sixth,
Other functions include collecting and logging error information, checking memory mounting status, and performance evaluation.

Next, cell processing will be described using a specific example. 23 and 24 show the operation algorithms of the cell processing of the nodes 1 and 2, FIGS. 25 and 26 show the operation algorithms of the cell processing of the nodes 4 to 7, and FIG.
The operation algorithms of the cell processing of Nos. 9 and 9 are shown in the flow charts of FIGS. However, error processing is omitted.

First, in the state where the node ID and the range of addresses as shown in Table 1 are allocated, when nothing is entered in the caches 13 and 14, the processor 11 in the node 1 addresses the memory 16. 1 and FIG. 1 for the processing when a read request is sent to the node 4 when accessing “00000000H” and a response is sent at the node 4.
2, with reference to FIGS. 13 and 14. In this case, the node 1 has the address “000000” in the memory 16.
16 bytes from "00H" are read, and the processor 11
To the cache 13 and return it to the cache 13. First, in the transmission request buffer of the node 1 shown in FIG. 4, a read transmission request indicating that “a request to read 16-byte data from the address“ 00000000H ”is requested” is stored. According to the algorithms shown in FIG. 23 and FIG. 24, the transmission means of the node 1 determines whether the busy flag is 0 or 1 (S231), and when the busy flag = 0 cell (hereinafter referred to as an empty cell) is received, the response request is issued. It is determined whether or not there is a read request (S232), and it is determined whether or not there is a read request (S234). If a read transmission request is stored, transmission processing is performed with a request (S235 to 237), and busy flag = 1. In addition, the cell type is changed to 00 (hereinafter referred to as a read cell), the transmission source ID is set to 10H of its own node ID,
Set the memory address to read and send. The bit pattern of the cell in that case is shown in FIG. This cell is
It arrives at node 4 through nodes 2 and 3. In the node 2, if the busy flag of the cell is 1 (S
231), the cell type is determined (S240), and the transmission ID
Is the self node ID (S241), and it is determined whether the target memory address is entered in the cache memory connected to the node (S246). In this case, since the transmission ID is not the node ID of itself and is not entered in the cache memory, the cell is passed as it is (S282). In the node 3, when the busy flag of the cell is 1, the monitor flag is set and the cell is transmitted. In the node 4, when the busy flag of the cell is 1 (S290), the receiving unit determines the cell type (S293) according to the algorithm shown in FIGS. 24 and 25, and determines whether the target memory address is the assigned address. It is determined whether or not (S294). When the target memory address is the allocated address, the cell is used as reception information, the cell request is recognized to be addressed to the own node, and the read reception request is stored in the reception request buffer (S302). Transfer processing is performed (S2
95-S303). As a result, as shown in FIG.
The cell is transmitted with the reception flag = 1. This cell then passes through nodes 5 to 9 and arrives at node 1.

When the node 1 recognizes that the read cell transmitted by itself is normally accepted according to the algorithm shown in FIGS. 23 and 24 (S231, S2).
40 and S241), the read transmission request in the transmission request buffer is released (S242, S243 and S244), the busy flag = 0 is set, and the cell is changed to an empty cell (S245). In the node 4, the read reception request stored in the reception request buffer is processed by the transfer processing means, and as a result, “address“ 0000000 ”is stored in the transmission request buffer of the node 4.
0H ”(as shown in FIG. 13, 00122233
44556677788899AABBCCDDEEFH
Response request is stored to the node ID = 10H ”. When the node 4 receives an empty cell (S290) according to the algorithm shown in FIGS. 25 and 26, it determines whether or not there is a response request (S291), and if the transmission request is stored, the request is transmitted. Perform processing (S29
2) Change to a cell with busy flag = 1 and type = 10 (hereinafter referred to as response cell), set the transmission source ID to 20H of its own node ID, set the reception ID to 10H, and set the memory address and data to read. Send. The bit pattern of the cell in that case is shown in FIG. This cell reaches node 1 through nodes 5-9. The nodes 5 to 9 send the cell after performing the same processing as the processing in the node 2 described above. According to the algorithm shown in FIGS. 23 and 24, the node 1 recognizes that the cell is addressed to its own node by the receiving means (S23).
1, S240, S266 and S274), transfer processing is performed (S275, S276 and S278), the response result is stored in the response buffer (S277), and the cell is passed. In this case, as shown in FIG. 14, the reception flag = 1 is transmitted. Further, an entry is made in the cache memory (S279), and the entry address is registered in the management means. Then, this transmission cell passes through the nodes 2 and 3 and arrives at the node 4 as described above. The node 4 releases the response transmission request in the transmission request buffer according to the algorithm shown in FIGS. 25 and 26 (S290, S293, S31).
3, S314, S315 and S316), the cell is changed to an empty cell (S317). Since the response result stored in the response buffer of the node 1 is in the cacheable space, the response result is returned to the processor 11, entered in the cache 13, and released from the response buffer. If the reception request buffer is full when the cell shown in FIG. 11 arrives at the node 4 (S301), the node 4 sets the reception flag = 1 and the retry flag = 1 at the same time (S303). When the node 1 recognizes that the read cell transmitted by itself is not normally accepted according to the algorithms shown in FIGS. 23 and 24 (S243), it does not release the read transmission request in the transmission request buffer (S2
44), the cell is changed to an empty cell (S245), transmitted to the next node, and waits for a new empty cell to be received. When the once-acquired cell is continuously used until the cell is normally accepted, the dotted line portions shown in FIGS. 23 and 24 may be processed as shown in FIG. However, note that this may cause a deadlock depending on the system.

By the above processing, the processor 11 designates an address, reads the information stored in the memory 16, and stores it in the cache memory.

Next, the case where the processor 12 accesses the same address "00000000H" is shown in FIG.
~ It demonstrates with reference to FIG. In the system of this embodiment, the data stored in the cache memory is always kept up to date and treated preferentially. In this case, address 00 of memory 16
Instead of the data transfer stored in 000000H, the node 1 detects that the access is to the address and stores 000000 in the cache 13.
The 16 bytes from 00H are returned to the processor 12 and entered in the cache 14, and the cache 13
Erase from the entry.

First, a read transmission request "requesting reading of 16-byte data from address" 00000000H "" is stored in the transmission request buffer of node 2. According to the algorithm shown in FIGS. 23 and 24, the node 2 determines whether the busy flag is 0 or 1 (S231), and when an empty cell is received, it determines whether there is a response request (S232) and there is a read request. It is determined whether or not there is (S234). If the read transmission request is stored, the transmission process is performed with a request (S235 to S237), the cell is changed to a cell with busy flag = 1 and type = 00 (hereinafter referred to as a read cell), and the transmission source ID is the own node ID. 11H, set the memory address to be read, and transmit. The bit pattern of the cell in that case is shown in FIG. This cell is node 3
And arrives at node 4. In the node 3, when the busy flag of the cell is 1, the monitor flag is set and the cell is transmitted. Node 4 is shown in FIG. 25 and FIG.
According to the algorithm shown in FIG. 6, when the busy flag of the cell is 1 (S290), the receiving unit determines the cell type (S293) and determines whether the target memory address is the assigned address (S294). When the target memory address is the allocated address, the cell is used as reception information, the cell request is recognized to be addressed to the own node, and the read reception request is stored in the reception request buffer (S302). Transfer processing is performed (S295 to S303). As a result, the cell is transmitted with the reception flag = 1 as shown in FIG. Then, this cell similarly passes through nodes 5 to 9 and node 1 and reaches node 2. The node 2 is shown in FIG. 23 and FIG.
According to the algorithm shown in FIG. 4, when the read cell transmitted by itself is recognized to be normally accepted (S23
1, S240 and S241) and releases the read transmission request in the transmission request buffer (S242, S2).
43 and S244), the busy flag is set to 0 and the cell is changed to an empty cell (S245). Further, in the node 4, the read reception request stored in the reception request buffer is processed by the transfer processing means, and as a result, the contents of the “address“ 00000000H ”(as shown in FIG. 17) are stored in the transmission request buffer of the node 4. ,
001122334445667778899AABCC
CDDEEFFH) is sent to the node ID = 11H ”. When the node 4 receives an empty cell (S290) according to the algorithm shown in FIGS. 25 and 26, it determines whether or not there is a response request (S291), and if the transmission request is stored, the request is transmitted. Processing is performed (S292), the response cell is changed to a busy flag = 1 and type = 10, the transmission source ID is set to 20H of its own node ID, the reception ID is set to 11H, and the memory address and data to be read are set and transmitted. The bit pattern of the cell in that case is shown in FIG. This cell is
It arrives at node 1 through nodes 5-9. Node 1
In the receiving means, when the busy flag of the cell is 1 (S231), the cell type is determined (S240) according to the algorithm shown in FIGS. 23 and 24, and it is determined whether the transmission ID is the own node ID. (S241), it is determined whether the target memory address is entered in the cache memory connected to the node (S246).
In this case, the transmission ID is not the own node ID, but the target address is entered in the cache memory, so the cell is transferred as reception information (S247-).
S252). Thereby, as shown in FIG. 18, the reception flag = 1. This cell arrives at node 2, but at node 2, if the busy flag of the cell is 1 according to the algorithm shown in FIGS. 23 and 24 (S23).
1), the cell type is determined (S240), it is determined whether the transmission ID is the own node ID (S266), and it is determined whether the reception ID is the own node (S274). In this case, it is determined that the reception ID is the own node ID, but since the reception flag is 1 (S275), the cell is passed. This cell then passes through node 3 and arrives at node 4. The node 4 releases the response transmission request in the transmission request buffer according to the algorithm shown in FIGS. 25 and 26 (S290, S29).
3, S313, S314, S315 and S316),
The cell is changed to an empty cell (S317). On the other hand, in the node 1, the read reception request stored in the reception request buffer is transferred and stored in the transmission request buffer of the node 1 “contents of address 00000000H (01234456789ABCDEF8899AA.
BBCCDDEEFH) as the node ID = 11H
A request to send the response is stored. In the transmission means, the node 1 determines whether the busy flag is 0 or 1 (S231), and when a cell with a busy flag = 0 (hereinafter referred to as an empty cell) is received, it is determined whether or not there is a response request (S232). . If the transmission request is stored, the transmission processing is performed as a request (S233), and the busy flag = 1 and the type =
10 cells (hereinafter referred to as response cells), the transmission source ID is set to 10H of the own node ID, and the reception ID is set to 11
It is set to H, and the memory address and data to be read are set and transmitted. The bit pattern of the cell in that case is shown in FIG. This cell then arrives at node 2. In the node 2, according to the algorithm shown in FIGS. 23 and 24, the receiving means recognizes that the cell is addressed to its own node (S231, S240, S266 and S2).
74) and transfer processing is performed (S275, S276 and S
278), the response result is stored in the response buffer (S277), and the cell is passed. In this case, FIG.
As shown in, the transmission is performed with the reception flag = 1. Also,
An entry is made in the cache memory (S279), and the entry address is registered in the management means. Then, the transmitted cell passes through the nodes 3 to 9 and arrives at the node 1. The node 1 releases the response transmission request in the transmission request buffer according to the algorithm shown in FIGS. 23 and 24 (S290, S293, S3).
13, S314, S315 and S316), the cell is changed to an empty cell (S317). Furthermore, in node 1,
The management means deletes the cache entry.
Since the response result stored in the response buffer in the node 2 is in the cacheable space, it is returned to the processor 12 and entered in the cache 14 and released from the response buffer. Node 4
The case where the node 1 returns before that can be processed according to FIG.

As described above, in the node where the address of the data stored in the cache memory is detected,
The data in the cache memory can be transmitted. Further, when the data is sent from the memory that stores the data of the address, the address can be detected, the node can perform the receiving process, and the data of the cache memory can be sent.

In the case of a write request, an address is added from a node connected to the processor which issued the write request, and a write request cell is sent out, and the memory is assigned to the address and the cache memory. Write processing is performed in each node.

For example, the address "00" is stored in the cache 13.
"000000H" data is stored in the node 8
However, the case where data is written to the same address "00000000H" will be described.

First, a write transmission request "requesting writing of 16-byte data from address" 00000000H "is stored in the transmission request buffer of the node 8. According to the algorithm shown in FIG. 28 and FIG. 29, the node 8 judges whether the busy flag is 0 or 1 (S330), and when receiving the empty cell, judges whether there is a response request (S331) and makes a read request. Whether or not there is a write request is determined (S333), and whether or not there is a write request is determined (S337). If a write transmission request is stored, transmission processing is performed with a request (S338), the cell is changed to a cell with busy flag = 1 and type = 01 (hereinafter referred to as write cell), and the transmission source ID is set to the node ID It is set to 31H, the write address is set, and the data is transmitted. This cell passes through node 9 and node 1
Arrive at. In node 1, as shown in FIGS. 23 and 24, when the target memory address is entered (S231, S240, S254 and S2).
60), process the received information (S261 to S265 and S282), and update the data corresponding to the address. This cell then passes through nodes 2 and 3 and arrives at node 4. In the node 4, when the busy flag of the cell is 1 (S290), the receiving unit determines the cell type (S293) according to the algorithm shown in FIGS. 25 and 26, and if the target memory address is the assigned address. It is determined whether or not (S304). When the target memory address is the assigned address, the cell is used as the reception information, and it is recognized that the request for the cell is addressed to the own node, and the write reception request is stored in the reception request buffer (S312). Transfer processing is performed (S305 to S311), and the cell is transmitted to the next node (S323). After storing the write reception request in the reception request buffer, the content of the corresponding address in the memory is updated. Receive flag = 1 due to transfer processing
To send the cell as.

The write processing can be performed by the above processing. Further, when one processor writes to an address of a memory, if another processor having a cache memory that stores data corresponding to the address updates the contents of the cache memory, the other processor and The processing may be coordinated with one processor. This can be dealt with by synchronizing the processors and determining the processing order.

Next, the processor 11 sends the address "FE
The data "0000111112222" in "000000H"
The case of writing "333344445555566666777H" will be described with reference to FIGS. The address "FE000000H" is an address assigned in the nodes 8 and 9 that do not have a cache memory, and in this case, it is a broadcast communication.

First, in the node 1, in the transmission request buffer, "from address" FE000000H "to 16
Byte data “000011112222233334
"44545556666667777H" request for writing "write transmission request" is stored. According to the algorithms shown in FIGS. 23 and 24, the transmission means of the node 1 determines whether the busy flag is 0 or 1 (S23
1) When receiving an empty cell with a busy flag = 0, it is determined whether there is a response request (S232), whether there is a read request (S234), and whether there is a write request (S238). ), If a write transmission request is stored, it is determined that there is a write request and transmission processing is performed (S239). Change to a cell with busy flag = 1 and type = 01 (hereinafter called a write cell),
The transmission source ID is set to 10H of its own node ID, the memory address to be written is set, and transmission is performed. The bit pattern of the cell in that case is shown in FIG. This cell is node 2-7
And arrives at node 8. According to the algorithm shown in FIGS. 28 and 29, the node 8 determines the cell type when the receiving means has the busy flag of the cell being 1 (S330) (S339). When the cell type is a write request, it is determined whether or not the transmission ID is the own node, and when it is not the own node, it is determined whether the target memory address is the assigned address (S356). If the desired memory address is an assigned address,
Using the cell as the reception information, it recognizes that the request of the cell is addressed to its own node, and stores the write reception request in the reception request buffer (S359). At the same time, transfer processing is performed (S357, S358, S36).
0). As a result, as shown in FIG. 22, the reception flag =
The cell is transmitted to the node 9 as 1. According to the algorithm shown in FIGS. 28 and 29, the node 9 also detects that the request of the cell is the address assigned to its own node, stores the read reception request in the reception request buffer, and the reception flag = 1 is overwritten and sent to node 1. When the node 1 recognizes that the light cell transmitted by itself is normally accepted according to the algorithm shown in FIGS. 23 and 24 (S231, S240, S254, S255, S25).
6) The write transmission request in the transmission request buffer is released (S257), and the cell is changed to an empty cell (S258).

On the other hand, in the nodes 8 and 9, the write reception request stored in the reception request buffer is processed, and as a result, 16-byte data "000011111222223333434445" is stored in the portion corresponding to the address "FE000000H" in each node.
55556666777H "is written.

As described above, the system to which this embodiment is applied can perform broadcast transfer in a node that does not have a cache memory. In addition, it is easy to peep at the exchange of information between other processors and I / O controllers. This indicates that it is easy to build a highly reliable system that is multiplexed (dual, duplex).

In the above embodiments, the data corresponding to the address of the cache memory (hereinafter referred to as the cache line) is permitted only to one cache memory in the system. Next, as a second embodiment, a case will be described in which a plurality of cache memories in the system are allowed to hold data of the same address. In this case, it is necessary to guarantee that the data of the same address held in all the cache memories have the same content. Two types of this match guarantee will be described below: a "soft match guarantee" that allows a mismatch period to some extent and a "strict match guarantee" that does not guarantee a mismatch period at all. In this case, with respect to writing to the same address, non-overlapping priorities are assigned to the processor, the I / O controller, etc. in advance, and each node holds the priorities.

First, an example of the "loose match guarantee" algorithm will be described.

(1) When changing the cache line in the cache memory connected to its own processor, each processor issues a write request corresponding to the address corresponding to the cache line. The node connected to the processor sends a write request cell in response to the write request.

(2) After that, if a write request for the same address is received from another node before the transmission cell passes through the transmission line and each node and returns to its own node, the request source And the priority of the self node are compared.

When the own node has a high priority, the retry flag of the write request is set in the cell of the write request to the same address from another node.

When the priority of the own node is low, the write process is performed according to the write request with the cell of the write request from the other node for the same address as the reception information.

(3) If the retry flag is not set when the cell transmitted in (1) above passes through the transmission line and each node and returns to the own node, the cache memory connected to the node. Change the desired cache line in.

When the retry flag is set,
The above process (1) is repeated for the same address.

(4) Other nodes that have not issued the write request check the retry flag of the received write request.

If the retry flag is not set, the process is performed according to the write request.

When the retry flag is set,
Do not follow the write request.

By thus sending the write request, the node connected to the storage device holding the data of the same address receives and performs the write processing. In this case, when the write requests overlap, the processing is performed according to the priority order.

Next, an example of the algorithm of "strict match guarantee" is shown below.

(1) When changing the cache line in the cache memory connected to its own processor, each processor says, "It is different because the address corresponding to the cache line has been written, so please allow it." A permission request indicating that is issued. The node connected to the processor sends a permission request cell in response to the permission request.

(2) After that, before the permission request cell passes through the transmission line and each node and returns to the own node,
When a write permission request for the same address is received from another node, the priority order of the request is compared with the own node priority order.

When the own node has a high priority, the information indicating "not permitted" is written in the cell of the write permission request for the same address from another node.

When the priority of the own node is low, the cell of the write permission request for the same address from another node is relayed as it is.

(3) When the permission request cell transmitted in (1) above passes through the transmission line and each node and returns to the own node, when the information indicating “not permitted” is not written Issues a write request to the address. A write request is received at another node,
The retry flag is not set (write processing is performed normally), and the write request is continuously issued until it returns.

When the permission request cell for the same address is received by the time the write request goes around and returns to the own node after the permission request cell is received, the permission request cell is received regardless of the priority order. And write information indicating "not allowed".

If the information indicating "not permitted" is written, after the write request for the same address is received, the process is repeated from (1). (However, the observation of the write request is started from the time when the write permission request is issued.) (4) The other nodes also perform the processes shown in (1) to (3) above.

In this way, when the permission request is transmitted and when the permission is permitted, by transmitting the write request, the node connected to the storage device holding the data of the same address receives and performs the write processing. In this case, when the write permission requests overlap, processing is performed according to the priority order.

By processing as described above, it is possible to permit the data of the same address to be held in a plurality of cache memories in the system, and the contents of the data of the same address held in all the cache memories match. Can be guaranteed to.

Although the above description has been given based on the configuration shown in FIG. 1, the physical configuration is not an essential item for this embodiment. For example, all the nodes may be arranged on one package or realized by one LSI. In this case, it is possible to more flexibly select a method such as clock generation, distribution, and transmission of frame delimiters. Also,
The transmission line may be made of any material, band, multiplicity, etc.

As described above, since the number of processors, memory controllers and I / O controllers accommodated in the transmission path on the ring is not limited, access to different addresses is highly independent. Further, the performance of the system can be easily adjusted depending on the number of packets circulating on the transmission path and the reservation method thereof. Further, since it is easy to monitor the transmission between other devices and to perform the broadcast transmission, it is easy to construct the multiplexing system. Furthermore, since the physical scale of the system is not limited, it is possible to construct a scalable system that does not depend on the transmission distance or the size of the device to be housed. In addition, since the directory is not used, the ring transmission capacity can be effectively used.

[0076]

According to the present invention, in the processor system, the number of devices such as processors is not limited, and the consistency of data in the cache memory can be guaranteed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a ring LAN system according to the present invention.

FIG. 2 is a frame format in the system shown in FIG.

FIG. 3 is a cell format in the system shown in FIG.

4 is a block diagram of a node 3 of the system shown in FIG.

5 is a block diagram of nodes 1 and 2 of the system shown in FIG. 1. FIG.

6 is a block diagram of nodes 4-7 of the system shown in FIG. 1. FIG.

7 is a block diagram of nodes 8 and 9 of the system shown in FIG.

FIG. 8 is a configuration diagram of a scramble circuit in the system shown in FIG.

9 is a state transition diagram of frame synchronization in the system shown in FIG.

10 is an explanatory diagram of a loop delay guarantee buffer in the system shown in FIG.

11 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

FIG. 12 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1.

FIG. 13 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1.

14 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

15 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

16 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

17 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

FIG. 18 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1.

19 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

20 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

21 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

22 is an explanatory diagram showing an example of cell data in the system shown in FIG. 1. FIG.

23 is a flowchart (1) of cell processing in nodes 1 and 2 of the system shown in FIG.

24 is a flowchart (2) of cell processing in the nodes 1 and 2 of the system shown in FIG.

25 is a flowchart (1) of cell processing in nodes 4 to 7 of the system shown in FIG.

FIG. 26 is a flowchart (2) of cell processing in nodes 4 to 7 of the system shown in FIG.

FIG. 27 is a configuration diagram of each node.

28 is a flowchart (1) of cell processing in the nodes 8 and 9 of the system shown in FIG.

29 is a flowchart (2) of the cell processing in the nodes 8 and 9 of the system shown in FIG.

FIG. 30 is a flow chart showing a modification example in the case of attempting to make cells continuous in the system shown in FIG. 1.

[Explanation of Codes] 1-9 ... Nodes. 11, 12 ... Nodes. 13, 14 ... Cache. 15 ... Monitoring device. 16 to 19 ... Memory. 20
... LAN controller. 21 ... LAN. 22 ... I / O bus. 23-24 ... Disc.

Claims (9)

[Claims] 1. A plurality of processors each including a cache memory for storing information, one or more storage devices to which an address space readable and writable by each of the plurality of processors is allocated, the plurality of processors and the storage device. And a node provided corresponding to each of the nodes, each node is connected to another node in a ring shape by a transmission line, and each node corresponding to the storage device is added to information. The received information is monitored based on the received information received by the receiving means that monitors the received address and the received information when the address matches the address assigned to the storage device. In the case of, the information stored in the storage device corresponding to the address is addressed to the node that issued the read instruction. And a transfer processing unit that performs a process of writing the received information to the storage device corresponding to the address when the received information is a write instruction, and each node corresponding to the plurality of processors is Sending means for sending information including an address of the storage device and a read instruction / write instruction to the address, and when the processor instructs the address and reads the information corresponding to the address by a read instruction, The read information is stored in the cache memory provided in the processor, the management means for managing the address of the information stored in the cache memory, and the address added to the information are monitored, and the address is managed by the management means. A receiving unit that uses the received information as the received information when it matches the address, and the received information received by the receiving unit. Then, when the received information is a read instruction, instead of the read information of the address from the node corresponding to the storage device,
When the information stored in the cache memory corresponding to the address is sent to the node that issued the read instruction and the received information is a write instruction, the received information is stored in the cache memory corresponding to the address. And a transfer processing unit that performs a writing process. 2. The transfer processing means of each node corresponding to each of the plurality of processors according to claim 1, wherein the transfer information corresponding to the address is used instead of the read information of the address from the node corresponding to the storage device. When transmitting the information stored in the cache memory to the node that issued the read instruction, when the node corresponding to the storage device receives the read instruction before receiving the read instruction, The information stored in the cache memory corresponding to the address is transmitted, a reception flag is set in the information so that the node corresponding to the storage device does not receive the read instruction, and the node corresponding to the storage device After receiving the read instruction, the information stored in the storage device corresponding to the address is Is set to information reception flag so that the node has issued only issued instruction is not received,
The information stored in the cache memory corresponding to the address is transmitted, and the reception means of each node corresponding to the plurality of processors and the storage device has the reception flag set in the reception information. The processor system characterized in that, when the above is detected, the received information is not regarded as the received information. 3. The information processing system according to claim 1, wherein one of the nodes is a master node that manages information transmitted on the transmission path, and the master node receives the information when it receives the information. A processor system characterized by adding master node reception information indicating that the master node reception information has been received, and discarding the information when the master node reception information is added. 4. The master node according to claim 3,
When a cell having a predetermined fixed length is generated and transmitted to the transmission line, the transmitting unit detects the cell on the transmission line and transmits the information, when the cell is not used In addition, the processor system is characterized in that the address of the memory device for reading and writing, information indicating that the cell is in use, and transmission information are added to a predetermined position of the cell and transmitted. 5. The master node according to claim 3,
A token for permitting the transmission of a predetermined information is generated and transmitted to the transmission line, and when transmitting the information, the transmitting unit detects and acquires the token on the transmission line and transmits the token. A processor system, wherein information indicating a capacity of information to be stored, an address of the storage device to be read and written, and transmission information are added and transmitted. 6. The priority order is assigned to the plurality of processors in advance, and in each node corresponding to the plurality of processors, the management unit holds the priority order and the transmission unit. Is a write request sent by adding the address of the storage device, and the transfer processing means has received information added with information indicating that the write request has been received since the write request was sent by the sending means. If a write request is sent from the other node to the address before receiving, the priority of the management means is referred to, and if the own node has a higher priority than the other node, another A node instructs to retransmit the request, and if the priority is low, a write request from another node to the address as a received information is written. Processor system, which comprises carrying out. 7. The processor according to claim 1, wherein priorities are assigned to the plurality of processors in advance, and in each node corresponding to the plurality of processors, the management unit holds the priorities and the transmission unit. Sends a write permission request by adding the address of the storage device, and the transfer processing unit adds information indicating that the write permission request has been received since the transmission unit sent the write permission request. If a write permission request is sent from the other node to the address before receiving the received information, the priority of the management means is referred to, and if the own node has a higher priority than other nodes, Indicates that the write permission request is not permitted from another node, and when the priority is low, the write permission is permitted from another node to the address. A processor system, wherein a permission request is permitted as a reception information to permit writing, and the transmission unit transmits the writing request by adding the address of the storage device when the writing is permitted. 8. The management means according to claim 1, wherein when the information stored in the cache memory corresponding to the address is transmitted by the transfer processing means of the management means, the management means determines the address managed by itself. A processor system characterized by erasing. 9. A plurality of processors each having a cache memory for storing information, one or more storage devices to which an address space readable and writable by each of the plurality of processors is allocated, and the plurality of processors and the storage device. In a processor system having nodes for controlling communication between the processor and the storage device, each of the nodes being connected to another node in a ring shape by a transmission line, When reading information stored in the storage device, each node corresponding to a plurality of processors sends an address of the storage device and a read instruction to the address to the transmission line, Each corresponding node receives a read instruction to the address assigned to the storage device. , The information stored in the storage device corresponding to the address is transmitted to the transmission path, and each node corresponding to the plurality of processors has a cache in which the information read from the storage device is provided in the processor. In addition to storing the information in the memory and holding the address of the information in the storage device, when another node sends a read instruction for the address, instead of the read information of the address from the node corresponding to the storage device. A processor system, wherein the information stored in the cache memory corresponding to the address is transmitted to the node that has issued the read instruction.