JPH06310729A - Semiconductor device having mos gate - Google Patents
Semiconductor device having mos gateInfo
- Publication number
- JPH06310729A JPH06310729A JP5096394A JP9639493A JPH06310729A JP H06310729 A JPH06310729 A JP H06310729A JP 5096394 A JP5096394 A JP 5096394A JP 9639493 A JP9639493 A JP 9639493A JP H06310729 A JPH06310729 A JP H06310729A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- region
- layer
- type region
- semiconductor device
- Prior art date
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- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000010410 layer Substances 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims abstract 4
- 239000012212 insulator Substances 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 abstract description 23
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 238000010894 electron beam technology Methods 0.000 abstract description 7
- 230000004888 barrier function Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＭＯＳゲートを備える
半導体装置の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor device having a MOS gate.
【０００２】[0002]
【従来の技術】絶縁ゲート型バイポーラトランジスタ即
ちＩＧＢＴ（ＩｎｓｕｌａｔｅｄＧａｔｅ Ｂｉｐｏｌ
ａｒ Ｔｒａｎｓｉｓｔｏｒ）は、モータ制御またはイ
ンバータなどの各種スイッチング素子として広く用いら
れている。2. Description of the Related Art Insulated gate type bipolar transistor or IGBT (Insulated Gate Bipol)
ar Transistor) is widely used as various switching elements such as motor control or inverters.
【０００３】ＩＧＢＴの構造は、通常のパワ−ＭＯＳＦ
ＥＴのドレイン領域に連続して、これと反対導電型のア
ノード領域を重ねて形成したものであり、Ｎ型ＩＧＢＴ
の断面図を図１により説明する。The structure of the IGBT is a normal power MOSF.
An N-type IGBT is formed by continuously forming a drain region of ET and overlapping an anode region of opposite conductivity type.
A sectional view of the above will be described with reference to FIG.
【０００４】即ち、縦型ＩＧＢＴのアノード領域として
機能するＰ+ １、Ｎ+ ２更にＮ- ３の順に重ねて構成す
る例えばシリコンから成る半導体基板の高比抵抗領域Ｎ
- ３表面から内部に向けてＰ拡散層４を設け、このＰベ
ース拡散層４内に環状のＮ+ソース拡散層５を形成す
る。That is, a high specific resistance region N of a semiconductor substrate made of, for example, silicon, which is formed by stacking P + 1, N + 2 and N - 3 which function as an anode region of a vertical IGBT in this order.
- 3 P diffusion layer 4 is provided toward the inside from the surface, to form an N + source diffusion layer 5 of the ring to the P base diffusion layer 4.
【０００５】また、Ｎ+ ソース拡散層５と高比抵抗領域
Ｎ- ３に挟まれたＰベース拡散層４部分をチャンネル領
域６として動作させるために、これを覆ってゲート絶縁
物層７を設置する。更に、ゲート絶縁物層７に重ねて多
結晶珪素層から成るゲート電極８を配置すると共に、こ
れを覆う層間絶縁物層９を設置する。Further, in order to operate the portion of the P base diffusion layer 4 sandwiched between the N + source diffusion layer 5 and the high specific resistance region N - 3 as the channel region 6, the gate insulating layer 7 is provided so as to cover it. To do. Further, a gate electrode 8 made of a polycrystalline silicon layer is arranged so as to overlap the gate insulator layer 7, and an interlayer insulator layer 9 covering the same is provided.
【０００６】一方、環状のＮ+ ソース拡散層５部分及び
これに挟まれかつ連続したＰベース拡散層４部分更に層
間絶縁物層９表面に連続してバリヤ金属層即ち金属層１
０を配置し、これに配線として機能する電極１１を積層
して形成する。On the other hand, a portion of the ring-shaped N + source diffusion layer 5 and a portion of the P base diffusion layer 4 which is sandwiched between the N + source diffusion layer 4 and the ring-shaped N + source diffusion layer 5 are further connected to the surface of the interlayer insulating layer 9 to form a barrier metal layer, that is, a metal layer 1.
0 is arranged, and an electrode 11 functioning as a wiring is laminated on this.
【０００７】アノード領域Ｐ+ １には、アノ−ド電極１
２を設けて、ＩＧＢＴを構成することによって、高入力
インピーダンスで、低オン抵抗の特性とすることが特徴
である。An anode electrode 1 is formed in the anode region P + 1.
2 is provided to form an IGBT, which is characterized by high input impedance and low on-resistance.
【０００８】[0008]
【発明が解決しようとする課題】以上のＩＧＢＴのソー
ス電極では、半導体基板を構成するシリコンがアルミニ
ウムに拡散するのを防ぐために、Ｔｉなどをバリヤ金属
即ち金属層１０を薄く形成し、ここにアルミニウムを含
む金属電極１１を設けてソース電極として機能する方式
が採られている。In the above-mentioned IGBT source electrode, in order to prevent the silicon constituting the semiconductor substrate from diffusing into aluminum, a barrier metal, that is, a metal layer 10 is formed thinly with Ti or the like. A method is adopted in which the metal electrode 11 including is provided to function as a source electrode.
【０００９】他の方法としては、金属層１０を形成せず
に電極１１としてアルミニウムに微量のシリコンを固溶
したＡｌ−ＳｉやＡｌ−Ｓｉ−Ｃｕを使用する例がある
が、信頼性やオン抵抗に関して金属層１０を設置する方
が有利である。更に、このようにソース電極として動作
する金属層１０は、前記のように層間絶縁物層９上に形
成する。このようなＩＧＢＴ素子では、アノード領域か
らドレイン領域に注入する少数キャリアの一部が過剰キ
ヤリアとして蓄積されるので、遮断時にゲート印加電圧
を零にしてチャンネルを閉じて、エレクトロンの流れを
止めても蓄積した少数キャリアが排出されるまで、オフ
状態に戻らない。その上、ドレイン領域に残るエレクト
ロンがアノード領域を通り抜ける際アノード領域から少
数キャリアの注入を誘起してターンオフ時間を大きくす
る。As another method, there is an example of using Al-Si or Al-Si-Cu in which a small amount of silicon is solid-dissolved in aluminum as the electrode 11 without forming the metal layer 10. It is advantageous to place the metal layer 10 in terms of resistance. Further, the metal layer 10 thus acting as the source electrode is formed on the interlayer insulating layer 9 as described above. In such an IGBT element, a part of the minority carriers injected from the anode region to the drain region is accumulated as an excess carrier, so that the gate applied voltage is set to zero at the time of interruption and the channel is closed to stop the electron flow. It does not return to the off state until the accumulated minority carriers are discharged. Moreover, when the electrons remaining in the drain region pass through the anode region, injection of minority carriers is induced from the anode region to increase the turn-off time.
【００１０】ターンオフ時間を改善する方法としては、
電子線を照射してキャリアのライフタイムを小さくする
方法が知られているが、ゲート酸化膜に発生した固定電
荷により、Ｎｃｈ−ＩＧＢＴのしきい値電圧が低下す
る。低下したしきい値電圧を回復するために電子線照射
後に熱処理を施す。As a method of improving the turn-off time,
A method of irradiating an electron beam to reduce the carrier lifetime is known, but the fixed charge generated in the gate oxide film lowers the threshold voltage of the Nch-IGBT. In order to recover the lowered threshold voltage, heat treatment is performed after the electron beam irradiation.
【００１１】この４００℃程度の熱負荷によりＮ+ ドレ
イン領域の損傷が回復するのに対して、キャリアのライ
フタイムは、電子線照射前の状態に戻ってしまうので、
熱処理温度としては、３５０℃以下が選ばれている。Although the damage of the N + drain region is recovered by the heat load of about 400 ° C., the lifetime of the carrier returns to the state before the electron beam irradiation.
As the heat treatment temperature, 350 ° C. or lower is selected.
【００１２】このような熱処理工程によりしきい値電圧
を許容範囲内に回復することができるが、ゲート絶縁物
層中の損傷が完全に回復しないと、ＩＧＢＴの動作に伴
いしきい値の変動（上昇）が発生する。Although the threshold voltage can be recovered within the permissible range by such a heat treatment process, if the damage in the gate insulating layer is not completely recovered, the fluctuation of the threshold value accompanying the operation of the IGBT ( Rise) occurs.
【００１３】一方、ソース電極のバリア金属として金属
層Ｔｉを使用すると、電子線照射後の熱処理は、ゲート
絶縁物層中の損傷の回復を阻害して、しきい値電圧が完
全に回復せず、経時変化を起こすもとになる。On the other hand, when the metal layer Ti is used as the barrier metal of the source electrode, the heat treatment after the electron beam irradiation hinders the recovery of damage in the gate insulating layer, and the threshold voltage is not completely recovered. , Causes the change over time.
【００１４】本発明は、このような事情により成された
もので、特に、電子線照射後の熱処理によりしきい値電
圧が十分に回復しかつ、経時変化が発生しない上に信頼
性の高いＭＯＳ型ゲートを備える半導体装置を提供する
ことを目的とする。The present invention has been made in view of the above circumstances, and in particular, the threshold voltage is sufficiently recovered by the heat treatment after the electron beam irradiation, and the change with time does not occur, and the MOS is highly reliable. An object of the present invention is to provide a semiconductor device including a mold gate.
【００１５】[0015]
【課題を解決するための手段】第１導電型の半導体基板
表面から内部に向けて形成する第２導電型の領域と，前
記第２導電型の領域内に環状に設ける第１導電型の領域
と，前記第１導電型の領域と第２導電型の領域の外周を
占めかつこれに連続する第２導電型領域に設けるチャン
ネル領域と，前記チャンネル領域を覆って形成する絶縁
物層と，前記絶縁物層に重ねて配置するゲート電極と，
前記ゲート電極を被覆する層間絶縁物層と，前記環状の
第１導電型の領域部分及びこれに連続かつ露出する第２
導電型の領域の表面部分に積層して配置しかつ、前記層
間絶縁物層の側部だけに連続する金属層と、前記金属層
に積層して配置する電極層とに本発明に係わるＭＯＳゲ
ートを備える半導体装置の特徴がある。A second conductivity type region is formed from the surface of a first conductivity type semiconductor substrate toward the inside, and a first conductivity type region is provided in a ring shape in the second conductivity type region. A channel region that occupies the outer periphery of the first conductivity type region and the second conductivity type region and is provided in a second conductivity type region that is continuous with the region; and an insulator layer formed to cover the channel region, A gate electrode which is arranged so as to overlap the insulating layer,
An interlayer insulating layer covering the gate electrode, the annular first conductivity type region portion, and a second continuous and exposed portion
A MOS gate according to the present invention is provided on a metal layer laminated on the surface of a conductivity type region and continuous only on the side of the interlayer insulating layer, and on an electrode layer laminated on the metal layer. There is a feature of the semiconductor device including
【００１６】また、金属層をＴｉ、ＷまたはＭｏから成
る郡から選定する一種を含み、電極層をアルミニウムを
主成分とすることにも特徴がある。Another feature is that the metal layer includes one selected from the group consisting of Ti, W or Mo, and the electrode layer contains aluminum as a main component.
【００１７】[0017]
【作用】本発明に係わるＭＯＳゲートを備える半導体装
置は、ソース拡散層とベース拡散層の両方に接触するよ
うにバリア金属である金属層を形成して、ゲート電極上
に設置しない点に特徴がある。と言うのは、このような
構成にすることにより、比較的低温での処理によりゲー
ト絶縁膜即ち絶縁物層中の損傷が回復できるとの事実を
基に完成したものである。A semiconductor device having a MOS gate according to the present invention is characterized in that a metal layer which is a barrier metal is formed so as to be in contact with both the source diffusion layer and the base diffusion layer and is not placed on the gate electrode. is there. This is completed based on the fact that with such a structure, the damage in the gate insulating film, that is, the insulating layer can be recovered by the treatment at a relatively low temperature.
【００１８】[0018]
【実施例】本発明に係わる実施例を図２乃至図６を参照
して説明する。Embodiments of the present invention will be described with reference to FIGS.
【００１９】従来の技術欄に示したように、ＩＧＢＴの
構造は、通常のパワＭＯＳＦＥＴのドレイン領域に連続
して、これと反対導電型のアノード領域を重ねて構成し
ており、本発明に係わるＮ型で縦型のＩＧＢＴを示す図
２により先ず説明する。As shown in the section of the prior art, the structure of the IGBT is constructed such that the drain region of a normal power MOSFET is continuous with the anode region of the opposite conductivity type and overlaps with the drain region. First, a description will be given with reference to FIG. 2 showing an N-type vertical IGBT.
【００２０】アノード領域として機能するＰ+ １、Ｎ+
２更にＮ- ３の順に重ねて、例えばシリコンから成る半
導体基板を構成し、最上層を構成する高比抵抗領域即ち
第１導電型の半導体基板３表面から内部に向けてＰ拡散
層即ち第１導電型の領域４を形成する。この第１導電型
の領域４内には、環状のＮ+ ソース拡散層即ち第２導電
型の領域５を形成する。また、集積回路素子を形成する
ために、第１導電型の領域４を複数個形成し、この中に
環状の第２導電型の領域５を形成することもある。P + 1, N + which functions as an anode region
2 and N − 3 are stacked in this order to form a semiconductor substrate made of, for example, silicon, and a P diffusion layer, that is, a first diffusion layer, that is, a first conductivity type semiconductor substrate 3 that forms the uppermost layer from the surface toward the inside. A conductivity type region 4 is formed. An annular N + source diffusion layer, that is, a second conductivity type region 5 is formed in the first conductivity type region 4. Further, in order to form an integrated circuit element, a plurality of first conductivity type regions 4 may be formed, and an annular second conductivity type region 5 may be formed therein.
【００２１】環状の第２導電型の領域４と高比抵の第１
導電型の半導体基板３に挟まれた第２導電型の領域４部
分をチャンネル領域６として動作させるために、これを
覆って厚さが１０００オングストローム程度の酸化珪素
層即ちゲート絶縁物層７を設置する。更に、ゲート絶縁
物層７に重ねて多結晶珪素層から成り厚さが約５０００
オングストロームのゲート電極８を配置すると共に、こ
れを覆う層間絶縁物層９を例えばＣＶＤ（ Ｃｈｅｍｉ
ｃａｌ Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ）法によ
り設置する。このような厚さの層間絶縁物層９には、そ
の厚さ方向を占める側部Ａが形成される。The annular second conductivity type region 4 and the first high resistivity region
In order to operate the region 4 of the second conductivity type sandwiched by the semiconductor substrate 3 of the conductivity type as the channel region 6, a silicon oxide layer having a thickness of about 1000 Å, that is, a gate insulator layer 7 is provided so as to cover it. To do. Further, the gate insulator layer 7 is formed of a polycrystalline silicon layer and has a thickness of about 5000.
An angstrom gate electrode 8 is arranged, and an interlayer insulating layer 9 covering it is formed, for example, by CVD (Chemi).
It is installed by the cal vapor deposition method. A side portion A occupying the thickness direction is formed in the interlayer insulating layer 9 having such a thickness.
【００２２】一方、環状のＮ+ ソース拡散層５部分及び
これに挟まれかつ連続した第２導電型の領域４部分更に
層間絶縁物層９表面の側面部分Ａのみに連続する金属層
１０を配置し、これに配線として機能する電極１１を積
層して縦型ＩＧＢＴを完成する。このような縦型ＩＧＢ
Ｔは、電子線を照射後ほぼ３５０℃で熱処理を行ってし
きい値電圧Ｖthを回復後、図３に明らかにする高温逆バ
イアス試験を行い、その結果を図４に示した。図４の比
較例は、図１の従来の縦型ＩＧＢＴを対象としたもので
ある。On the other hand, a ring-shaped N + source diffusion layer 5 portion, a second conductivity type region 4 portion which is sandwiched between the N + source diffusion layer 5 portion and a continuous metal layer 10 are disposed only on the side surface portion A of the interlayer insulating layer 9. Then, the electrodes 11 functioning as wirings are stacked on this to complete the vertical IGBT. Such a vertical IGB
T was subjected to heat treatment at about 350 ° C. after irradiation with an electron beam to recover the threshold voltage V th, and then a high temperature reverse bias test shown in FIG. 3 was performed. The results are shown in FIG. The comparative example of FIG. 4 is intended for the conventional vertical IGBT of FIG.
【００２３】図３における高温逆バイアス試験は、縦型
ＩＧＢＴトランジスタ（図２参照）のエミッタとコレク
タ間にダイオードＤを順方向に接続し、ベースエミッタ
間にツェナダイオードＺをクランプし、ベースとエミッ
タの間に抵抗Ｒを介して電源ＶGEを配置する。しかも、
ダイオードＤ、ツェナダイオードＺ及び抵抗Ｒは、縦型
ＩＧＢＴトランジスタ外部に接続し、測定温度は、約１
２５℃である。In the high temperature reverse bias test shown in FIG. 3, the diode D is connected in the forward direction between the emitter and collector of the vertical IGBT transistor (see FIG. 2), the Zener diode Z is clamped between the base and the emitter, and the base and the emitter are clamped. A power source V GE is arranged between the two via a resistor R. Moreover,
The diode D, the Zener diode Z, and the resistor R are connected to the outside of the vertical IGBT transistor, and the measurement temperature is about 1
25 ° C.
【００２４】外部の各部品と接続する縦型ＩＧＢＴトラ
ンジスタ端子は、図２にエミッタをＥ、ベースをＢ更に
コレクタをＣと記載した。The vertical IGBT transistor terminal connected to each external component is shown in FIG. 2 by referring to E for the emitter, B for the base and C for the collector.
【００２５】このような高温逆バイアス試験の結果は、
縦軸に１０００時間後のＶth、横軸に初期（Ｉｎｔｉａ
ｌ）のＶthを採った図４に明らかにした。これにある比
較例では、＋５％程度の変動が見られるのに対して、本
願は、殆ど変動がない。いいかえれば金属層を層間絶縁
物層の上部には、設置せず側部だけに接触かつ連続さ
せ、更に、Ｎ+ ソース拡散層５部分と、これに挟まれか
つ露出するＰ拡散層４部分に重ねて形成する構造による
効果が判然としている。The results of such a high temperature reverse bias test are
The vertical axis indicates V th after 1000 hours, and the horizontal axis indicates initial (Intia
Vth of 1) is shown in FIG. In this comparative example, a fluctuation of about + 5% is observed, whereas in the present application, there is almost no fluctuation. In other words, the metal layer is not placed on the interlayer insulating layer and is contacted and continuous only with the side portion, and further, the N + source diffusion layer 5 portion and the P diffusion layer 4 portion sandwiched between and exposed to this are formed. The effect of the structure formed by overlapping is clear.
【００２６】また図５は、本発明に係わるＭＯＳＦＥＴ
を、図６は、同じく横型ＩＧＢＴを示した。ＭＯＳＦＥ
Ｔは、半導体基板をＮ+ 、Ｎ- の半導体層により構成す
る点が図２と違い、その他はほぼ同じ構造である。FIG. 5 shows a MOSFET according to the present invention.
FIG. 6 also shows a lateral IGBT. MOSFE
The T has a structure similar to that of FIG. 2 in that the semiconductor substrate is composed of N + and N − semiconductor layers, and is otherwise the same.
【００２７】図６に明かにする横型のＩＧＢＴでは、コ
レクタ端子を別途形成する。即ち、図２における金属層
１０−Ｅ、Ｐ拡散層４−Ｂ及びＮ+ ソース拡散層５によ
り構成するトランジスタのエミッタとベースに対して、
別にコレクタ領域１３を形成する点が特徴である。In the lateral IGBT shown in FIG. 6, the collector terminal is separately formed. That is, with respect to the emitter and base of the transistor constituted by the metal layer 10-E, the P diffusion layer 4-B and the N + source diffusion layer 5 in FIG.
Another feature is that the collector region 13 is formed separately.
【００２８】即ち、第１導電型の半導体基板３の所定の
位置に第１導電型のＮ+ 領域１４を形成し、この中に第
１導電型のＰ+ 拡散層１５を設けてコレクタ領域１３を
構成する。That is, the N + region 14 of the first conductivity type is formed at a predetermined position of the semiconductor substrate 3 of the first conductivity type, and the P + diffusion layer 15 of the first conductivity type is provided therein to collect the collector region 13. Make up.
【００２９】図７は、図２に明かにした縦型ＩＧＢＴの
他の例であり、相違点は、金属層１０にある。図２にあ
っては、層間絶縁物層９の側面部分Ａだけに形成するの
に対して、図７では、側面全体の加えて層間絶縁物層９
表面部分も被覆しており、製造プロセスの相違即ち金属
層１０のパターニング工程の有無によりもたらされるも
のである。FIG. 7 shows another example of the vertical IGBT shown in FIG. 2, and the difference lies in the metal layer 10. In FIG. 2, it is formed only on the side surface portion A of the interlayer insulating layer 9, whereas in FIG.
The surface portion is also covered and is caused by the difference in the manufacturing process, that is, the presence or absence of the patterning step of the metal layer 10.
【００３０】[0030]
【発明の効果】以上のように、本発明に係わるＭＯＳゲ
ートを備える半導体装置は、ゲート電極上にバリア金属
であるチタンなどから成る金属層が介在していないの
で、比較的低温の熱処理によりゲート電極の損傷が回復
きる。As described above, in the semiconductor device having the MOS gate according to the present invention, since the metal layer made of titanium or the like which is the barrier metal is not present on the gate electrode, the gate is formed by heat treatment at a relatively low temperature. The electrode damage is completely recovered.
【００３１】従って、しきい値電圧Ｖthが十分に回復
し、経時変化もなく信頼性の高いＭＯＳゲートを備える
半導体装置を提供できる。Therefore, it is possible to provide a semiconductor device having a highly reliable MOS gate in which the threshold voltage V th is sufficiently recovered and does not change with time.
【図１】従来のＭＯＳゲートを備える半導体装置の断面
図である。FIG. 1 is a cross-sectional view of a semiconductor device including a conventional MOS gate.
【図２】本発明に係わるＭＯＳゲートを備える半導体装
置の一実施例であるＩＧＢＴの断面図である。FIG. 2 is a cross-sectional view of an IGBT which is an embodiment of a semiconductor device having a MOS gate according to the present invention.
【図３】高温逆バイアス試験用回路図である。FIG. 3 is a circuit diagram for a high temperature reverse bias test.
【図４】図３の回路によりＭＯＳゲートを備える半導体
装置に高温逆バイアス試験を行った結果を示す図であ
る。FIG. 4 is a diagram showing a result of performing a high temperature reverse bias test on a semiconductor device having a MOS gate by the circuit of FIG.
【図５】本発明の第２の実施例を示す断面図である。FIG. 5 is a sectional view showing a second embodiment of the present invention.
【図６】本発明の第３の実施例を示す断面図である。FIG. 6 is a sectional view showing a third embodiment of the present invention.
【図７】本発明の第４の実施例を示す断面図である。FIG. 7 is a sectional view showing a fourth embodiment of the present invention.
１：第１導電型の半導体基板、 ２、３：第２導電型の半導体基板、 ４：第１導電型の領域、 ５：第２導電型の領域、 ６：チャンネル領域、 ７：絶縁物層、 ８：ゲート電極、 ９：層間絶縁物層、 １０：金属層、 １１：配線層。 1: semiconductor substrate of the first conductivity type, 2, 3: semiconductor substrate of the second conductivity type, 4: first conductivity type region, 5: second conductivity type region, 6: channel region, 7: insulator layer , 8: gate electrode, 9: interlayer insulating layer, 10: metal layer, 11: wiring layer.
Claims (2)
向けて形成する第２導電型の領域と，前記第２導電型の
領域内に環状に設ける第１導電型の領域と，前記第１導
電型の領域の外周を占めかつこれに連続する第２導電型
領域に設けるチャンネル領域と，前記チャンネル領域を
覆って形成する絶縁物層と，前記絶縁物層に重ねて配置
するゲート電極と，前記ゲート電極を被覆する層間絶縁
物層と，前記環状の第１導電型の領域部分及びこれに連
続かつ露出する第２導電型の領域の表面部分に積層して
配置しかつ、前記層間絶縁物層の側部だけに連続する金
属層と、前記金属層に積層して配置する電極層とを具備
することを特徴とするＭＯＳゲートを備える半導体装置1. A region of the second conductivity type formed from the surface of a semiconductor substrate of the first conductivity type toward the inside, a region of the first conductivity type provided annularly in the region of the second conductivity type, and the first region. A channel region that is provided in a second conductivity type region that occupies the outer periphery of the one conductivity type region and is continuous with this, an insulator layer that is formed to cover the channel region, and a gate electrode that is arranged so as to overlap the insulator layer. An interlayer insulating layer covering the gate electrode, a ring-shaped first conductivity type region portion and a surface part of a second conductivity type region continuous with and exposed from the first conductivity type region portion, and the interlayer insulation layer. A semiconductor device having a MOS gate, comprising a metal layer continuous only on a side portion of a physical layer, and an electrode layer laminated and arranged on the metal layer.
またはＭｏから成る群から選定する一種を含み、電極層
をアルミニウムを主成分とすることを特徴とするＭＯＳ
ゲートを備える半導体装置2. The metal layer according to claim 1 is formed of Ti, W
Alternatively, a MOS including one selected from the group consisting of Mo and having an electrode layer containing aluminum as a main component.
Semiconductor device with gate
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5096394A JPH06310729A (en) | 1993-04-23 | 1993-04-23 | Semiconductor device having mos gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5096394A JPH06310729A (en) | 1993-04-23 | 1993-04-23 | Semiconductor device having mos gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06310729A true JPH06310729A (en) | 1994-11-04 |
Family
ID=14163748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5096394A Pending JPH06310729A (en) | 1993-04-23 | 1993-04-23 | Semiconductor device having mos gate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06310729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11869961B2 (en) | 2016-09-20 | 2024-01-09 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
1993
- 1993-04-23 JP JP5096394A patent/JPH06310729A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11869961B2 (en) | 2016-09-20 | 2024-01-09 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
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