JPH06309288A - Low power consumption circuit for parallel multiprocessor system - Google Patents

Abstract

PURPOSE:To hold the highest performance of a system, and to suppress the total power consumption at the time of a processing operation to the minimum by deciding the number of processors (CP) which actually operate parallel processings according to task amounts which are changed according to a time, and disconnecting the operating power sources of the residual CP. CONSTITUTION:A monitoring means 1 such as a counter which monitors the total of a waiting time for an interrupting request from each I/O to plural CP in parallel is provided as an SV in addition to a conventional monitoring circuit for monitoring a fault. The SV counter of the monitoring means 1 counts the total time of a time until each CP responds to the interruption request generated from each I/O, and the cycle of an interrupting operation is actually started, that is, the waiting time since the interrupting request is issued, the number of the CP which are actually operated in parallel is decided according to the waiting time, and supply power sources to the CP which are not operated are turned off. After the number of the CP which are actually operated is decided, at the time of increasing the number of the CP, the supply power sources to the CP which are additionally operated are turned on, and at the time of decreasing the number of the CP, the power sources to the pertinent CP are turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption method for suppressing the total power consumption of a parallel multiprocessor system to a minimum. 2. Description of the Related Art In recent years, with the increase in speed of computers and control devices and the increase in processing amount, parallel processing type multiprocessors have been required, and the total power consumption of systems has increased. In order to reduce the operating cost of the system, it is necessary to minimize the total power consumption of the parallel multiprocessor system. However, system performance should not be compromised.

[0002]

2. Description of the Related Art There is no fundamental solution for reducing the power consumption without degrading the performance of the system. Conventionally, in the parallel multiprocessor system shown in FIG. Range, processor C
This has been dealt with by reducing the clock rate of P, delaying the operation cycle of the common bus with each I / O, and replacing some of the devices used with low-speed type.

[0003]

Therefore, the above-mentioned conventional method has a problem that it is not the suppression of the total power consumption while maintaining the maximum performance of the system. An object of the present invention is to realize a method of suppressing the total power consumption to the minimum while maintaining the maximum performance of the system.

[0004]

The basic idea of the present invention for achieving this object is as follows. Normal processor C
The amount of task (load) processed by P depends on the amount of communication performed by each I / O with an external device, so it is not always constant but changes with time. As the number of I / Os communicating with the external device increases, the amount of tasks the CP receives and processes an interrupt request from each I / O increases. When the amount of tasks to be processed is large, all of the parallel CPs are operated, but when the amount of tasks is small, only one or two CPs among them are processed, and the remaining CPs are not processed and work. Although it is in a standby state, the power supply power is consumed and the power is wasted. The basic configuration of the present invention is, as shown in the principle diagram of FIG. 1, provided with a monitoring means 1 for monitoring the total waiting time for interrupt requests from each I / O to a plurality of CPs in parallel, and totaling the monitoring results. Parallel C depending on increase / decrease of waiting time
The configuration is such that P knows the increase / decrease in the amount of tasks to be processed, determines the number of CPs that actually perform parallel processing, and cuts off the operating power supply of the remaining CPs.

[0005]

In the present invention, the monitoring means 1 monitors the total waiting time for interrupt requests from each I / O to a plurality of CPs in parallel, and the parallel CPs are controlled by increasing or decreasing the waiting time of the total of the monitoring results. Knowing the increase / decrease in the amount of tasks to be processed, the number of CPs that actually perform parallel processing is determined, and the operating power supply of the remaining CPs is cut off. Therefore, there is always wasteless power consumption according to the task amount.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The principle diagram of FIG. 1 is the same as that of the embodiment of the present invention, and FIG. 2 shows the power-on of each processor panel CP.
FIG. 3 shows the configuration of the / OFF control circuit, and FIG. 3 shows the relationship between the number of active CPs and the total interrupt waiting time. In Figure 1, each I / O
Communicates with each external device, and when a task to be processed occurs, the CP is notified by an interrupt to request processing. At this time,
If the number of parallel CPs operating is one, the task occurrence rate becomes large, the waiting time increases, and the system performance deteriorates. However, in the present invention, a plurality of CPs are connected in parallel from each I / O. A monitoring means 1 such as a counter for monitoring the total waiting time for an interrupt request to the device is provided as SV in addition to the conventional monitoring circuit SV _A for fault monitoring. The SV counter of the embodiment of the interrupt waiting time monitoring means 1 of the present invention is
The time until each CP responds to the interrupt request generated at O and the cycle of the interrupt operation is actually started, that is, the total waiting time after raising the interrupt request is counted, and according to the waiting time Determine the number of CPs that are actually operated in parallel, and turn off the power supply to the CPs that are not operated. After deciding, if the number of CPs is to be increased, the power supply to the CPs to be additionally operated is turned on, and if the number of CPs is to be reduced, the power to the corresponding CPs is turned off. By these operations, it is possible to always consume power without waste according to the task amount. Current C
In addition to the CPU, the P circuit consists of local RAM, ROM, and peripheral circuits.
Since the LSI is installed, the power consumption per CP is several amperes. As a parallel system, the larger the number of parallel CPs mounted, the greater the processing capacity per unit time, but the power consumption lost when there is no task to be processed increases, so the effect of the power consumption reduction circuit of the present invention is remarkable. Is. Figure 2 shows the ON / OFF control for each CP power supply.
As shown in, only the power control logic circuit that generates the control signal of the relay SW that turns on / off the power input + 5v to the main circuit section by the control line signal from the SV is always on. Is its power input + 5v is O of the output of the logic circuit.
Controlled by N / OFF signal.

The SV of the interrupt waiting time monitoring means 1 of the present invention shown in FIG. 1 outputs a signal line for controlling the power supply to each CP, and each CP accesses the shared memory MEM through a common bus. The so-called interrupt cycle is monitored and the interrupt waiting time is counted. The method of realizing the function of this SV can be realized by hardware or software.

[0008]

As described above, according to the present invention, the number of CPs that actually perform parallel processing is determined according to the task amount that changes with time, and the operating power supply of the remaining CPs is cut off. The effect of always performing processing operations with the minimum required power consumption can be obtained without degrading the system performance.

[Brief description of drawings]

FIG. 1 is a principle diagram showing a basic configuration of a low power consumption circuit of a parallel multiprocessor system of the present invention.

FIG. 2 is a configuration diagram of a power ON / OFF control circuit of each processor panel CP according to the embodiment of the present invention.

FIG. 3 is a diagram showing the relationship between the number of operating CPs and the total interrupt waiting time according to the embodiment of this invention.

FIG. 4 is a block diagram of a conventional parallel multiprocessor system.

[Explanation of symbols]

1 is a monitoring means SV interrupt latency counter for SV, CP is each processor, each processor panels, SV _A is a conventional fault monitoring circuit.

Claims (1)

[Claims] 1. In a low power consumption circuit of a multiprocessor system in which a plurality of CPs processes data in a shared memory in parallel in parallel by interrupt requests from a plurality of I / Os in parallel, a plurality of CPs are paralleled to each other. Provides monitoring means (1) to monitor the total waiting time for each I / O interrupt request, and knows the increase or decrease in the total waiting time of the monitoring result, and the increase or decrease in the amount of tasks to be processed by the parallel CP. A power saving circuit for a parallel multiprocessor system, characterized in that the number of CPs to be processed in parallel is determined and the operating power supplies of the remaining CPs are cut off.