JPH0630056B2 - Signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing device that performs an operation mainly for signal processing.

[Conventional technology]

Fig. 5 shows a host processor using a digital signal processing processor (DSSP1) mainly for audio signal processing, which was shown in, for example, the 1986 Proceedings of the Symposium of the IEICE Communications Division National Conference (No.S10-1). FIG. 3 is a simplified block diagram showing a signal processing device controlled by a sensor. (1) is a host processor that controls the signal processing device, (2) is a signal processing processor that mainly performs signal processing, and (3)
Is an instruction memory selection signal, (4) is a signal processing processor (2)
Reset signal for initializing, a program counter (abbreviated as PC below) (5), an instruction address (6), and a read-only instruction memory (8) in which an instruction word is stored in advance. The stored external instruction memory, (9) is a switching circuit for selecting one of the two instruction words by the selection signal (3), and (10) is an instruction word register (holding an instruction word ( Hereinafter, abbreviated as IR), (11) is a decoder that decodes an instruction word, (12) is an arithmetic processing unit that performs various arithmetic processes, (13) is a control signal, and (14) stores arithmetic data that performs signal processing. The data memory, (15), is the calculated data. Further, FIG. 6 is a flow chart for explaining the operation.

Next, the operation of this signal processing will be described with reference to FIGS. 5 and 6. First, when the power is turned on, the host processor (1) starts its operation, and outputs to the signal processing processor (2) a selection signal (3) for selecting which internal or external instruction memory is used. When the logical value of the selection signal (3) is "0", the internal instruction memory is selected, and when the logical value is "1", the external instruction memory is selected.
After that, the host processor (1) is the signal processing processor (2).
To reset signal (4). When the signal processing processor (2) receives the reset signal (4), it initializes the internal registers and the like and sets the value of the PC (5) to zero. Next, the instruction address (6) indicating the address 0 output from the PC (5) is the read-only instruction memory (7) inside the signal processing processor (2).
And an external external instruction memory (8), and the instruction word at that address is read and input to the switching circuit (9). In the switching circuit (9), either one of the command words is selected by the selection signal (3) given from the host processor (1), and I
Set to R (10). The instruction word set in the IR (10) is decoded (decoded) by the decoder (11) to generate control signals for each section. The arithmetic processing unit (12) inside the signal processing processor (2) is controlled by the control signal (13) from the decoder (11), and various arithmetic operations are performed on the arithmetic data (15) in the data memory (14). Done.

When performing complicated signal processing in the conventional device, the program tends to be large, and the signal processing processor (2)
It is necessary to use the external instruction memory (8) because the program capacity of the internal read-only instruction memory (7) is insufficient. When using the external instruction memory (8), output the instruction address (6) and input the instruction word using the external terminal
(2) An input / output element is required for exchanging internal signals and external signals, and an instruction word is read in order to pass through an extra element for reading from the internal read-only instruction memory (7). It takes longer to get to. Therefore, when using the external instruction memory (8), a clock with a long cycle must be given to the signal processing processor (2), and after the instruction memory is switched, the reset signal (4) is input, If you do not make initial settings, it will malfunction.

The read-only instruction memory (7) inside the signal processing processor (2) is composed of a so-called mask ROM in which a program is written in advance when the processor is manufactured, and is a dedicated program for performing a specific process. It seems to write.

[Problems to be solved by the invention]

Since the conventional signal processing device is configured as described above, in order to allow the signal processing processor to perform complicated processing and other processing, an external instruction memory is provided, and it is possible to read and execute an instruction word from the outside. The processing time is reduced by half because it takes time to read an instruction word from the outside, and the instruction memory inside the signal processing processor is a write-only memory. Therefore, the program cannot be changed after the processor is manufactured, and the program error occurs. In case of any modification or modification, it is necessary to remanufacture the processor and replace the signal processing processor itself, resulting in low development efficiency and uneconomical problems.

The present invention has been made to solve the above problems, and a program can be easily changed by an instruction from a host processor, which causes a large addition of hardware and a decrease in processing efficiency. Without complicated processing or temporary execution of other processing in the signal processing processor, etc.
An object of the present invention is to obtain a signal processing device whose processing can be changed flexibly.

[Means for solving problems]

A signal processing device according to the present invention uses an instruction memory inside a signal processing processor as a writable instruction memory, controls temporary stop and restart of the signal processing processor according to an instruction from a host processor, and writes and reads the writable instruction memory. Is controlled.

[Action]

In the signal processing device according to the present invention, the operation of the signal processing processor is temporarily stopped in the host processor, the instruction memory inside the signal processing processor is rewritten, and then the operation is restarted to enable other processing. To do.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows an example in which a so-called verification is performed inside the processor to determine whether the contents written in the instruction memory inside the signal processing processor are correct. (21) is the host processor, (22) is the signal processing processor, and (23) ) Is a hold request signal for requesting a temporary stop of the instruction execution operation of the signal processing processor (22), (24) is a hold enable signal for notifying the outside that the suspension is in progress, (25) is a program counter, ( 26) is an instruction memory control unit, (27) is a rewritable instruction memory that can be rewritten, (28) is an instruction address,
(29) is a switching circuit, (30) is a selection signal, (31) is an external instruction memory, (32) and (33) are command words, (34) is a comparison circuit, (35) is a judgment result, (36). Is a write end signal. In the figure, the arithmetic processing unit is omitted because it is similar to the conventional example. Also, the second
The figure is a flow chart for explaining the operation.

Further alternatively, the comparison circuit (34) is a determination means.

The operation will be described below with reference to FIGS. 1 and 2. When it becomes necessary to change the processing contents of the signal processing processor (22) in the host processor (21), a hold request signal (23) for requesting the signal processing processor (22) to temporarily suspend the execution of the instruction word. To set. When the signal processing processor (22) receives a hold request, it immediately outputs a hold permission signal (24) when the currently executing instruction is completed, stops updating the PC (25), and suspends execution of the instruction word.

Next, a writable instruction memory (2
The selection signal (30) is output so that the instruction address (28) for designating which address of 7) is rewritten and the instruction address (28) is selected by the switching circuit (29). The instruction address (28) is also output to the external instruction memory (31) at the same time, from which the instruction word
(32) is output and written to the writable instruction memory (27). The instruction word (32) written in the writable instruction memory (27) is read again from the writable instruction memory (27), and the read instruction word (33) and the written instruction word (32) are compared ( It is input to 34) and it is determined whether the two command words match. If the two command words do not match, it means that an error occurred when writing to the writable command memory (27), and the write error flag inside the command memory control unit (26) is set according to the judgment result (35). . This flag is not reset until all writes are complete.

The above operation is repeated until the writing of one instruction word is completed and the rewriting of all the instruction words is completed. After the completion of all writing, the state of the write error flag of the instruction memory control unit (26) is checked, and if it is set, the flag is reset and the writing of the instruction word is started again. When the write error flag is not set and the rewriting is completed normally, the write end signal (36) is output to the host processor (21). In the host processor (21), hold request signal (2
Cancel 3) to cancel the pause. Signal processing processor
When the hold request signal (23) is released at (22), the instruction memory control section (26) outputs a selection signal (30) so that the switching circuit (29) selects the instruction address of the PC (25). , PC (25)
Updates the instruction address, and when paused, the instruction is executed from the instruction address next to the instruction address of the last executed instruction word. By thus making the instruction memory inside the signal processing processor rewritable, it becomes possible to easily change the processing contents of the signal processing.
In addition, it is possible to prevent the processor from malfunctioning due to a rewrite error by incorporating a verify circuit inside.

Further, FIG. 3 shows an embodiment in which a judgment circuit for judging whether the contents of the writable instruction memory are correct is provided outside the signal processing processor, and FIG. 4 shows a flow chart for explaining the operation.

The point of changing the processing contents of the signal processing processor (22) will be described in detail.

There are various encoding algorithms in digital signal processing, especially in audio and image information compression, and it is impossible to preload all the processing procedures into the instruction memory of limited capacity inside the DSP. . When these voice and image communication devices are configured using the instruction rewritable DSP according to the present invention, the encoding algorithm of the partner device is queried after the line is established, not the initial load, and the matching algorithm is loaded into the DSP. This enables the same device to communicate with a communication partner having various encoding algorithms. In addition, the algorithm can be changed during communication, allowing flexible operation of the device.

Further, by providing these loaders inside the DSP, the peripheral circuits can be reduced, the degree of substrate integration is improved, the size of the device can be reduced, and the cost can be reduced.

The operation will be described below with reference to FIGS. 3 and 4. As in the case of FIG. 1, when it is necessary to change the processing contents of the signal processing processor (42) in the host processor (41), the hold request signal (23) is set and the PC
The update of (25) is stopped, and the execution of the command is suspended. When the hold enable signal (24) is received, the host processor
The instruction address (28) is output from (41) to the external instruction memory (31) and the signal processing processor (42). External instruction memory (3
The command word (32) read from 1) is input to the switching circuit (43) and is input to the signal processing processor (42) by the selection signal (44) from the host processor (41). Next, the instruction control signal (43) from the host processor (41) outputs the selection signal (48) from the instruction memory control unit (46) to the switching circuit (47), and the instruction to the writable instruction memory (27) is issued. The word (32) is written.
Next, the read control signal (49) is output from the host processor (41) and the written instruction word is writable.The instruction word (33) is read from the instruction memory (27) and switched from the instruction memory control unit (46). The selection signal (48) is output to the circuit (47), and the command word (33) is input to the switching circuit (43). The command word (33) is input to the comparison circuit (50) by the selection signal (44) from the host processor (41). The comparison circuit (50) compares the instruction word (32) read from the external instruction memory (31) with the instruction word (33) read from the writable instruction memory (27), and determines the judgment result (51). Output to the host processor (41). In the host processor (41), if the two instruction words match with each other according to the determination result (51), the instruction word is written next. If the two command words do not match, the command word is written again. When all the writing is completed, the host processor (41) releases the hold request signal (23) and restarts the operation of the signal processing processor (42), thereby achieving the same effect as that of the embodiment shown in FIG. be able to.

In this embodiment, m × n (m is an integer of 1 or more, n
Is an integer of 2 or more) When an instruction word with a bit width is read from the external instruction memory and input to the signal processing processor, m × n
Although the number of external terminals is required, if the number of bits is divided into m bit widths and the data is written into the internal writable instruction memory n times, m external terminals will suffice. For example, when inputting an instruction word with a width of 32 bits, it is necessary to input 32 words at a time.
Although it requires 8 external terminals, if it is divided into 8 bit widths and input 4 times, it is possible to input with only 8 external terminals, which requires 4 times time for rewriting. This is a very effective means when the number of terminals is limited.

〔The invention's effect〕

As described above, according to the present invention, the instruction memory inside the signal processor is made a writable instruction memory, its operation is temporarily stopped by an instruction from the host processor, and the instruction memory inside the signal processor is rewritten. Further, since the judging means judges writing of the command word in the writable command memory and the host processor controls the operation of the processor based on the judgment result, the program can be arbitrarily changed after the processor is manufactured. It can be done and development efficiency is high, it is economical, and even during signal processing, by temporarily stopping instruction execution, rewriting the program and restarting instruction execution, more complex signal processing,
Since a single signal processor can have various signal processing functions, more flexible signal processing can be performed. Further, there is an effect that it is possible to prevent a malfunction of the processor due to a rewriting mistake.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal processing device according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a block diagram showing the signal processing device shown in FIG. 4, FIG. 4 is a flow chart for explaining the operation of FIG. 3, FIG. 5 is a block diagram showing the conventional signal processing device, and FIG. 6 is the operation of the conventional example of FIG. It is a flow chart explaining. (21) is the host processor, (22) is the signal processing processor,
(23) is a hold request signal, (24) is a hold enable signal, and (2
5) is the program counter, (26) is the instruction memory controller, (2
7) is writable instruction memory, (28) is instruction address, (29)
Is a switching circuit, (30) is a selection circuit, (31) is an external instruction memory,
(32) and (33) are command words, (34) is a comparison circuit, (35) is a judgment result, and (36) is a write end signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-78248 (JP, A) "TMS32020 Digital Signal Processor User's Manual" Texas Instruments Japan Ltd. (1986-11) P. 2-1 to 2-18, 6-1 to 6-6

Claims (3)

[Claims] 1. A processor mainly provided with a writable instruction memory for storing instruction words for instructing various internal operations, which mainly performs signal processing, and a pause of the processor operation.
An instruction from the host processor in a signal processing device comprising means for instructing restart, an instruction memory storing an instruction word to be written in the writable instruction memory, and a host processor connected to them for controlling them. Means for temporarily stopping the operation of the processor, reading an instruction word from the instruction memory, writing the instruction word in the writable instruction memory, and determining means for determining whether a predetermined instruction word has been written in the writable instruction memory And a host processor that controls the operation of the processor based on the determination result of the determination means. 2. When an instruction word is read from the instruction memory and written in the writable instruction memory, the instruction word is read from the instruction memory according to the instruction address output from the host processor and output from the host processor. After writing to the writable instruction memory by an address and a write control signal, whether the read instruction word and the written instruction word are read from the writable instruction memory by the read control signal from the host processor and match. The signal processing apparatus according to claim 1, wherein the host processor controls the host processor so that the determination is made in the host processor, and if they do not match, the command word is written again in the writable memory. 3. An instruction word of m × n (m is an integer of 1 or more, n is an integer of 2 or more) bit width when reading the instruction word from the instruction memory and writing the instruction word to the writable instruction memory. The signal processing device according to claim 1, wherein the signal processing device is divided into m bits and read and written in n times.