JPH0628849A - Dynamic type ram - Google Patents

Abstract

PURPOSE:To allow a dynamic type cell memory to hold information with a high reliability by providing a tire circuit at a part where heat radiating condition is bad on a semiconductor substrate. CONSTITUTION:A tire circuit 4 is provided at the central part of a semiconductor chip 1 on the worst condition of the radiation of heat. When a dynamic type RAM is switched from an operating state to a data holding mode (automatic refresh mode), the part remains to be a high temperature until the end of a temperature distribution generated by the chip 1. Then, a refresh cycle corresponding to the high temperature is decided by arranging the tire circuit 4 at the pertinent part. Therefore, it is not necessary to set the refresh cycle longer than the refresh time of the memory cell arranged at an area where the radiating condition is satisfactory.

Description

Detailed Description of the Invention

[0001]

This invention relates to a dynamic RA
The present invention relates to an M (random access memory), and more particularly to a technique effective when used in an automatic refresh control circuit and a timer circuit for determining its refresh cycle.

[0002]

2. Description of the Related Art A memory cell of a dynamic RAM is
Composed of one MOSFET (insulated gate type field effect transistor, the same applies hereinafter) and one capacitor,
Information is stored depending on the presence / absence of charges held in the capacitor. Therefore, a refresh operation is required in which the charge held in the capacitor is read out, amplified, and rewritten before being lost due to the leak current. There is a dynamic RAM in which such a refresh operation is automatically performed by a built-in timer circuit. An example of such a dynamic RAM is disclosed in Japanese Patent Laid-Open No. 60-8.
There is a 3293 publication.

[0003]

Information retention time of a dynamic memory cell has temperature dependency, and at high temperature, leakage current increases and retention time becomes short. According to the experiments by the inventor of the present application, at high temperature, it becomes shorter than that at room temperature by one digit or more. However, the dynamic RA of the above publication
In M, only the memory cell portion having a large amount of leakage around the memory array is used, the change in temperature distribution due to the heat flow on the semiconductor substrate and the influence of minority carriers due to other circuits are not taken into consideration. It must be said that the control is insufficient.

An object of the present invention is to provide a dynamic RAM which realizes the optimum automatic refresh cycle setting. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a timer circuit that determines the refresh cycle of the automatic refresh control circuit is arranged in a region where heat is released slowly on the semiconductor substrate on which the dynamic RAM is formed.

[0006]

According to the above-mentioned means, since the timer circuit is provided in the portion on the semiconductor substrate where the heat dissipation condition is bad, there is no fear that the refresh time of the memory cell will be longer than it actually is, and the dynamic memory cell Can perform a highly reliable information holding operation.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a dynamic type R according to the present invention.
A schematic chip layout diagram of one embodiment of an AM is shown. In the figure, the semiconductor chip 1 is formed in a vertically long rectangle. A plurality of bonding pads 2 are formed along the upper and lower short sides of the semiconductor chip 1. The memory array 3 is arranged above and below the chip. A timer circuit 4 for refreshing is arranged in the central portion between the two memory arrays 3.

In the dynamic RAM, an address selection circuit for selecting a memory cell formed in the memory array 3, an address buffer for capturing an address signal, a data input buffer for capturing write data, and a memory cell. A main amplifier and a data output buffer for amplifying a read signal from the CPU, a control circuit for receiving a control signal and generating various timing signals necessary for the operation of the internal circuit, and the like are required. It should be understood to be included. Further, the automatic refresh control circuit may be included in the timer circuit 4 or may be included in the control circuit.

[0009] Actually, a known dynamic RA
Like M, the input / output circuits such as the address buffer, the data input buffer, and the data output buffer are arranged close to the bonding pads as described above, and the address decoder, word line driver, column switch circuit, data input / output line, etc. A sense amplifier and a precharge circuit are connected to complementary data lines which are arranged at a predetermined position adjacent to the memory array and which constitute the memory array. In the shared sense amplifier type, the sense amplifier is not directly connected to the complementary data line, but the selection switch M.
It is selectively connected to the left and right complementary data lines via the OSFET.

The timer circuit 4 is arranged in the central portion of the semiconductor chip 1 between the memory arrays 3 as in this embodiment for the following reason. In a semiconductor package having no heat radiation fin, the heat generated in the semiconductor chip mainly flows from the bonding pad to the bonding wire and the lead frame (lead extraction pin). Therefore, in the operating semiconductor integrated circuit device, the temperature of the circuit element that is the heat generation source is high,
The temperature gets lower as it gets closer to the bonding pad.

When the dynamic RAM enters the data holding mode (automatic refresh mode) from the above operating state, the heat generated in the semiconductor chip 1 flows toward the bonding pad and a temperature gradient is generated. Therefore, without considering such a temperature gradient, for example, as shown in FIG. 6, if the timer circuit 4 is arranged at a position near the bonding pad 2 on the periphery of the chip, a relatively low temperature is obtained according to the temperature gradient. As a result, the timer circuit 4 is activated, and there is a possibility that the time is set to be one digit longer than the refresh time of the memory cell that operates in a high temperature such as the central portion.

In the embodiment shown in FIG. 1, the timer circuit 4 is arranged in the central portion of the semiconductor chip 1 which has the worst heat dissipation conditions. This portion is an area where the temperature of the dynamic RAM remains high until the end of the temperature distribution generated in the semiconductor chip 1 when the dynamic RAM enters the data retention mode (automatic refresh mode), and the timer circuit 4 is provided there.
Are arranged so that the refresh cycle corresponding to this high temperature is determined. Therefore, the timer circuit 4 never sets a time longer than the ability of the refresh time of the memory cells arranged in the region having better heat dissipation conditions.

In FIG. 1, the position where the timer circuit 4 is shown does not mean that the timer circuit is entirely formed there. This means that the timer circuit may be present at the position indicated by block 4. That is, the timer circuit itself is basically a MOSF that performs charge-up with a capacitor like a dynamic memory cell.
This is because it can be formed by a relatively simple circuit that is composed of ET and that is composed of voltage detection means for detecting the holding voltage of the capacitor. However, this dynamic memory cell has an element structure in which the capacitance of the capacitor is equivalently reduced and the charge retention time can be shortened.

FIG. 2 is a schematic chip layout diagram of another embodiment of the dynamic RAM according to the present invention. In the figure, the semiconductor chip 1 is formed in a vertically long rectangle. In this embodiment, four of the semiconductor chips 1 are used.
A plurality of bonding pads 2 are formed along one side. The memory array 3 is arranged above and below the chip. When the bonding pads 2 are arranged along the four sides in this manner, the left and right bonding pads 2 are arranged.
A timer circuit 4 for refreshing is arranged in a relatively narrow range in the central portion of the semiconductor chip 1 away from the. With this configuration, the timer circuit 4 does not set the time longer than the ability of the refresh time of the memory cells arranged in the region where the heat dissipation is better than the above, similarly to the above.

FIG. 3 is a schematic chip layout diagram of another embodiment of the dynamic RAM according to the present invention. In the figure, the semiconductor chip 1 is formed in a vertically long rectangle. In this embodiment, the bonding pad 2 is formed at the vertical center of the semiconductor chip 1. When the bonding pad 2 is arranged at the center of the semiconductor chip 1 as described above, the LOC (lead-on-chip) technique is used.

In the LOC, the semiconductor chip forming the dynamic RAM is bonded to the lower side of the lead with an adhesive through an insulating film. The tip of each of these leads is connected to a bonding pad 2 vertically arranged in the center of the semiconductor chip 1 by a gold wire (bonding wire). It should be noted that two power supply busbar leads for supplying the power supply voltage and the ground potential of the circuit are arranged in the central portion of the semiconductor chip 1 so as to sandwich the bonding pad, and the power supply and the ground potential are appropriately provided at a plurality of locations. The power supply impedance can be suppressed to a low level by connecting to the bonding pad of.

Although not particularly limited, the memory array 3 is
The semiconductor chip 1 is divided into four parts by the vertical center part in which the bonding pads 2 are arranged and the horizontal center part in which the timer circuit 4 is formed. When adopting the LOC structure as described above, the bonding pads 2 arranged in the vertical center are arranged.
The timer circuit 4 is formed as described above around the chip away from the chip. With this configuration, the timer circuit 4 does not set the time longer than the ability of the refresh time of the memory cells arranged in the region where the heat dissipation is better than the above, similarly to the above.

FIG. 4 is a schematic chip layout diagram of another embodiment of the dynamic RAM according to the present invention. The semiconductor chip 1 in the figure is formed in a vertically long rectangle. In this embodiment, the bonding pad 2 is formed in the vertical center portion of the semiconductor chip 1 as in FIG. When the bonding pad 2 is arranged at the center of the semiconductor chip 1 as described above, the LOC (lead-on-chip) technique is used.

The semiconductor chip 1 uses a P-type substrate,
A memory cell is composed of N-channel MOSFETs. In a memory cell using such an N-channel MOSFET, the information holding time is shortened by electrons which are minority carriers of the circuit flowing in the P-type substrate. Therefore,
The timer circuit 4 is provided close to the input / output buffer 6 and the substrate voltage generation circuit 5, which are likely to generate minority carriers, in addition to the above-mentioned location where the heat dissipation condition is bad.

That is, in this embodiment, as described above, the places where the heat dissipation conditions are bad are the left center part of the chip, the place near the substrate voltage generating circuit 5 as a circuit in which minority carriers are easily generated, and the input / output buffer 6. Of these, the timer circuit 4 is arranged in the vicinity of the output buffer.

When a plurality of timer circuits are provided at a plurality of locations as described above, the automatic refresh operation is performed using the one having the shortest cycle among them. By adopting such a configuration, the refresh cycle is determined by substantially monitoring the temperature and the minority carriers, which are factors that shorten the charge retention time of the dynamic memory cell, so that the information of the dynamic memory cell with high reliability is determined. Hold can be realized.

FIG. 5 is a block diagram showing an embodiment of the timer circuit for automatic refreshing according to the present invention. In this example, n such as RTM1-RTMn
It has a plurality of refresh timer circuits, supplies its output signal to the OR gate circuit OR to form a timing pulse φ _RTM for determining the refresh cycle, and supplies it to the reset terminal RESET of each refresh timer circuit RTM1 to RTMn. As a result, the timing pulse φ _RTM that determines the refresh cycle is the refresh timer circuits RTM1 to RTMn composed of the above plurality.
It is generated periodically by the shortest timer output.

The automatic refresh control circuit receives the timing pulse φ _RTM and generates an address counter circuit for generating a row address signal necessary for a refresh operation, and an automatic refresh mode setting to control a multiplexer to control an external circuit. Instead of the address signal, an address signal for automatic refresh formed by an address counter circuit is supplied to a row address selection circuit, a timing pulse necessary for row operation is generated, and the timer circuit is activated. The control operation is performed, and the well-known refresh control circuit itself can be used, and the description thereof is omitted.

Refresh timer circuit RTM1 of FIG.
˜RTMn is for substantially monitoring temperature and minority carriers as in the embodiment of FIG. 4, and is also applicable to the embodiments of FIGS. 1 to 3. For example, also in the embodiments shown in FIGS. 1 to 3, it is the worst when the plurality of refresh timer circuits RTM1 to RTMn are appropriately provided and the temperature gradients are not the same depending on the places where the timer circuits RTM1 to RTMn are provided. The refresh cycle can be determined according to the conditions.

The operational effects obtained from the above embodiment are as follows. That is, (1) by arranging a timer circuit that determines the refresh cycle of the automatic refresh control circuit in a region where heat is released slowly on the semiconductor substrate on which the dynamic RAM is formed, the refresh cycle has an ability of the refresh time of the memory cell. The effect that the dynamic memory cell can perform the information holding operation with high reliability can be obtained without the fear of becoming longer.

(2) By forming the timer circuit for determining the refresh cycle in a region apart from the portion where the bonding pad is formed on the semiconductor substrate, the heat generated in the semiconductor chip is mainly generated from the bonding pad to the bonding wire and the lead frame. Since it flows to the (lead lead-out pin), there is no fear that the refresh cycle becomes longer than the refresh time of the memory cell, and it is possible to cause the dynamic memory cell to perform highly reliable information holding operation. The effect of being able to be obtained is obtained.

(3) The timer circuit is constructed by utilizing the leak current of the dummy cell or the diffusion layer substantially equivalent to the memory cell, and is arranged in the vicinity of the region where the substrate current is likely to occur. Since it is possible to cope with the factor that the retention time of the dynamic memory cell is shortened by the minority carriers, it is possible to obtain the effect that the dynamic memory cell can perform a highly reliable information retention operation.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the layout of the entire dynamic RAM can adopt various embodiments.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by arranging the timer circuit that determines the refresh cycle of the automatic refresh control circuit in a region on the semiconductor substrate on which the dynamic RAM is formed, where heat is released slowly, the refresh cycle becomes longer than the refresh time of the memory cell. Therefore, it is possible to cause the dynamic memory cell to perform the information holding operation with high reliability.

[Brief description of drawings]

FIG. 1 is a schematic chip layout diagram showing an embodiment of a dynamic RAM according to the present invention.

FIG. 2 is a schematic chip layout diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 3 is a schematic chip layout diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 4 is a schematic chip layout diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 5 is a block diagram showing an embodiment of an automatic refresh timer circuit according to the present invention.

FIG. 6 is a schematic block diagram for explaining an example of a conventional dynamic RAM for explaining the present invention.

[Explanation of symbols]

1 ... Semiconductor chip, 2 ... Bonding pad, 3 ... Memory array, 4 ... Timer circuit, 5 ... Substrate voltage generating circuit,
6 ... Input / output buffer. RTM1 to RTMn ... Refresh timer circuit, OR ... OR gate circuit.

Front Page Continuation (72) Inventor Yoshihisa Koyama 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd.

Claims (4)

[Claims] 1. A dynamic RAM comprising a built-in automatic refresh control circuit and forming a timer circuit for determining a refresh cycle in a region on a semiconductor substrate where heat is released slowly. 2. A dynamic RAM comprising an automatic refresh control circuit and a timer circuit for determining a refresh cycle, which is formed in a region apart from a portion where a bonding pad is formed on a semiconductor substrate. 3. The timer circuit is configured by utilizing a leak current of a dummy memory cell cell or a diffusion layer which is substantially equivalent to a memory cell, and is arranged close to a region where a substrate current is likely to occur. The dynamic RAM according to claim 1 or 2, wherein the dynamic RAM is a memory. 4. The refresh circuit according to claim 1, wherein a plurality of the timer circuits are arranged at different positions, and the refresh cycle is determined by the timer output having the shortest cycle among the plurality of timer outputs. The dynamic RAM according to claim 2 or claim 3.