JPH06284118A - Digital signal reception circuit - Google Patents

Abstract

PURPOSE:To extend the transmission distance by suppressing jitter of a detection signal generated due to waveform distortion of a cable so as to enhance the stability of a clock extract circuit. CONSTITUTION:After a reception signal is subjected to equalization amplification by an equalization amplifier 1, the amplified signal is waveform-shaped and eye-pattern locus is made narrow by a pulse sharpner 3, a 1st comparator 7 and a 2nd comparator 8 decide a code and a clock extract device 6 is driver via a logic circuit 9. Jitter of a pulse width of a detection signal is suppressed by sharpening the pulse thereby allowing the clock extract device 6 to be operated stably against code interference caused in a long distance cable.

Description

Detailed Description of the Invention

[0001]

The present invention is used in the transmission of digital signals. The present invention relates to clock extraction from a received signal, and more particularly to a digital signal reception circuit that can improve the stability of a clock extraction circuit and extend the transmission distance.

[0002]

2. Description of the Related Art In a conventional digital signal receiving circuit, the output signal of an equalizing amplifier is directly input to a comparator for code judgment.

[0003]

In such a conventional digital signal receiving circuit, since the output of the equalizing amplifier is directly compared with the threshold value by the comparator, the bit pattern (+1, 0, -1) of the received signal is obtained. The pulse width of the binary (1, 0) signal of the comparison result fluctuates according to the random sequence of the code, and the same amount of fluctuation of the pulse width is also transmitted to the OR output of the two comparators. When it becomes large, the clock extraction circuit that receives it cannot follow the fluctuation and cannot extract the clock, and even if it can follow it, the fluctuation remains as jitter of the extracted clock and deteriorates the clock accuracy. was there.

Further, as the cable length becomes longer, the equalization amplifier cannot complete equalization, and the clock extractor cannot operate, which eventually increases the variation amount of the OR output pulse width and becomes a factor to narrow the transmission distance. Was there.

The present invention solves such a problem, and suppresses the jitter of the detection signal generated by the waveform distortion due to the cable, enhances the stability of the clock extraction circuit, and extends the transmission distance. The purpose is to provide.

[0006]

DISCLOSURE OF THE INVENTION The present invention is directed to an equalizing amplifier for equalizing and amplifying a received signal, and a first comparison for comparing the output pulse level of the equalizing amplifier with two different thresholds having different polarities. And a second comparator, a logic circuit that outputs a logical sum of outputs from the first comparator and the second comparator, and a clock that extracts and outputs a clock using the output of the logic circuit as an input And an extractor.

The equalizing amplifier is provided with a pulse sharpening device which receives the output pulse waveform of the equalizing amplifier, sharpens the output pulse waveform and outputs the sharpened output pulse waveform to the first comparator and the second comparator. , An equalizer having a frequency characteristic proportional to the square root of the frequency, an amplifier for amplifying the output of this equalizer, and the output of this amplifier is fed back to the equalizer to match the length of the cable to be equalized. It is desirable that the pulse sharpener is configured by an automatic gain controller that adjusts an amplified output, and the pulse sharpener has a grounded-emitter NPN transistor and a PNP transistor that receive the output of the equalizing amplifier as input, and these two transistors. Of two differentiating circuits connected to each collector output of and the inverting summing amplifier that inputs each output of these two differentiating circuits and performs inverting summing amplification The clock extractor includes a phase comparator that inputs the output of the logic circuit and compares phases, a low-pass filter that receives the output of the phase comparator, and an output that receives the output of the low-pass filter. Are preferably fed back to the phase comparator.

[0008]

The received signal is equalized and amplified to sharpen the output pulse waveform. The sharpened output pulse level is compared with two different thresholds, and the logical sum output is used as the input of the clock extractor.

As described above, by sharpening the equalized waveforms and then comparing the waveforms, it is possible to suppress the variation in the pulse width of the output from the comparator based on the spread of the eye pattern, and the variation is suppressed. By inputting a signal, the stability of the clock extractor is enhanced and the length of the equalized cable can be extended.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a block diagram showing the overall configuration of an embodiment of the present invention,
2 is a block diagram showing a configuration example of an equalizing amplifier in the embodiment of the present invention, FIG. 3 is a circuit diagram showing a configuration example of a pulse sharpening device in the embodiment of the present invention, and FIG. 4 is a clock extraction in the embodiment of the present invention. It is a block diagram which shows the structural example of a container.

In the embodiment of the present invention, an equalizing amplifier 1 for equalizing and amplifying a received signal, and a first comparator 7 for comparing the output pulse level of the equalizing amplifier 1 with two different thresholds having different polarities, respectively. And a second comparator 8, a logic circuit 9 for outputting a logical sum of outputs from the first comparator 7 and the second comparator 8, and a clock with the output of the logic circuit 9 as an input. Further, as a feature of the present invention, the output pulse waveform of the equalizing amplifier 1 is input, the output pulse waveform is sharpened, and the first comparator 7 and the second comparator 7 are provided. The pulse sharpening device 3 for outputting to the device 8 is provided.

The equalizing amplifier 1 is an equalizer (hereinafter referred to as √f equalizer) having a frequency characteristic proportional to the square root of the frequency.
10 and an amplifier 1 for amplifying the output of the √f equalizer 10.
1 and an AGC (automatic gain) controller 12 that feeds back the output of the amplifier 11 to the √f equalizer 10 and adjusts the amplified output according to the length of the cable to be equalized.

The pulse sharpener 3 has a grounded-emitter NPN transistor T which receives the output of the equalizing amplifier 1 as an input.
r ₁ and PNP transistor Tr ₂ , two differentiating circuits connected to the collector outputs of the two transistors Tr ₁ and Tr ₂ , and an inverting addition amplification that receives the respective outputs of the two differentiating circuits as inputs. The clock extractor 6 is composed of a summing amplifier, and the clock extractor 6 has a phase comparator 21 that receives the output of the logic circuit 9 as an input and compares the phases, a low-pass filter 22 that receives the output of the phase comparator 21, and a low-pass filter. A voltage-controlled oscillator 23 that receives the output of 22 and feeds back the output to the phase comparator 21.
Composed of and.

Next, the operation of the embodiment of the present invention thus constructed will be described.

The received signal is input from the input terminal IN, is amplified by the equalizing amplifier 1 after being compensated for the frequency characteristic and the inverse characteristic of the cable, and is guided to the pulse sharpener 3 as a pulse without intersymbol interference. The pulse sharpening device 3 is a non-linear circuit having a higher gain as the level of the pulse is higher. Therefore, the pulse passing through the pulse sharpening device 3 has a sharply changed waveform.

The first comparator 7 compares the positive threshold value (1) with the sharpened pulse level, and the second comparator 8
Compares the negative threshold value (2) with the sharpened pulse level, and outputs a binary signal "1" while the threshold value is exceeded. Therefore, when the received signal is a "+1" signal, the binary signal "1" is output from the first comparator 7, and when the received signal is a "-1" signal, the second comparator 8 outputs a binary signal. The signal "1" is output. The waveform at that time is shown in FIG.

These binary signals are input to the logic circuit 9 and output from the logic circuit 9 to the clock extractor 6. The clock extractor 6 continuously generates the clock CLK as shown in FIG. 6 in response to the input signal.

FIG. 7 shows the input and output waveforms of the comparator in the conventional example. The comparison result is obtained according to the eye pattern of the output of the equalizing amplifier 1, but the comparison result is obtained according to the spread of the eye of the eye pattern. A fluctuation occurs in the pulse width of. On the other hand, in the present invention, since the eye pattern is sharpened as shown in FIG. 5, this fluctuation range is reduced, and only a slight amount remains.

Next, the operation of each block shown in FIG. 1 will be described. First, the operation of the equalizing amplifier 1 will be described with reference to FIG.

The output of the √f equalizer 10 is amplified by the amplifier 11, and is fed back by the AGC controller 12 to control the √f equalizer 10 and adjust according to the cable length. The output level of the amplifier 11 is constant regardless of the cable length.

Next, the operation of the pulse sharpener 3 will be described with reference to FIG.

The waveform after equalization is applied to the bases of NPN transistor Tr ₁ and PNP transistor Tr ₂ whose emitters are grounded. NPN transistor Tr for positive input
₁ is closed, the collector current changes in accordance with the change in the base-emitter voltage, and the output voltage is generated from the first resistor R ₁ connected between the positive power supply and the collector. Since the relation between the base-emitter voltage of the transistor and the collector current has a diode characteristic, this circuit has a diode voltage / current conversion characteristic. That is, as the input signal voltage becomes higher, the collector current exponentially increases and the output voltage exponentially increases.

In the case of negative input, PNP transistor Tr
₂ is closed, and an output signal is generated from the second resistor R ₂ connected between the negative power source and the collector. The DC components of these two output signals are removed by the first capacitor C ₁ and the second capacitor C ₂ , and the operational amplifier 13, the third resistor R ₃ , the fourth resistor R ₄ , and the fifth resistor R are removed.
_It is input to the inverting addition amplifier constituted by ₅ and is output from the output terminal of the operation amplifier 13 as a pulse whose waveform is sharpened according to the diode characteristic.

Next, referring to FIG. 4, the clock extractor 6
The operation of will be described. This example shows a configuration in the case of a PLL (Phase Lock Loop).
1, a low-pass filter 22, and a feedback loop of a voltage-controlled oscillator 23, which pulls in the output 5 of the logic circuit 9 and oscillates.

Taking the phase comparator 21 which compares rising phases of two inputs as an example, as shown in FIG. 6, the output of the logic circuit 9 is jittered with respect to the output signal 14 from the voltage controlled oscillator 23. Is caused. If this jitter becomes large, it becomes impossible to operate beyond the stability limit as a feedback loop as described above, but in the present invention, this jitter is suppressed and the PLL operates stably as described above. Of course, in the present embodiment, the output clock CLK is 90 ° by the delay circuit for the sign determination.
Use after delaying. When the cable length becomes long, intersymbol interference increases in the eye pattern of the output of the equalizing amplifier 1 and the locus of the eye pattern widens, but the pulse sharpening device 3 causes the input of the first comparator 7 and the second comparator 8 to be increased. Since the spread of the eye pattern is suppressed, the fluctuation of the pulse width of the output of the first comparator 7 and the second comparator 8 is suppressed, and P
The LL operates stably even if the eye pattern deteriorates. This allows the cable length to be set longer.

[0026]

As described above, according to the present invention, the waveforms after equalization can be sharpened before the comparison, so that the fluctuation of the pulse width of the output from the comparator due to the spread of the eye pattern is suppressed. There is an effect that it can be suppressed, the stability of the clock extractor using it as input is enhanced, and the cable length can be extended.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an equalizing amplifier according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a pulse sharpening device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of a clock extractor in the embodiment of the present invention.

FIG. 5 is a diagram showing a comparator input / output waveform in the embodiment of the present invention.

FIG. 6 is a time chart of the clock extractor according to the embodiment of the present invention.

FIG. 7 is a diagram showing a comparator input / output waveform in a conventional example.

[Explanation of symbols]

 1 Equalizing Amplifier 2 Equalizing Amplifier Output 3 Pulse Sharpener 4 Pulse Sharpener Output 5 Logic Circuit Output 6 Clock Extractor 7 First Comparator 8 Second Comparator 9 Logic Circuit 10 √f Equalizer 11 Amplifier 12 AGC controller 13 Operation amplifier 14 Voltage controlled oscillator output 21 Phase comparator 22 Low pass filter 23 Voltage controlled oscillator

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[Procedure amendment]

[Submission date] June 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

The equalizing amplifier is provided with a pulse sharpening device which receives the output pulse waveform of the equalizing amplifier, sharpens the output pulse waveform and outputs the sharpened output pulse waveform to the first comparator and the second comparator. , An equalizer having a frequency characteristic proportional to the square root of the frequency, an amplifier for amplifying the output of this equalizer, and the output of this amplifier is fed back to the equalizer to match the length of the cable to be equalized. It is desirable that the pulse sharpener is configured by an automatic gain controller that adjusts an amplified output, and the pulse sharpener has a grounded-emitter NPN transistor and a PNP transistor that receive the output of the equalizing amplifier as input, and these two transistors. Load resistors (R ₁ , R ₂ ) connected to the collector output of each
And remove the DC component from each output of this load resistance
Through the capacitors (C ₁ , C ₂ )
The clock extractor is composed of an inverting addition amplifier that receives a signal as input and performs inverting addition amplification, and the clock extractor has a phase comparator that receives the output of the logic circuit as an input and a phase comparison, and an output of this phase comparator as an input. It is desirable to be configured by a low-pass filter and a voltage-controlled oscillator that receives the output of the low-pass filter as an input and feeds the output back to the phase comparator.

Claims (5)

[Claims] 1. An equalizing amplifier for equalizing and amplifying a received signal, and a first comparator and a second comparator for respectively comparing the output pulse levels of the equalizing amplifier with two different thresholds having different polarities. , A logic circuit for outputting a logical sum of outputs from the first comparator and the second comparator, and a clock extractor for extracting and outputting a clock with the output of the logic circuit as an input. Characteristic digital signal receiving circuit. 2. A pulse sharpener which receives the output pulse waveform of the equalizing amplifier, sharpens the output pulse waveform, and outputs the sharpened output pulse waveform to the first comparator and the second comparator. The described digital signal receiving circuit. 3. The equalizing amplifier has an equalizer having a frequency characteristic proportional to a square root of a frequency, an amplifier for amplifying an output of the equalizer, and an output of the amplifier is fed back to the equalizer. The digital signal receiving circuit according to claim 1, comprising an automatic gain controller that adjusts an amplified output according to the length of the cable to be equalized. 4. The pulse sharpener includes a grounded-emitter NPN transistor and a PNP transistor which receive the output of the equalizing amplifier as input, two differentiating circuits connected to respective collector outputs of the two transistors, and 2. The digital signal receiving circuit according to claim 1, wherein the digital signal receiving circuit comprises an inverting addition amplifier which receives the outputs of the two differentiating circuits and performs inverting addition amplification. 5. The clock extractor receives the output of the logic circuit as an input and compares the phases, a low-pass filter having the output of the phase comparator as an input, and the output of the low-pass filter as an input. 2. The digital signal receiving circuit according to claim 1, comprising a voltage controlled oscillator which feeds back its output to the phase comparator.