JPH06283721A - Nonvolatile memory-cell, its array device, its manufacture, and its memory circuit - Google Patents

Abstract

PURPOSE: To provide a contactless flash EPROM cell, an array and a method for fabricating a contactless flash EPROM cell. CONSTITUTION: First and second extending drain diffusion regions and a source diffusion region are formed on a semiconductor substrate along a substantially parallel line. A field oxide region is provided on the side opposite to the first and second drain diffusion regions. A floating gate and control gate word lines WL0 through WLN are formed perpendicularly to a drain-source-drain structure and two rows 13, 15 and 14, 16 of storage cell sharing a source region are set. The shared source region is connected with a virtual ground terminal through a bottom block select transistor 25. Each drain diffusion region is connected with global bit lines 17, 18 through upper block select transistors 19, 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and more particularly to a flash EPROM cell using a floating gate transistor, an array device, and a manufacturing method thereof.

[0002]

Flash EPROM is a growing field of non-volatile charge storage type semiconductor integrated circuits. These flash EPROMs have the ability to electrically erase, program, and read memory cells within the chip. The memory cells of a flash EPROM are formed using so-called floating gate transistors in which data is stored in the cells by charging or discharging the floating gate. The floating gate is made of a conductive material, typically poly-Si, is insulated from the channel of the transistor by an oxide film or other insulating thin film, and a second insulating film of the transistor. Insulated from control gates or word lines.

The act of charging the floating gate is referred to as the "program" step for flash EPROMs. This step is performed by applying a positive voltage of about 12 volts between the gate and the source and a positive voltage between the drain and the source, for example, 7 volts, which is a so-called hot voltage.・ Made by injection of electrons. The operation of discharging the floating gate is the flash EPRO.
This is called the "erase" function of M. This erase function is typically accomplished by the mechanism of an FN tunnel between the floating gate and the source of the transistor (source erase) or between the floating gate and the semiconductor substrate (channel erase). For example, the source erase effect is achieved by applying a large positive voltage from the source to the gate while floating the drain of each memory cell. This positive voltage can be as high as 12 volts.

For further details regarding the structure and function of conventional flash EPROMs, see U.S. Pat. S. You can know by patent. Mukherjee, et al., USPatent No.4,698,787 issu
ed October 6, 1987; Holler, et al., USPatent No.4,
780,423 issued October 25, 1988. Flash EPR
More advanced techniques for OM ICs are described in: Woo, et al., “A Novel Memory Cell Usin
g Flash Array Contactless EPROM (FACE) Technology
”, IEDM 1990, Published by the IEEE, Pages 91-94
And Woo, et al., “A Poly-Buffered“ FACE ”Technolo
gy for High Density Me-mories ”, 1991 SYMPOSIUM ON
A prior art example of a VLSI TECHNOLOGY, page 73-74 "contactless" array EPROM device is described below. Kazerounian, et al., “Alternate Metal Virt
ual Ground EPROM Array Im-plemented In A 0.8 μM Pr
ocess for Very High Density Applications ”, IEDM, Pu
blished by IEEE 1991, pages 11.5.1-11.5.4.

[0005]

[Problems to be Solved by the Invention] Woo, et al. And Kazero
There is growing interest in the design of contactless array non-volatile memory, as evidenced by the publication of unian, et al. The so-called contactless array is formed by an array of storage cells that are coupled to each other by buried diffusion layers, which are intermittently coupled to the metal bit lines by contacts. Only. Early flash EPROM designs, such as the Mukherjee, et al. System, required a "half" metal contact for each memory cell. Because the metal contacts occupy a considerable area in a semiconductor integrated circuit, they are a great obstacle in designing a high density memory. In addition, the device is even smaller,
Attempts to shrink the area will be limited by the metal covering the adjacent drain and source bit line contacts used to access the storage cells in the array.

The present invention has been made in view of the above,
The present invention relates to an improvement of a non-volatile memory cell composed of a floating gate transistor, and in particular, to a flash EPROM cell which can be integrated at high density, an array device for the flash EPROM cell, and a manufacturing method thereof. It is intended. Another object is to provide a memory circuit using the improved flash EPROM cell.

[0007]

SUMMARY OF THE INVENTION The present invention provides a non-volatile memory cell (flash EPROM cell) which has a unique drain-source-drain configuration in which one source diffusion layer is shared by two floating gate transistors. And the extending first and second drain diffusion regions and source diffusion regions are formed along the semiconductor substrate. Field oxide regions are formed outside the first and second drain diffusion regions. The floating gate and control gate word lines are formed orthogonally to a drain-source-drain structure formed of two columns of storage cells having a shared source region. The shared source region is coupled to the virtual ground terminal by the block select transistor below. Each drain diffusion region is coupled to the global bit line by an upper block select transistor. The cell structure according to the present invention provides a virtual ground supply coupling a plurality of column transistors to a virtual ground terminal via horizontal conductors such as drains, source and drain diffusion regions, and buried diffusion lines, Two wide area bit lines that extend substantially in parallel are used. Thus, for a cell of two transistors, only two metal contact pitches are needed.

According to another aspect of the invention, these multiple drain-source-drain structures are one large IC.
A high-density nonvolatile charge storage type semiconductor integrated circuit is obtained. This non-volatile charge storage type semiconductor integrated circuit can be divided along the block boundary by using the block select transistors in the upper and lower parts, and enables individual erasing action. Also,
The block select feature couples a single block of memory cells to a global bit line at a time. This provides an improvement over leakage current to the transistors along a given row of the array.

Thus, one memory circuit, each N
It is provided as K sub-arrays with storage cells of columns, M rows. Each storage cell in the storage cell array has a first terminal, a second terminal and a control terminal. There are multiple word lines coupled to the control terminals of the storage cells corresponding to each row. N global bit lines consisting of bit lines corresponding to each column of storage cells, and a number of each coupled to a first terminal of M storage cells in each column within each sub-array. There are local bit lines. The upper block select transistor selectively connects the local bit line in the sub-array of the storage cell to the corresponding wide area bit line in response to the sub-array select signal. In addition, a number of local virtual ground lines and means for connecting the local virtual ground lines in the sub-array to the local virtual ground terminals are included. Each of the local virtual ground lines is coupled to a second terminal of a storage cell in a column in a respective subarray. A column select transistor, coupled to the global bit line, allows selective access to the N columns of storage cells.

In addition to the memory cell and array device thereof as described above, a method of manufacturing an array of floating gate devices is provided. The first method is configured as follows. Defining a plurality of drain diffusion regions extending in the first direction; doping the drain diffusion regions; forming a tunnel insulating film on at least the semiconductor substrate major surface in a region adjacent to the drain diffusion regions; Providing a floating gate conductive material on the tunnel insulating film at least in the region adjacent to the drain diffusion region;
Forming a floating gate conductive film; exposing the extending source diffusion region in alignment with the floating gate conductive material by the floating gate conductive material formed on the main surface of the semiconductor substrate. Doping the source diffusion region; insulating layer;
Providing also source diffusion regions and exposed floating gate conductive material; and rows of multiple conductive materials for control insulating material and floating material.
Form so as to cover the gate conductive material. The second method is configured as follows: forming a tunneling insulative material over at least the extended channel region over the semiconductor substrate major surface; Providing to cover the tunnel insulating material in the existing channel region; providing control gate insulating material to cover the floating gate conductive material; source diffusion region and drain diffusion extending to the semiconductor substrate Exposing the region aligned with a floating gate conductive material; doping the drain diffusion region with a first distribution of dopant; doping the source diffusion region with a second distribution of dopant; insulating Exposed floating gate conductive material covering the source and drain diffusion regions It thereby also grown on top; and a line consisting of a large number of electrically conductive material, be formed so as to cover the control insulating material and the floating gate conductive material.

[0011]

The floating gate transistor and non-volatile memory of the present invention have several distinct features. First, the metal pitch of adjacent drain and source bit lines is relaxed by having a structure that shares the source (virtual ground) bit line. The bit line passes through the transistors 16 and the like in parallel and is coupled to one metal source line together with a metal drain contact line or a wide area bit line. This can result in a very dense core array. Second, the flash EPROM array allows sector erase to be performed and memory cell failures while the flash EPROM array is divided into subarrays while being selected by the fully decoded block select lines. Occurs only while its corresponding subarray is selected. This greatly improves the operation and reliability of the product. Third,
In the first cell type, the source side of the cell does not undergo many oxidation processes, so the end of the source junction retains very good integrity. What is more characteristic is that the source junction is not affected by dopant depletion and the thickening of the oxide edge that is typical of cells designed by the prior art. In the prior art, there is a more extensive oxidation process after source implantation. For this reason, the new cell can be expected to have a good source erasing effect. In addition, fairly high gate coupling ratios can be achieved with a unique cell layout. In the above layout, the floating gate poly-Si layer can extend over the drain and field oxide regions to significantly increase the coupling area of the control gate to the floating gate poly-Si.

According to the first manufacturing method, the source diffusion region in the cell structure is self-contained in the floating gate transistor in the adjacent transistor row.
To be aligned. Similarly, the drain diffusion region is self-aligned to the opposite isolation region of each block. Further, according to the second manufacturing method, both the drain and source diffusion regions are self-aligned with the floating gate. Thus, the drain-source-drain configuration can create a substantially uniform channel length for all memory cell transistors in the array.
The source is also made by ion implantation with a distribution of dopants that provides a graded junction, facilitating tunneling during the source erase operation.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. 1 and 2 show circuit diagrams of a flash EPROM device according to the present invention. FIG. 3 shows a block diagram of a memory circuit of a flash EPROM device according to the present invention. 4, 5, 6 and 7 are sectional views showing a method of manufacturing a flash EPROM cell according to the present invention. FIG. 8 is a plan view thereof. FIG. 1 illustrates a drain-source-drain circuit configuration (a configuration including a pair of transistors having a common source) of a flash EPROM according to the present invention. This circuit configuration has a first local bit line 10 and a second local bit line 11. The first and second local bit lines 10 and 11 are obtained by means of buried diffusion layer conductors as described below. The local virtual ground line 12 is also obtained by the buried diffusion layer. Many floating gate transistors having gates, drains and sources are coupled to local bit lines 10, 11 and local virtual ground line 12. The sources of most transistors are coupled to the local virtual ground line 12. The drain of the transistor in the first column shown at 13 is coupled to the first local bit line 10 and the drain of the transistor in the second column shown at 14 is coupled to the second local bit line 11. The gates of the floating gate transistors are coupled to word lines WL _{0 to} WL _N. still,
Here, each word line (eg, WL ₁ ) is coupled to the gates of a first column of transistors (eg, transistor 15) and a second column of transistors (eg, transistor 16). Thus, transistors 15 and 16 can be thought of as cells consisting of two transistors sharing a source diffusion layer.

The operation of charging the floating gate is called the program step of the flash EPROM cell. This allows a large positive voltage of about 12 volts between the gate and the source, and 6 between the drain and the source.
This can be done by injecting hot electrons by applying a positive voltage of Volts. floating·
The operation for discharging the gate is the flash EPR.
This is called an OM cell erase step. This is done by an FN tunneling mechanism between the floating gate and the source (source erase) or an FN tunneling mechanism between the floating gate and the semiconductor substrate (channel erase). Source erase involves grounding the gate or biasing it negatively on the order of -8 volts, with 12 volts or 8 volts on the source.
This is done by applying a positive bias on the order of volts. Channel erasure is performed by applying a negative bias to the gate and / or a positive bias to the semiconductor substrate.

As shown in FIG. 1, the first global bit line 17 and the second global bit line 18 are connected to the respective drains.
Associated with a cell having a source-drain circuit configuration. The first global bit line 17 is coupled to the source of the upper block select transistor 19 via a metal-diffusion contact 20. Similarly, the second global bit line 18 is coupled to the source of the upper block select transistor 21 via a metal-diffusion contact 22. The drains of the upper block select transistors 19, 21 are coupled to the first and second local bit lines 10 and 11, respectively. The gates of the upper block select transistors 19 and 21 have block select signals T applied to the line 23.
Controlled by BSEL.

The local virtual ground line 12 is connected to the conductor 2 via the lower block select transistor 25.
4 to a virtual ground terminal. The drain of the lower block select transistor 25 is coupled to the local virtual ground line 12. The source of the lower block select transistor 25 is coupled to the conductor 24. The gate of the lower block select transistor 25 is controlled by the lower block select signal BBSEL applied to line 26. In the system proposed by the present invention, the conductor 24
Is a conductor with a buried diffusion layer, which extends horizontally through the array to the metal-diffusion contact. This metal-diffusion contact makes contact with a vertically extending metal virtual ground bus.

The wide area bit lines 17, 18 are arranged vertically through the array to the respective column select transistors 27, 2.
It extends to 8. Transistors 27, 28 couple the select global bit line to a sense amplifier and program data circuit (not shown). Thus, the source of column select transistor 27 is coupled to global bit line 17 and is connected to column select transistor 2
The gate of 7 is supplied with the column decode signal Y ₁ and the drain of the column select transistor 27 is coupled to the conductor 29.

The many subarrays shown in FIG. 2 are made up of blocks of the flash EPROM cell shown in FIG. FIG. 2 illustrates two subarrays of the overall IC. The sub-array is sectioned along the alternate long and short dash line 50, and the sub-array 51 is located above the alternate long and short dash line 50.
A has a sub-array 51B at the bottom. The first block 52 includes bit lines (eg, bit lines 70, 7).
The second block 53 is arranged along the line 1). These memory sub-arrays are formed on the upper and lower portions of the pair of bit lines 70 and 71 by metal-diffusion contacts 5.
5, 56, 57 and 58 are common and are divided like virtual ground conductors 54A and 54B (embedded diffusion layers). Virtual ground conductors 54A, 54
B extends horizontally across the array to a virtual ground metal line 59, which is arranged vertically through metal-diffusion contacts 60A, 60B. The sub array is formed on the opposite side of the metal / virtual ground line 59 so that the adjacent sub arrays share the metal virtual ground line 59. The metal virtual ground line 59 has a virtual ground select transistor 79 controlled by the decode signal Z _N.
Coupled to array ground and erase high voltage circuitry via. The virtual ground select transistor 79 is
It can be used to isolate the array area sharing metal lines 59 from high voltage erase. Thus, the layout of the sub-array has two metal contact pitches per column of two-transistor cells for the wide area bit line and one metal contact pitch per sub-array for the metal virtual ground line 59. Pitch is needed.

In addition, the two sub-arrays shown in FIG. 2 have additional decoding at the top and bottom of them, respectively, with block select signals TBSELA, TBSEL.
Being provided by B, BBSELA and BBSELB, the word line signals can be shared. In one proposed system, each subarray consists of 8 blocks, consisting of 32 pairs of transistor cells and word lines in each column, 512 cell subarrays, for a total of 16 global bits. There are lines and 32 word lines. As will be appreciated, the device according to the invention can form a sector flash EPROM array. this is,
Advantageously, during a read, program or erase cycle, the sources and drains of the transistors in the unselected sub-array are isolated from the currents and voltages applied to the bit lines and virtual ground lines. Thus, during the read operation,
The read operation is improved because the leakage current from the unselected sub-array does not contribute to the current applied to the bit line.
During programming and erasing operations, the high voltage on the virtual ground lines and the bit lines are isolated from the unselected blocks.
This allows a sector erase operation. The lower block select transistor (eg, transistor 6
5A, 65B) may not be necessary in some implementations. Also, these block select transistors can share a lower block select signal with an adjacent sub-array, as illustrated at the bottom with respect to FIG. Alternatively, the lower block select transistor (eg,
65A, 65B) can replace the adjacent virtual ground terminals 60A, 60B by a single isolation transistor.

FIG. 3 shows a flash EPRO according to the present invention.
It is a block diagram which shows the outline of MIC. Flash EP
The ROMIC has the memory array 100 shown in FIG. 2, and a large number of extra cells 101 are provided in the system so that a damaged memory array can be replaced.
In addition, this circuit includes a number of reference cells 102, a sense amplifier, a program data input circuit, a block 103 which includes array ground and erase high voltage circuits, and a block 1 which includes a word line and a block select decoder.
04, and a block 105 containing a column decoder and a virtual ground decoder. The reference cell 102 is
Coupled to the sense amplifier of block 103 to count changes in channel length, such as those that occur during fabrication or reflected in the voltage and current applied to the bit line being read. The reference cell 102 can also be used to generate programming and erase voltages. This redundant cell arrangement was made possible by the split construction of the flash EPROM array as discussed above. The word line and block select decoder 104 row and virtual ground decoder 105 can be programmed after testing the redundant cells to replace dead cells in the memory array 100. In addition, the circuit has a mode control circuit 106 for controlling the voltages of the virtual ground, drain and word lines used during erase, program and read operations and various operations.

A method of fabricating the flash EPROM cell according to the present invention and the cell used in the above-described circuit will be described with reference to FIGS. 4A to 4D and 5A to 5D, and FIGS.
D and a cross section according to Figures 7A to 7C. FIG. 8 is a plan view thereof. An example of the first cell type is illustrated in FIGS. 4A-4D and 5A-5D. The manufacturing process of the cell shown in this sectional view shows the outline thereof. FIG. 4A illustrates the process of the first step. To make an N-channel cell, a P ⁻ -type Si semiconductor substrate 100 is prepared and a relatively thick field oxide region 10 grown vertically in a well-known LOCOS field oxidation process.
1 and 102 are generated. Further, a thin oxide film 103 is formed on the main surface of the semiconductor substrate around the field oxides 101 and 102. In the next step, as shown in FIG. 4B, a photoresist mask 104 is deposited between the field oxides 101, 102, the mask being essentially parallel to the field oxide regions 101, 102. Extends along. As a result, the drain diffusion region is covered with the field oxide 101 and the photoresist mask 1.
04 and between the field oxide 102 and the photoresist mask 104. An N-type dopant is ion-implanted into the semiconductor substrate 100 through the thin oxide film 103, as shown schematically by the arrow. Thus, the drain diffusion region is self-aligned with the isolation field oxides 101 and 102.

In the next step, the photoresist mask 104 is removed and the N-type dopant implanted in the semiconductor substrate 100 is annealed to form the local bit lines 105 and 106, as shown in FIG. 4C. And activate. In addition, drain oxides 107 and 108 are formed so as to cover the diffusion bit lines 105 and 106. Figure 4
D illustrates the next step in cell fabrication. In particular,
The thin oxide 103 is removed by a blank wet etch, and a tunnel oxide 110 is created between the drain diffusion bit lines 105,106. The thickness of the tunnel oxide film 110 is about 100 angstroms in the system of this embodiment. However, the tunnel oxide 110 is about 120 in a flash EPROM cell.
It is less than Angstrom. Thicker oxide film is UV
It may be used in non-volatile cells such as EPROM cells, but tunnel oxides for erase operations do not use such thick oxides. The oxide films 107, 108 above the bit lines 105, 106 by the buried diffusion layer are
This step is about 1000 angstroms thick.

The next step shown in FIG. 5A is poly S.
This is a step of depositing the first layer of the i layer 111 and doping an impurity element to make the poly-Si a conductor. Then, the oxide / nitride / oxide (ONO) layer 112 is formed as the first layer.
Is formed to provide a control gate insulating film on the poly-Si layer 111. The poly-Si layer 111 layer by this step is about 1500 angstroms thick and the ONO layer is about 250 angstroms thick. In FIG. 5B, self-aligned source diffusion regions are defined using a photomask process. After the photo mask process, poly-Si layer 111 and O
The NO insulating layer 112 is etched to expose the source diffusion region. In addition, the floating gate poly-Si layer 111 and the ONO layer 112 are floating.
Etched to define the width of the gate. Thus, one of the etched poly-Si layers 111 defines the source diffusion region and the other defines the width of the floating gate. In this embodiment, the latter is located on top of field oxide region 101 or 102. afterwards,
Source diffusion region, N ⁺ / N extending parallel to the drain diffusion region 105, 106 ^- N-type dopant to form a double diffused diffusion region is ion-implanted. The dopant used is a combination of phosphorus and arsenic to form the double diffusion.

The photoresist is removed and the semiconductor substrate is annealed, as shown in FIG. 5C. N ⁺
And by diffusing and annealing the N ^- dopant,
The source diffusion region 115 is activated. Also, a source oxide film 116 is formed and an oxide film 117 separates the floating gate from the word line poly-Si layer that is subsequently defined.
It is generated along the side surface of the i layer 111. FIG. 5D illustrates the next step in the process of manufacturing a flash EPROM cell. This involves depositing a second poly layer 118 and using a photomask process to define the word lines. In the photomask process, the word line defining etch is continued to the floating gate poly-Si layer 111 to define the floating gate of each transistor. Word line 118 is approximately 4,500 angstroms thick. Finally, a passivation and metallization layer (not shown) is deposited on top of the cell.

As shown in FIG. 5D, the first transistor has a drain diffusion line 105 and a source diffusion line 11.
5, a cell structure is obtained in which the second transistor is formed between the drain diffusion line 106 and the source diffusion line 115, respectively. The floating gate is from the source diffusion line 115 to the drain diffusion line 1
05 and across field oxide 101. In this embodiment, these floating
The gate oxide is about 2.4 microns long and 0.8 microns wide. On the other hand, the source oxide film 11 is formed from one end of the drain oxide film 107 above the transistor.
6, the width of the tunnel oxide film 110 up to one end is about 1.
2 microns. A redundant region over the drain diffusion line 105 and the field oxide 102 is used to increase the coupling ratio by the floating gate to a magnitude greater than about 50%. Because the ONO layer is about 250 Å thick and the tunnel oxide is about 100 Å thick, the coupling ratio can be improved by increasing the area of the floating gate. Because it must be. Alternatively, the ONO layer may be made thinner to reduce the area required for the floating gate. As can be seen, the source diffusion is done in a step independent of the drain diffusion, and is implanted with a dopant with a different distribution to create a graded junction in the channel of each transistor to facilitate the source erase function. To be done. No graded junctions and source diffusions are required for channel erase or UV erase type floating gates.

Next, FIGS. 6A to 6D and FIGS. 7A to 7
C shows in cross-section a second cell type embodiment according to the invention. As shown in FIG. 6A, the first
The step is to produce field oxide 201, 202 as described in FIG. 4A. Further, an unnecessary oxide film is formed, and this oxide film is removed to prepare the semiconductor substrate 200 for forming the tunnel oxide film. As shown in FIG. 6B, a thin tunnel oxide film 203 is formed to a thickness of about 100 Å. In the next step of FIG. 6C, a poly-Si layer is deposited and dope is doped, and the coupling ratio is about 50.
%, 120 angstrom thick O
The NO layer 205 is generated. Thicker oxide film 203 and ONO layer 205 are used in the UV-EPROM cell.
In FIG. 6D, a photomask process is used to define the floating gate and source and drain diffusions of the N ⁺ layer. Thus, photomask layers 206 and 207 are defined to protect the floating gate region. A layer of poly-Si layer 204 and a layer of ONO 205 are etched except where covered by masks 206 and 207, exposing the drain, source and drain regions. Next, an N-type dopant is ion-implanted into the exposed area as shown by arrow 208. These regions are formed by self-alignment with the floating gate and field isolation regions. For flash EPROM arrays,
The next step is illustrated in FIG. 7A. According to this step, the photo mask process uses masks 210, 211 that cover the drain and isolation regions. In this step, the N-type dopant is added to the arrow 212.
The source region is ion-implanted as shown by
It will have N ⁺ and N ⁻ type dopants to form a graded junction. The steps in FIG. 7A are UV
It can be omitted in the description of the method for manufacturing the erase-type EPROM cell.

As shown in FIG. 7B, the semiconductor substrate is annealed to activate the dopants and defines drain diffusion regions 213 and 214 as well as source diffusion region 215. In addition, the drain oxide film 216,
The oxide film 217 and the source oxide film 218 are formed so as to cover the side surfaces of the floating gate poly-Si. Finally, as shown in Figure 7C, a second poly-Si layer 219 is deposited and etched to define the transistor. In this embodiment, ONO
The sandwich 205 has a tunnel oxide film thickness of ± 20.
%, The coupling ratio is high (in the range of about 40% to 60%, preferably about 50%), and the floating gate extended on the drain and field isolation regions is used. No need. Finally, passivation and metallization layers (not shown) are deposited on the device of Figure 7C. Thus, as seen in FIG. 7C, the cell structure according to the second type is such that the first transistor has a buried drain diffusion region 2
The second transistor is formed between the embedded drain diffusion region 214 and the embedded source diffusion region 215 between the embedded drain diffusion region 214 and the embedded source diffusion region 215. Each transistor has a floating gate made of the first poly-Si layer 204. floating·
The gate is insulated from the channel region of each transistor by the tunnel oxide film 203, and the ONO layer 205 is isolated from the control gate in the word line / poly-Si layer 219.
Is insulated by. The ONO layer 205 has a tunnel oxide film 203 with a thickness of about ± 2 in order to ensure a sufficiently high coupling ratio for flash EPROM operation.
The thickness is within the range of 0%.

Since the ONO layer 205 in the cell types shown in FIGS. 6A-6D and 7A-7C is sufficiently thin, the surface area of the floating gate is shown in FIGS. 4A-4D. It need not extend as it did in the first type of cell structure illustrated in FIGS. 5A-5D. Furthermore, in the structure shown in FIG. 7C, all of the first and second drain diffusion regions 213 and 214 and the source diffusion region 215 are formed in the first poly-Si layer 2.
04 and the ONO insulating layer 205 are self-aligned with the floating gate structure. This demonstrates that the channel lengths of each transistor are substantially equal.

FIG. 8 shows the EPROM shown in FIGS. 4 and 5.
A sub-array layout of the cell IC is shown. Obviously, this arrangement is also substantially the same for the cell shown in FIG. 7C except for the size of the floating gate. As seen in FIG. 8, the IC has a number of isolation regions 300 that extend vertically through the sub-array.
Through 302. These isolation regions correspond to the thick oxide films 101 and 102 shown in FIG. 5D. These field oxides 300, 301 define isolation regions with a region 303 between them. In the element-isolated region, there are strip-shaped first buried diffusion lines 304 and second buried diffusion lines 305 corresponding to the diffusion lines 105 and 106 in FIG. 5D. There is a source diffusion line 306 corresponding to the diffusion line 115 in FIG. 5D between the strip-shaped buried diffusion lines. A number of word lines 307-309 traverse the isolation regions that define the control gates of the floating gate transistors of the array device. A floating gate (see, eg, notch 310) covers the semiconductor substrate between the tunnel oxide and the respective word line.

The top select transistor is a buried diffusion line 304 defined by a local bit line,
Associated with each of the 305. For example, the block select transistor in the cutout area 311 is
It has a drain 312 coupled to the extending buried diffusion region 304 and a source 313 coupled to a metal line (not shown) by a metal-diffusion contact 314. The metal lines extend parallel to the isolation region 300 above the sub-array. Similarly, the second buried diffusion line 305 is coupled to the drain 315 of the upper select transistor. This transistor is coupled to metal-diffusion contact 317,
And having a source 316 coupled through the contact to a vertically extending metal line (not shown) that acts as a wide area bit line. The gate of the upper block select transistor is set by the upper select word line 318 which extends horizontally across the array. The upper block select transistor coupling the local bit line 304 to the metal-diffusion contact 314 is connected to the block select transistor coupling the local bit line 305 to the metal-diffusion contact 317.
Separated from the transistor by field oxide region 319. In this way, the transistors in each column can be independently selected for read and program operations.

Local source diffusion 306 is coupled to the underlying block select transistor having a buried diffusion source 320 and a buried diffusion drain 321. The buried diffusion drain is a conductor consisting of a strip of buried diffusion layer that extends horizontally across the array to the metal-diffusion contact 322. The metal-diffusion contacts, in turn, are coupled to metal lines 323 that provide virtual ground voltage to the array. The lower block select transistor is controlled by the select line 324 in the poly-Si layer. As can be appreciated, the select lines 324 of the poly-Si layer are shared with the subarray depicted in the figure and the subarray 325 below the figure.
Subarray 325 has a block select source region 326 that shares a buried diffused drain 321 that connects the subarray to a virtual ground bus. Thus, the bottom block select signal of the poly-Si layer traverses the wide structure 324 extending from the source region 320 of the first sub-array to the second sub-array 325.
Within the source region 326. In this manner, the bottom block select signal acts so that the local virtual ground diffusion 306 can act on the subarrays on either side of the drain diffusion region 321.

Of course, other implementations may be implemented in which the bottom block select signal is individually controlled for each subarray that requires a separate block select signal for word line 324. In the above example ,. Also,
The bottom block select transistors can be implemented as one for each buried diffusion line in a manner similar to the top block select transistors. In another implementation, the lower block select transistor controls the metal-diffusion contacts 32 that control multiple local virtual ground bit lines.
It can be replaced by a conductor with one isolated transistor near two. Element isolation region For example, the element isolation region 301 periodically extends through the lower block select source region 320 and the drain region 321.
Then, the block select transistors under the adjacent sub-arrays are separated. As can be seen, the virtual ground metal bus 323 extends vertically across the figure. The bus 323 is a metal-diffusion contact 322.
Is connected to the lower block select transistor.

The device isolation region 301 separates the subarray on both sides of the field oxide 301 by isolating the underlying block select transistor.
As shown in FIG. 6, the sub-array thus has four (as an example) columns of transistors 350, 351, 352, 353, which generally share the lower block select transistors in region 354. A preferred system has 16 columns of transistors (2
8 blocks with individual transistor cells). The transistors formed by diffusion regions 304, 305 will thus be in a sub-array separate from the transistors in columns 350 and 351. The transistors to the right of virtual ground metal line 323 will also be in separate subarrays. The lower block select transistor that was shared is
It is controlled by the block signal applied to the line 324, so that four sub-arrays (two on each side of the metal 324).
Have their source diffusion regions, eg, 359, coupled to a virtual ground bus 323 responsive to the signal on line 324. This results in sector erase for four subarrays at a time.

In the present invention, the N channel of the flash EPROM array has been described, but it is obvious that the P channel can be easily realized. Further, the embodiments and the description thereof disclosed in the present invention are for explaining the present invention, and do not disclose all the gist of the present invention. Therefore, the present invention is not limited to the disclosed embodiments, which were chosen in order to best explain the principles of the invention and its practical application, and to numerous modi? Cations. It is clear that cations and variations can be made by experienced technicians.

[0035]

As described above, the nonvolatile memory of the present invention
The cell and array device is a new floating gate
A flash EPROM cell including a transistor, an array device thereof, and a memory circuit thereof can be provided, and the main features thereof are as follows. 1. Two adjacent local drain bit lines share one source bit line and one metal source
The bit lines are formed in parallel with all sub-arrays of the cell, and the contactless structure has an effect of obtaining a very dense core array of the nonvolatile memory. 2. Sector erase is a floating
There are advantages that can be realized by using a partitionable array device composed of gate transistors. 3. A nonvolatile memory cell using the novel floating gate transistor of the present invention provides a flash memory array having high operation and high reliability,
Also, there is an advantage that a memory circuit can be obtained.

Further, the non-volatile memory cell, array device of the present invention can provide a flash EPROM cell, and the device can be adapted to an array of various memory circuits. Thus, the storage cells in the memory array are ROM, PROM, EPROM, UV erase E
Clearly, a PROM, or other EPROM, could be applied. Furthermore, the flash EPRO disclosed in the present application
It goes without saying that M is for the purpose of the source erase operation and can be adapted to the channel erase operation if desired.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a nonvolatile memory cell according to the present invention.

FIG. 2 is a schematic diagram of an array device including nonvolatile memory cells according to the present invention, and is a circuit diagram showing two sub-arrays.

FIG. 3 is a block diagram showing an embodiment of a semiconductor integrated circuit using a nonvolatile memory cell according to the present invention.

4A to 4D illustrate a method of manufacturing a non-volatile memory cell according to an embodiment of the present invention. It is a figure.

5A to 5D are diagrams of FIGS. 4A to 4D.
FIG. 6 is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory cell, which is continued from FIG.

6A to 6D illustrate a manufacturing method of another embodiment of a non-volatile memory cell along a word line of an array device with the non-volatile memory cell according to the present invention. FIG.

7A to 7C are diagrams of FIGS. 6A to 6D.
FIG. 6 is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory cell, which is continued from FIG.

8A to 4D and FIGS. 5A to 5D.
FIG. 6 is a plan view of an array device including a nonvolatile memory cell obtained by the manufacturing method of FIG.

[Explanation of symbols]

10 First Local Bit Line 11 Second Local Bit Line 12 Local Virtual Ground Line 13, 15 First Row Transistor 14, 16 Second Row Transistor 17 First Wide Area Bit Line 18 Second Wide Area Bit Line 19 , 21 Upper block select transistor 20, 22 Metal-diffusion contact 23, 26 Line 24, 29 Conductor 25 Lower block select transistor 27, 28 Column select transistor WL _{0 to} WL _N Word line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 16/04 16/06 H01L 27/115 6741-5L G11C 17/00 530 B 7210-4M H01L 27 / 10 434 (72) Inventor Hayashi Tenraku United States California 95104, Santa Clara, Capertino, Madera Live 10501 (72) Inventor State United States California 94087, Santa Clara, Saniever, Martin Avenue 1640

Claims (93)

[Claims] 1. A semiconductor substrate of a first conductivity type, a contactless drain diffusion region of a second conductivity type extending in the first direction in the semiconductor substrate, extending in the first direction in the semiconductor substrate, A second conductivity type contactless source diffusion region having a distribution of dopants that provides a graded channel junction at a location spaced from the drain diffusion region to form a channel region between the source and drain diffusion regions; Region, a first insulating layer formed on the main surface of the semiconductor substrate in which the source and drain diffusion regions are formed, and a large number of floating gate electrodes covering the first insulating layer formed in the channel region A second insulating layer formed on the main surfaces of the plurality of floating gate electrodes, and a second insulating layer above each floating gate electrode. A floating gate transistor array comprising a number of control gate electrodes covering a layer and extending in a second direction across the source and drain diffusion regions. 2. A comparatively in contact with the first insulating layer, adjacent to the drain diffusion region, extending in the first direction, and separating the drain diffusion region from other constituents of the semiconductor substrate. A floating gate transistor array as claimed in claim 1 including a thick insulating region. 3. The thick insulating region extends to a sufficient depth into the semiconductor substrate to prevent a parasitic channel between the drain diffusion region and other components in the semiconductor substrate. A floating gate transistor array according to claim 2 characterized. 4. The source diffusion region includes a relatively shallow region doped with arsenic to form a graded channel junction and a relatively deep region doped with phosphorus. A floating gate transistor array as claimed in claim 1. 5. The floating gate transistor has a capacitive coupling ratio, a channel region,
A capacitive coupling ratio is increased by a floating gate electrode extending below a control gate electrode covering a drain diffusion region and a relatively thick insulating region. The floating gate transistor array according to item 1. 6. The floating gate transistor has a capacitive coupling ratio, the first insulating layer has a first thickness over a channel region for an FN tunnel, and The second insulating layer has a coupling ratio of about 40.
The floating gate transistor array of claim 1 having a second thickness overlying the floating gate electrode to be in the range of 50% to 50%. 7. The first thickness is less than or equal to about 120 Å and the second thickness is ± 20% of the first thickness.
7. A floating gate transistor array as claimed in claim 6, characterized in that 8. The control electrode lower portion in which the floating gate electrode is substantially equal to the first main surface adjacent to the first insulating layer holding the channel surface region on the channel region and the channel electrode region. 7. A floating gate transistor array according to claim 6 having a second major surface adjacent to a second insulating layer carrying a control surface region of the. 9. A bit line conductor, a first channel terminal coupled to the drain diffusion region, and a second channel terminal coupled to the bit line conductor.
A block select transistor having a terminal and a gate electrode supplied with a block select signal, and means for applying a source potential to the source diffusion region, the bit line conductor being coupled to the source diffusion region. 2. A floating gate transistor array as claimed in claim 1 including column select means coupled to and selectively capable of being a bit line conductor. 10. A first-conductivity-type semiconductor substrate, a first drain diffusion region extending in a first direction on a main surface of the semiconductor substrate, and a first direction extending on a main surface of the semiconductor substrate in a first direction. , A source diffusion region formed apart from the first drain diffusion region to form a first channel region between the source and the first drain diffusion region, and a first diffusion layer on the main surface of the semiconductor substrate. A second drain diffusion region extending in a direction and spaced from the source diffusion region to form a second channel region between the source and the second drain diffusion region; and the first and second channels. Region, the source diffusion region, a first insulating layer covering the main surface of the semiconductor substrate on which the first and second drain diffusion regions are formed, and a first insulating layer upper part covering the first channel region. A plurality of floating gate electrodes, A second plurality of second floating gate electrodes over the first insulating layer covering the second channel region; a second insulating layer covering the first and second plurality of floating gate electrodes; and a source. A shared source on a second insulating layer extending in a second direction across the first and second drain diffusion regions and covering the first and second multiple control gate electrodes. A floating gate transistor characterized by comprising a plurality of control gate conductors by forming a number of floating gate transistor pairs with diffusion regions.
Transistor array. 11. The first and second bit line conductors and a first channel coupled to the first drain diffusion region.
A first block select transistor having a terminal, a second channel terminal coupled to the first bit line conductor, and a gate electrode coupled to the block select signal; and a second drain diffusion A first channel coupled to the region
A second block select transistor having a terminal, a second channel terminal coupled to the second bit line conductor, and a gate electrode coupled to the block select signal, and coupled to the source diffusion region. Also, means for providing a source potential to the source diffusion region, and column select means for being coupled to the first and second bit line conductors to selectively provide the first and second bit line conductors. The floating gate transistor array of claim 10 including: 12. A floating gate transistor according to claim 10, wherein the first and second drain diffusion regions are contactless.
Array. 13. The first and second bit line conductors extending in the first direction and isolated from a number of control gate conductors. A floating gate transistor array according to the item. 14. A floating gate according to claim 13, wherein the first and second bit line conductors are present in an insulating region between the first and second thick insulating regions. -Transistor array. 15. Floating region according to claim 10, characterized in that the source diffusion region has a distribution of dopants which gives a graded channel junction.
Gate transistor array. 16. The source diffusion region comprises a relatively shallow region doped with arsenic and a relatively deep region doped with phosphorous to form a graded channel junction. A floating gate transistor array as claimed in claim 15. 17. Floating gates in an array
The transistor has a capacitive coupling ratio, and the floating gate electrode is below the control gate electrode that covers the channel region, the drain diffusion region, and a portion of the relatively thick insulating region. 11. Floating gate according to claim 10, characterized in that it extends in order to increase the ring ratio.
Transistor array. 18. Floating gates in an array
A transistor having a capacitive coupling ratio and a first insulating layer covering the channel region for the FN tunnel;
And a second insulating layer having a second thickness above the floating gate electrode such that the coupling ratio is greater than about 40%. Floating gate
Transistor array. 19. A patent characterized in that the first thickness is less than about 120 angstroms and the second thickness is within plus or minus 20% of the first thickness. A floating gate transistor array according to claim 18. 20. A first floating gate electrode retains a channel surface region above a channel region.
A first major surface adjacent to the insulating layer and a second major surface substantially equal to the channel surface area and adjacent to the second insulating layer holding the control surface area under the control electrode. 19. The floating gate transistor array according to claim 18, which has. 21. A semiconductor substrate of a first conductivity type, a first relatively thick insulating region formed in the semiconductor substrate, and a first insulating region spaced apart to form an isolation region in the semiconductor substrate. A second relatively thick insulating region formed in the first direction and extending in the first direction, and a first channel terminal diffusion region in the isolation region, extending in the first direction, the first and second A second channel terminal diffusion region spaced from the first channel terminal diffusion region to provide a first channel region between the first channel terminal diffusion region and the first channel terminal diffusion region. A third channel extending in the direction and spaced within the isolation region to provide a second channel region between the second and third channel terminal diffusion regions. Channel terminal diffusion region and the semiconductor Covering the plate, the first and second channel regions, the first insulating layer covering the first to third channel terminal diffusion regions, and the first insulating layer covering the first channel region. First to cover
A plurality of floating gate electrodes, a second insulating layer, and a second channel region.
A plurality of floating gate electrodes, a second insulating layer covering the first and second plurality of floating gate electrodes, and a plurality of floating gates in the isolation region having a shared second channel terminal diffusion region. Forming a gate transistor pair to cover the first and second thick insulating regions and a floating gate electrode in the first plurality and a floating gate electrode in the second plurality; To a plurality of control gate conductors extending in a second direction across each of the third channel terminal diffusion regions and covering a second insulating layer. Array. 22. First and second bit line conductors, and a first coupled to the first channel terminal diffusion region.
A first block select transistor having a second channel terminal coupled to the first bit line conductor, and a gate electrode coupled to the block select signal; First coupled to the channel terminal diffusion region
Second block select transistor having a channel terminal of the second bit line conductor, a second channel terminal coupled to the second bit line conductor, and a gate electrode coupled to the block select signal; and a second diffusion. Means for supplying a source potential to the second channel terminal diffusion region, and to the first and second bit line conductors, and selectively to the first and second bit lines. A floating gate transistor array comprising: column select means, which may be a conductor. 23. The first and second bit line conductors,
23. A floating gate transistor array as claimed in claim 22 which extends in the first direction and is insulated from a number of control gate conductors. 24. The first and second bit line conductors,
24. A floating gate transistor array according to claim 23, which is present over the isolation region between the first and second thick insulating regions. 25. The floating gate transistor of claim 21, wherein the first and second drain diffusion regions are contactless.
Array. 26. Floating region according to claim 21, characterized in that the source diffusion region has a distribution of dopants which gives a graded channel junction.
Gate transistor array. 27. The source diffusion region comprises a relatively shallow region doped with arsenic and a relatively deep region doped with phosphorus to form a graded channel junction. A floating gate transistor array as claimed in claim 26. 28. Floating gates in an array
The transistor has a capacitive coupling ratio, and
The floating gate electrode extends underneath the control gate electrode overlying the channel region, the drain diffusion region, and a portion of the relatively thick insulating region to extend the capacitive coupling ratio. 22. A floating gate transistor array according to claim 21. 29. Floating gates in an array
The transistor has a capacitive coupling ratio, and
The floating gate electrode such that the first insulating layer has a first thickness covering the channel region for the F-N tunnel and the second insulating layer has a coupling ratio in the range of about 40% to 60%. The floating gate transistor array of claim 21 having a second thickness on the top of the. 30. The first thickness is less than about 120 angstroms and the second thickness is about ± 20 of the first thickness.
Claim 2 characterized by being in the range of%.
A floating gate transistor array according to item 9. 31. A first major surface of a floating gate electrode adjacent a first insulating layer carrying a channel surface region overlying the channel region and a lower portion of the control electrode substantially equal to the channel surface region. 30. A floating gate transistor array according to claim 29, having a second major surface adjacent to a second insulating layer carrying the control surface region of. 32. A semiconductor substrate of a first conductivity type, a plurality of relatively thick insulating regions for providing a large number of isolation regions to the semiconductor substrate, the insulating regions being spaced apart from the semiconductor substrate, and extending in a first direction. , Multiple firsts in each separation area
A drain diffusion region of the first channel region extending in the first direction in each of the separated regions, each of the first channel region between the source and the first drain diffusion region in each of the separated regions. A plurality of source diffusion regions spaced apart from the first drain diffusion region, and extending in the first direction in each of the separated regions, in each of the separated regions. A number of second spaced apart from the source diffusion regions to provide a second channel region between the source and second drain diffusion regions.
A drain diffusion region, and a first insulating layer covering the semiconductor substrate, the source diffusion region, and the first and second drain diffusion regions above the first and second channel regions in the respective separated regions. A first plurality of floating gate electrodes overlying the first insulating layer above the first channel region in the plurality of isolated regions, and a second channel region in the plurality of isolated regions. A second plurality of floating gate electrodes overlying the first insulating layer, a second insulating layer overlying the first and second multiple floating gate electrodes, and overlying the second insulating layer; Each is first
In a second direction across a number of thick insulating regions, a source, and a sequence of first and second drain diffusion regions above a floating gate electrode in a second number of the plurality of floating gate electrodes. A plurality of control gate conductors extending, thereby forming, within each isolated region, a number of floating gate transistor pairs with a shared source diffusion region. Floating gate
Transistor array. 33. A number of first and second bit line conductor pairs associated with each isolation region, a first channel terminal coupled to a first drain diffusion region within each isolation region, A plurality of first channels each having a second channel terminal coupled to a pair of first bit line conductors paired with a respective isolation region and a gate electrode coupled to a block select signal. A block select transistor, a first channel terminal coupled to a second drain diffusion region in each isolated region, and a second bit line conductor paired with each isolation region Second channel terminal, a second block having a gate electrode coupled to the block selector signal, A plurality of second block select transistors consisting of rect transistors, a means for supplying a source potential to the plurality of source diffusions, coupled to the plurality of source diffusions, and a plurality of firsts. 33. The floating gate transistor array of claim 32, further comprising: and a column select means coupled to the second bit line conductor pair, the column select means optionally being a bit line conductor. 34. A plurality of bit line conductor pairs extending in the first direction and insulated from a plurality of word line conductors. Floating gate transistor array as described. 35. The floating gate of claim 34, wherein the first and second bit line conductor pairs are on respective separated regions between the thick insulating regions. -Transistor array. 36. A number of bit line conductors, word line conductors, for providing block select signals for controlling the voltage potential control, erase and read modes of the bit line conductors, word line conductors and source diffusion regions, 33. A floating gate transistor array as claimed in claim 32, further comprising means coupled to means for providing a source potential. 37. Means for providing a source potential comprises a first channel terminal coupled to a number of source diffusion regions, a second channel terminal coupled to a source potential conductor, and a block. 33. The floating gate transistor array of claim 32, comprising a source block select transistor having a gate electrode coupled to receive a select signal. 38. The floating gate transistor array of claim 37, wherein the source potential conductors are essentially parallel to the multiple bit line conductors. 39. The floating gate transistor array of claim 32, wherein the plurality of first and second drain diffusion regions are contactless. 40. The floating gate transistor array of claim 32, wherein the multiple source diffusion regions have a distribution of dopants that provides a graded channel junction. 41. The distribution of dopants in a number of source diffusion regions is such that a relatively shallow region doped with arsenic and phosphorus and a relatively deep region doped with phosphorus form a graded channel junction. 41. comprising
Array of. 42. Floating gates in an array
The transistor has a capacitive coupling ratio, and the floating gate electrode covers a portion of the channel region, the drain diffusion region, and the relatively thick insulating region,
33. A floating gate transistor array as claimed in claim 32, extending below the control gate electrode to increase the capacitive coupling ratio. 43. Floating gates in an array
The transistor has a capacitive coupling ratio and a first insulating layer covers the channel region for the FN tunnel.
And the second insulating layer has a coupling ratio of about 4
Floating to be in the range of 0% to about 60%
33. The floating gate transistor array of claim 32, wherein the floating gate transistor array covers the gate electrode and has a second thickness. 44. The method of claim 1, wherein the first thickness is less than or equal to about 120 Å and the second thickness is within ± 20% of the first thickness. 43. A floating gate transistor array according to paragraph 43. 45. A control electrode, wherein the floating gate electrode is substantially equal to the channel surface area and a first major surface adjacent to the first insulating layer covering the channel region and retaining the channel surface region. 47. A floating gate transistor according to claim 45 having a second major surface adjacent to a second insulating layer holding a covering control surface area.
Array. 46. K sub-arrays having N columns and M rows of storage cells each comprising a first cell, a second cell and a control cell in a column, and storage cells in each row. Multiple word lines coupled to the control terminals, N global bit lines, one for each column of storage cells, and M storage cells in each column, inside each sub-array. A plurality of local bit lines each coupled to the first terminal, and means for selectively coupling the local bit lines to the sub-array of storage cells to the corresponding global bit line in response to the first sub-array select signal. , Inside each sub-array, M storage cells in one adjacent column and M in another adjacent column.
A plurality of local virtual ground lines, each coupled to the second terminals of the storage cells, the second terminals of the M storage cells in each adjacent row, and the other adjacent rows in each sub-array. Multiple local virtual ground lines coupled to the M storage cells, means for connecting to the local virtual ground lines in the storage cell sub-array with virtual ground terminals, and selective access to the N columns of storage cells A memory circuit including a column select means coupled to a wide area bit line for. 47. Includes a plurality of virtual ground terminals, and virtual ground select means coupled to the plurality of virtual ground terminals for selectively accessing the virtual ground terminals connected to the sub-array. 47. The memory circuit according to claim 46, wherein: 48. Means for coupling a local virtual ground line in a sub-array of storage cells to a virtual ground terminal is coupled to a first terminal and a virtual ground terminal coupled to at least one local virtual ground line. 47. A memory circuit as claimed in claim 46, comprising a sub-array select transistor having a second terminal and a control terminal coupled to the second sub-array select signal. 49. A patent including virtual ground terminal, global bit line, sub-array select signal and means for controlling a word line to program a read and erase mode for a storage cell. The memory circuit according to claim 46. 50. The memory circuit of claim 49, wherein the erase mode comprises a source erase cycle. 51. The memory circuit of claim 49, wherein the erase mode comprises channel erase cycles. 52. The memory circuit of claim 49, wherein the erase mode comprises a UV erase cycle. 53. The memory circuit of claim 46, wherein the storage cell comprises a flash EPROM cell. 54. The memory circuit of claim 46, wherein the storage cell comprises a floating gate transistor. 55. The memory circuit according to claim 46, wherein the local bit line and the local virtual ground line are diffusion regions. 56. A number of extra storage cells, a decoder for supplying word line signals, column select signals and sub-array select signals, and N storage cells.
55. The memory circuit of claim 54 including programmable means coupled to a decoder for replacing a storage cell within the column with an extra storage cell. 57. Defining a number of drain diffusion regions extending in a first direction, doping the drain diffusion regions, and at least forming a first surface on the main surface of the semiconductor substrate in a region adjacent to the drain diffusion regions. Providing an insulating material, and providing at least a floating gate conductive material covering the first insulating material in a region adjacent to the drain diffusion region, and a control gate insulating covering the floating gate conductive material. A conductive material, exposing the extended source diffusion region by aligning the floating gate conductive substance of the semiconductor substrate with the floating gate conductive substance, and doping the source diffusion region; Isolate the source diffusion region and any exposed floating gate conductive material. A contactless floating gate memory comprising providing a layer and forming a row of multiple conductive materials overlying the control gate insulating material and the floating gate conductive material. Array device manufacturing method. 58. The step of exposing a plurality of elongated source diffusion regions is spaced from the first side to define one side of the source diffusion region and the width of the floating gate region. The second provided
Defining an extended floating gate region having sides of, and etching the floating gate conductive material such that the floating gate region overlies at least a portion of the adjacent drain diffusion region. Claim 57.
A method for manufacturing a contactless floating gate memory array device according to the above item. 59. The method of claim 58, wherein the second side of the floating gate region is defined to overlie the adjacent drain diffusion region. 60. The method of manufacturing a contactless floating gate memory array device according to claim 57, wherein the first insulating material is silicon dioxide. 61. The control gate insulating material comprises:
Claim 60, characterized by comprising ONO
A method for manufacturing a contactless floating gate memory array device according to the above item. 62. The contact of claim 57, wherein the first insulative material comprises silicon dioxide having a thickness that does not reach the floating gate material below about 120 angstroms. Method for manufacturing a less floating gate memory array device. 63. The thickness of the control gate insulating material is substantially greater than the thickness of the tunnel insulating material, wherein the first insulating material is silicon dioxide having a thickness that does not reach the floating gate conductive material. ONO
58. A contactless floating gate memory device according to claim 57.
Array device manufacturing method. 64. A contactless floating gate memory array device as claimed in claim 57, wherein the step of doping the source diffusion region sets the dopant distribution to have a graded junction. Manufacturing method. 65. Forming a large number of insulating regions extending in a first direction on a main surface of a semiconductor substrate, and forming a large number of insulating regions extending in the first direction and spaced apart from each other. Defining at least a plurality of drain diffusion regions extending in the first direction, the drain diffusion regions having one drain diffusion region inside each of the isolation regions in the plurality of isolation regions; Doping, providing a first insulating material on the semiconductor substrate at least in a region adjacent to the drain diffusion region, and floating at least in a region adjacent to the drain diffusion region to cover the first insulating material. Providing a gate conductive material, providing a control gate insulating material covering the floating gate conductive material, and expanding the source extending over the semiconductor substrate. The exposed regions by aligning the floating region with a floating gate conductive material, exposing the source diffusion region, and insulating layer covering the source diffusion region and any exposed floating gate conductive material. A method of making a floating gate memory array comprising: providing and forming a row of multiple conductive materials overlying a control gate insulating material and a floating gate conductive material. 66. The floating gate of claim 65, wherein the step of defining a number of drain diffusion regions comprises aligning one end of each drain diffusion region with a respective insulating region.・
A method for manufacturing a memory array. 67. A patent, wherein the step of defining multiple drain diffusion regions comprises defining two drain diffusion regions and two floating gate conductive material regions in each isolation region. A method of manufacturing a floating gate memory array according to claim 65. 68. The step of defining a number of drain diffusion regions aligns one end of the first drain diffusion region in each isolation region with a first insulating region to provide a second drain within the isolation region. 68. A method of manufacturing a floating gate memory array as set forth in claim 67, comprising aligning opposite ends of the diffusion region with the second insulating region. 69. The step of exposing a plurality of elongated source diffusion regions is spaced from the first side to define a width of the floating gate region and a first side defining one side of the source diffusion region. The second provided
Defining an extended floating gate region having sides of, and etching the floating gate conductive material such that the floating gate region overlies at least a portion of the adjacent drain diffusion region. Claim 65, characterized in that
A method of manufacturing a floating gate memory array according to the paragraph. 70. The second side of the floating gate region is defined over the insulating region such that the floating gate region overlies the adjacent drain diffusion region. 69. A method of manufacturing a floating gate memory array according to item 69. 71. The step of exposing a number of extended source diffusion regions, each defining a first side of one of the source diffusion regions and a width of the floating gate region. Defining two extended floating gate regions in each isolated region having a second side spaced from one side, the floating gate regions at least adjacent drain diffusion regions 69. A method of making a floating gate memory array as claimed in claim 67 including etching the floating gate conductive material so that it overlies a portion of the. 72. A second side of the floating gate region is defined over the insulating region such that the floating gate region extends over the adjacent drain diffusion region. A method of manufacturing a floating gate memory array as set forth in claim 71. 73. A method of manufacturing a floating gate memory array according to claim 65, wherein the first insulating material is silicon dioxide. 74. The control gate insulating material comprises:
Claim 65, characterized by comprising ONO
A method of manufacturing a floating gate memory array according to the paragraph. 75. The method of claim 65, wherein the first insulative material comprises silicon dioxide having a thickness that does not reach the floating gate conductive material of less than about 120 angstroms. Of manufacturing a floating gate memory array of. 76. The first insulating material is a floating material.
From silicon dioxide having a thickness that does not reach the gate conductive material, the control gate insulating material comprises ONO having a thickness substantially greater than the thickness of the tunnel insulating material. A method for manufacturing a floating gate memory array according to claim 65. 77. The method of claim 65, wherein the step of doping the source diffusion region comprises setting the dopant distribution to have a graded junction.
A method of manufacturing a floating gate memory array according to the paragraph. 78. Providing at least an insulating material on the semiconductor substrate in the extended channel region, and providing at least a floating gate conductive material covering the first insulating material in the extended channel region. Providing a control gate insulating material covering the floating gate conductive material, and exposing the source diffusion region and the drain diffusion region extending to the semiconductor substrate by aligning with the floating gate conductive material. , Doping the drain diffusion region with a dopant having a first distribution, doping the source diffusion region with a dopant having a second distribution, the source and drain diffusion regions, and any exposed floating・ Providing an insulating layer covering the gate conductive material, and controlling A floating gate characterized in that it comprises forming a number of rows of conductive material overlying the edge material and the floating gate conductive material.
Method of manufacturing gate memory array. 79. Doping the source and drain diffusion regions comprises a first implant of a first dopant into both the source and drain diffusion regions and a second implant of a second dopant into the source diffusion regions. 79. A method of manufacturing a floating gate memory array according to claim 78. 80. A method of manufacturing a floating gate memory array according to claim 78, wherein the first insulating material is silicon dioxide. 81. The control gate insulating material comprises:
Claim 78, characterized by comprising ONO
A method of manufacturing a floating gate memory array according to the paragraph. 82. The method of claim 78, wherein the first insulating material comprises silicon dioxide having a thickness that does not reach the floating gate conductive material of less than about 120 angstroms. Of manufacturing a floating gate memory array of. 83. The control gate insulating material comprises:
83. A floating gate according to claim 82, comprising ONO having a thickness between the floating gate conductive material and a row of conductive material of about 120% of 120 angstroms. -Method for manufacturing a memory array. 84. The step of doping the source and drain diffusion regions sets a first distribution of dopants in the source region that forms a graded junction and a second distribution of dopants in the drain region that forms a steeper junction. 79. A method of manufacturing a floating gate memory array according to claim 78. 85. A semiconductor substrate extending in the first direction is provided with a plurality of isolation regions spaced apart from each other, and a plurality of insulating regions extending in the first direction are formed on the semiconductor substrate; Depositing a first insulative material on at least the semiconductor substrate in a channel region extending into the isolation region; and floating gate conductivity covering the first insulative substance in at least the extended channel region. A conductive material, at least a floating gate conductive material covering the first insulating material in the channel region, and a control gate covering the floating gate conductive material. Depositing a conductive material, exposing the source and drain diffusion regions extending to the semiconductor substrate with a floating gate conductive material, and exposing the source; And doping the drain diffusion region, creating an insulating layer over the source and drain diffusion regions and any exposed floating gate conductive material, and providing a control insulating material and a floating gate conductive material. A method of manufacturing a floating gate memory array comprising forming a number of rows of conductive material overlying. 86. The step of exposing a number of source and drain diffusion regions aligns one end of each drain diffusion region with a respective insulating region and causes the second end of each drain diffusion region to have a floating gate conductivity. 86. A floating gate according to claim 85, characterized in that the floating gate
A method for manufacturing a memory array. 87. The step of defining a number of drain diffusion regions comprises defining two drain diffusion regions in each isolated region and two regions of floating gate conductive material. 86. A method of manufacturing a floating gate memory array according to claim 85. 88. The step of defining a number of drain diffusion regions aligns one end of the first drain diffusion region in each isolated region with a first insulating region and defines the interior of each isolated region. 89. A method of making a floating gate memory array according to claim 87, comprising aligning the opposite end of the second drain diffusion region with the second insulating region. 89. The method of manufacturing a floating gate memory array according to claim 85, wherein the first insulating material is silicon dioxide. 90. The control gate insulating material comprises:
Claim 85, characterized by comprising ONO
A method of manufacturing a floating gate memory array according to the paragraph. 91. The method of claim 85, wherein the first insulating material comprises silicon dioxide having a thickness that does not reach the floating gate conductive material of less than about 120 angstroms. Of manufacturing a floating gate memory array of. 92. The control gate insulating material comprises:
94. The floating of claim 91, comprising ONO having a thickness between the floating gate conductive material and a conductive material of 120 Angstroms plus or minus about 20% rows. -Method for manufacturing a gate memory array. 93. Doping the source and drain diffusion regions comprises setting a dopant distribution in the source region that forms the graded junction and a dopant distribution in the drain region that forms the steeper junction. 88. A method of manufacturing a floating gate memory array according to claim 85.