JPH0628324A - Parallel computer and compiler - Google Patents

Abstract

PURPOSE:To attain an optimum scheduling operation even when the executing time differs by the instructions by forming an instruction group with the instructions in dependent relation and then carrying out the scheduling operations for each instruction group. CONSTITUTION:An instruction scheduling part 6 of an intermediate code optimizing part 8 forms a group (instruction group) with each of instructions in dependent relation and secures the correspondence between the instruction groups that can be carried out in parallel with each other. Then, the orders of clocks are calculated for the total execution time covering the instruction issued first through the final instruction and the time when another instruction group is issued after the issue of the first instruction of each instruction group. Then, the instruction groups are noted from the first one and the presence or absence is decided for the instruction groups that can be carried out in parallel to each other (have a replaceable order of issue or the issuing time which can be carried up). If such instruction groups are recognized, such groups that can minimize the total execution time are selected and the issuing time is carried up for the noted instruction group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler that generates an object program used in a computer that processes instructions in a pipeline, a parallel computer that solves simultaneous linear equations that appear when simulating physical phenomena, and a plurality of parallel computers. The present invention relates to a parallel computer having an arithmetic element processor and performing matrix multiplication with a small memory.

[0002]

2. Description of the Related Art Conventionally, a compiler used in a computer such as a parallel computer is arranged so that an instruction sequence is executed in the shortest possible time in consideration of characteristics such as a pipeline of a target architecture. There is an optimization method called “instruction scheduling”. 26 to 3
With reference to 0, the terms used in the following description and the conventional instruction scheduling method will be briefly described.

First, the definitions and explanations of terms will be given.

Pipeline processing: A process for speeding up the overall processing by dividing the process from the reading of machine instructions to the completion of execution into several stages and executing each stage in parallel for a plurality of instructions. Wear technology.
A typical pipeline and instruction execution state are shown in FIG.
Shown in (a), (b) and (c). 30A shows a 4-stage pipeline, FIG. 30B shows a 5-stage pipeline, and FIG. 30C shows a 6-stage pipeline.

Basic block: A sequence of a series of instructions that are sequentially executed one by one from the first instruction to the last instruction. That is, an instruction sequence that does not include label definitions, branch instructions, or call instructions.

Resource: A register, memory, processor state, carry, etc.

Data dependency: Two instructions use the same resource in any of the relations of "definition"-"reference", "reference"-"definition", and "definition"-"definition". If
The two instructions are said to have a data dependency. "Definition" here is the process of setting the value, and refer to "
Is a process used in the calculation.

In interlocked pipeline processing, if the result of one instruction is used by another instruction, or if a particular resource is needed by two instructions at the same time, the other instruction will wait until the first instruction completes. The order must wait. In such a case, the hardware temporarily stops parallel execution and performs synchronous control.

A plurality of arithmetic units (an adder 31, a multiplier 32, a divider 3) having a pipeline processing system and capable of being executed in parallel.
27 (a) having a register 3) and a register 34), the program of FIG. 27 (b) is compiled into the instruction sequence of FIG. 27 (c).

The pipeline is composed of five stages shown in FIG. 26 (b) and includes load (read from memory),
store (writing to memory), add (addition), mul
Each instruction of (multiplication) executes each stage from instruction fetch to writing to register in 1 clock, div (division) instruction executes instruction execution stage (E stage) in 6 clocks, other stages execute in 1 clock I will.

In the pipeline processing, an instruction can be issued every 1 clock and each stage of the pipeline can be performed in parallel. Therefore, if there is no dependency between the instructions, the division instruction is 10 clocks and the other instructions are Execution is completed after 5 clocks.

However, in the instruction sequence of FIG. 27C, since the instruction 3 uses the operation result of the instruction 1 and the instruction 2, the instruction 3
Cannot fetch the register (R stage) after the instruction fetch (F stage) until the execution results of the instruction 1 and instruction 2 are written in the register. Therefore, an interlock occurs here. In FIG. 28A, the hatched portion shows the interlock state.

Similarly, instruction 5, instruction 3, instruction 4, and instruction 6
And the instruction 5, the instruction 8 and the instruction 7, and the instruction 9 and the instruction 8 also have a data dependency relationship, and until the execution result of the previously issued instruction is output, more specifically, the decoding of the next instruction is performed until the W stage ends. (R stage) cannot be started and interlock occurs.

When the instruction sequence of FIG. 27 (c) is executed, FIG.
As shown in (a), due to the interlock occurring between each instruction, a free state occurs in the pipeline operation unit,
This is a cause of increasing the overall execution time.

With respect to such an instruction sequence, the number of interlocks is reduced as much as possible without changing the meaning of the program, or the empty state of the pipeline operation unit is reduced as much as possible to shorten the execution time. There is a compiler optimization method called "instruction scheduling" that rearranges.

An example of a typical instruction scheduling method used in the past is PBGibbons abd SSMuchnic
k, “Efficient Instruction Scheduling for a Pipeli
ned Architecture ”, Proceedings of SIGPLAN Symposi
um on Compiler Construction, Palo Alto, CA, June 198
Introduced according to 6, pp.11-16.

(1) For an instruction in a basic block,
Create a directed directed graph. In the graph, each instruction in the basic block is used as a node, and two instructions having a dependency relationship regarding the use of resources are connected by '→'. 'a →
If b ', it indicates that "a must be executed before b".

(2) The root node (a in the above example) of the dependent directed graph is placed in the root node candidate set at the time of scheduling.

(3) The following is repeated until the candidate set becomes empty.

[3-1] The optimum node is selected from the candidate set according to the following rules.

Select an instruction that has no dependency on the last scheduled instruction.

Select an instruction that has a dependency relationship with any of the instructions in the dependency graph.

Select a product with a large number of successors.

Select the longest longest path length for the remaining instructions in the dependency graph.

[3-2] The newly scheduled instruction is removed from the candidate set and the dependency graph, and the instruction that has become the new root node on the dependency graph is added to the candidate set.

Here, the number of successors represents the number of nodes connected to the instruction of interest by "→", and the path length is the execution time required to finish executing the successor after the instruction of interest. Is represented. For example, in FIG.
In the dependency directed graph of (b), the number of successors for instruction 1 is 3, the number of successors for instruction 4 is 2, the path length of instruction 7 is 20 clocks obtained by adding the execution times of instructions 7, 8 and 9, and 5 The path length is 10 clocks. This is because the division instruction has 10 clocks and the others have 5 clocks.

The instruction sequence in FIG. 27C is a basic block because it does not include a label definition or a branch instruction. FIG. 28 shows the result obtained by performing the process (1) on this instruction sequence.
It is a dependence directed graph of (b). Based on this dependency graph, the above processes (2) and (3) are performed.

The first candidate for the root node is the instruction 1 or the instruction 2 or the instruction 7 having the longest path of 20 clocks.
However, instruction 1 and instruction 2 have 3 successors, and instruction 7
Is 2, so either instruction 1 or instruction 2 becomes the root node first. In this case, either instruction may be the root node first, and the instruction 1 is selected as an example. When [3-1] is selected for the instruction 1, the instruction 2 or the instruction 7 having the longest path length becomes a candidate, but the instruction 2 having the maximum number of successors is selected.

A similar selection is made for instruction 2. In this case, the number of successors is 2 and the maximum number is 3, 4, and 7.
Is the candidate, but the longest instruction with a path length of 20 clocks 7
Is selected.

In the same manner, by processing the instructions after the instruction 7, the instruction sequence of pattern A or pattern B shown in FIG. 29 is formed. In addition, some patterns can be created depending on how to select the instruction, such as the case where the instruction 2 is the first root node.

The instruction sequences of patterns A and B are shown in FIG.
0 (a) and (b) are executed and the execution time is 20
It is a clock. It can be seen that the execution time before instruction scheduling was 24 clocks as shown in FIG. 28 (a), while the conventional instruction scheduling reduced the execution time by 4 clocks.

However, the instruction sequence is as shown in FIG.
As shown in FIG. 9, an instruction sequence like pattern C is also conceivable. FIG. 30C shows how the pattern C is executed.

The execution time of pattern A and pattern B is 20
In contrast to the clock, the execution time of the instruction sequence of pattern C is 19 clocks, and it can be seen that the execution time is further shortened. Therefore, it can be said that the pattern C is the optimum instruction scheduling.

Here, if the interlock state is shown by the slanted lines in each of the figures in FIG. 30, no interlock occurs even if command 2 is issued next to command 1 or command 7 is issued. Further, the path length of the remaining instructions for both instruction 2 and instruction 7 is 20 clocks, which is the longest. Therefore, the instruction to be issued next to the instruction 1 is determined by the instruction 2 or the instruction 7,
By the processing of [3-1], the number of successors becomes larger, and the instruction 2 is selected first. That is, in the conventional instruction scheduling method, the instruction sequence of pattern C is not selected.

On the other hand, in a parallel computer equipped with such a compiler, a physical phenomenon is actively simulated based on a partial differential equation.

When simulating a physical phenomenon on the basis of a partial differential equation like a semiconductor device simulation on a parallel computer, the target region is divided into a grid, and the partial differential equation is discretized at grid points. Perform linearization if necessary, and solve by solving simultaneous linear equations. At this time, the coefficient matrix of the simultaneous linear equations to be solved becomes a special sparse matrix.

The iterative solution method called the conjugate gradient method with pretreatment is widely used as a solution method for solving the simultaneous linear equations. Regarding this solution, Takeshi Murata et al.,
"Supercomputer, application to scientific computing" (Maruzen, 1985).

In the preconditioned conjugate gradient method, from the viewpoint of speeding up by vectorization or parallelization, the bottleneck of speeding up is the incomplete LU decomposition which is the preprocessing and the inverse of the approximated matrices L and U. In the process of obtaining the matrix, it is a so-called forward / backward substitution process, which is a sequential process.

As a method of performing these processes at high speed, there is a method of vectorizing by utilizing the peculiarity of the matrix that appears in the simulation of the physical region divided into a lattice, and there is a method called hyperplane method. This will be described below.

For example, when simulating the two-dimensional lattice shown in FIG. 9, it is necessary to solve a simultaneous linear equation having a lower triangular matrix having a coefficient matrix as shown in FIG. In FIG. 10, (1) to (16) correspond to the grid points 1 to 16 in FIG. 9, and black circles indicate nonzero elements. This black circle indicates that the physical quantity of the grid point 5 is the grid point 1
It means that it can be calculated if the physical quantity of is obtained.

In the usual method, the solution is obtained in numerical order from the grid point 1, but in the hyperplane method 1, 2, 5, 3, 6,
The solution is obtained in the order of 9, 4, 7, 10, 13, ... This is based on the set of grid points indicated by broken lines in FIG.
This is equivalent to finding the solution in the order of (1) to (7). The calculation of the solution of the grid points on the broken line can be vectorized because there is no dependency, but conventionally, this calculation was performed by one vector processor. Further, in recent years, a parallel computer that simultaneously operates a plurality of processing element processors (PEs) and performs high-speed processing has been actively developed. Such a parallel computer has a configuration as shown in FIG. 31, for example.

In FIG. 31, PE 41 is an arithmetic element processor. PE41 is array controller ACU1
Perform the operation according to the microcode from 04. The PEs 41 are arranged in an m × n two-dimensional array by the network 103 to form a PE array.

Each PE 41 is connected to the PE 41 adjacent to each other in the vertical and horizontal directions. Also, PE41 on the right end
Is connected to the leftmost PE41 in the same row, and the uppermost PE41 is connected to the lowermost PE41 in the same column. This is a so-called torus-shaped two-dimensional lattice coupling. Each PE 41 has a data memory 42 and can perform data communication with the connected PE 41. Thereby, the data stored in the data memory 42 of another PE 41 can be used for the calculation.

Each PE 41 simultaneously performs the same processing according to the microcode sent from the ACU 44. So-called SIMD (Single Instruction Multiple Data S
tream) form parallel processing. ACU44 is PE4
In the information processing apparatus to which the control function 1 of FIG.
The instruction stored in 5 is decoded, and the decoded instruction is PE
If the instruction is for 41, a microcode for PE 41 is generated and transferred to all PEs 41. The decoded instruction is A
For data processing by CU44 itself, AC
U44 processes itself.

Here, for convenience, it is assumed that m = n, and n × n.
Consider a case where the product of n × n matrices, C = A * B, is obtained in the PE array arranged in a two-dimensional manner. The PE 41 located at the i-th row and the j-th column is represented by PE (i, j) (0 ≦ i ≦ n−1, 0 ≦ j ≦ n−1).

Each PE 41 arranges the data so as to have one operated element of the matrix as initial data. That is, PE (i, j) (0≤i≤n-1, 0≤j≤n-
1) has initial data a [i] [j] and b [i] [j]. 4x4
FIG. 32 shows how the initial data is arranged in the case of a matrix.
The product of matrices is shown in FIG.

In PE (i, j), element c [i] of matrix C
Responsible for the calculation of [j], and executes all the PEs 41 simultaneously.
The operation performed by PE (i, j) (0≤i≤n-1, 0≤j≤n-1) is as follows.

C [i] [j] = 0; k = 0 to n−1 c [i] [j] = c [i] [j] + a [i] [k] * b [k] [j ];repeat. (I) PE (i, j) has no data other than a [i] [j] and b [i] [j], so each PE (i, j) is in the same row of the PE array. From all PEs 41 a [i] [k] (0≤k≤n
-1) from all PEs 41 in the same column to b [k] [j]
(0 ≦ k ≦ n−1) needs to be transferred.

The conventional multiplication formula is executed in the procedure shown in the flowchart of FIG.

(1) First, data is transferred in the row direction. Each PE 41 simultaneously transfers its own a to the PE 41 on the right (steps 131 and 132). That is, PE (i, j) (0≤i≤n-1, 0≤j≤n-
1) transfers a [i] [j] to the PE 41 on the right. Then, a [i] [j-1] is received from the PE 41 on the left side and stored in the memory 42 (step 133).

(2) Each PE (i, j) receives the a [i] [j-1] received from the PE (i, j-1) on the left in (1),
The data is simultaneously transferred to the PE 41 on the right side. By this, PE
(I, j) (0≤i≤n-1, 0≤j≤n-1) receives a [i] [j-2] from the PE 41 on the left side and stores it in the memory 42. To do. By repeating this process n-1 times, PE (i, j) (0≤i≤n-1,0
≦ j ≦ n−1) can receive a [i] [0] to a [i] [n−1] (steps 133 to 135).

That is, all the n PEs 41 in the same row have transferred data from the other n-1 PEs 41. This is called n-to-n broadcasting. This can be done in parallel on all rows (steps 133-135).

(3) Similarly, data transfer is performed in the column direction. All PEs (i, j) (0≤i≤n-1, 0≤j
≦ n−1) receives b [0] [j] to b [n−1] [j]. That is, n to n broadcasting is performed in the column direction (steps 136 to 14).
0). The state of the data held by each PE 41 at this time is shown in FIG. 35 for the case of n = 4.

(4) Since all the data necessary for the operation have been prepared, each PE 41 simultaneously calculates the equation (I).
The result is obtained for each PE 41 (steps 141 to 14).
5).

With the PE array arranged in a two-dimensional lattice, n-to-n broadcasting in the row direction or the column direction can be performed at high speed. Transferring the same data from one of the n PEs 41 to the other n-1 units is called 1-to-n broadcasting, and the time required for 1-to-n broadcasting is one communication between adjacent PEs. It takes n-1 cycles, with the time being one cycle. On the other hand, the time required for one time of n-to-n broadcasting similarly ends in n-1 cycles.

Therefore, in the two-dimensional lattice-coupled PE array, the n: n broadcasting can transfer data more efficiently than the 1: n broadcasting. The time required for data transfer in the entire matrix multiplication is 2 (n-1) cycles.

In the matrix multiplication method based on the above n-to-n broadcasting, the data transfer is performed at high speed, but in each PE 41,
All data required for calculation will be stored in advance.
Since n pieces of data are received in the row direction and n pieces of data in the column direction, a memory amount capable of storing 2n pieces of data as shown in FIG. 35 is required. That is, a large amount of memory is required when n is large.

[0058]

As described in the prior art, in the conventional compiler, when the number of execution clocks differs depending on the instruction, an instruction having a dependency relationship with the instruction issued earlier that has a larger number of clocks. There is a problem that the execution time of the whole instruction is lengthened by delaying the issue time of the instruction or issuing an instruction with a large number of clocks that has a dependency relationship with a certain instruction later.

This is because the conventional method does not consider the execution time of all dependent instructions because the scheduling is performed based on the information for each instruction.

Generally, between instructions having a dependency relationship, the next instruction cannot start processing after register reading until the instruction issued earlier is completed, so the execution time is shortened even if issued before that. However, in the conventional compiler, even if there is a dependency instruction, it may become a candidate when selecting the next node, and there is a waste of selection, or such an instruction was selected first. To
There was also the problem that more effective orders could not be issued.

Further, in the conventional vector computer, even if the hyperplane method is used, simultaneous linear equations are solved by one processor, and therefore, in principle, it is not possible to increase the speed beyond the parallelism obtained by the vector pipeline. . Therefore, 3
There was a problem in that it was not possible to make full use of it even though there was essentially a higher degree of parallelism as in the simulation of the dimensional domain. As a solution method on a parallel computer, there is a method having a high degree of parallelism such as the SOR method, but there is a problem that the numerical stability may not be good.

Further, in the conventional parallel computer, since all the necessary data in each PE for performing the matrix multiplication is held before the calculation is started, the calculation is performed when the memory amount of each PE is small. There was a drawback that could not be executed.

The present invention solves such a problem, and an object of the first invention is to provide an instruction sequence in which the total execution time is the shortest even when the number of execution clocks differs depending on the instruction. Is to provide a compiler capable of performing instruction scheduling that minimizes the empty state of the pipeline and improves the efficiency of selecting the next instruction for an instruction that has a dependency relationship. .

A second object of the present invention is to dispose a plurality of processors in a one-dimensional or two-dimensional manner so that the hyperplane method can be calculated in parallel and simultaneous linear equations can be solved at high speed. To provide a parallel computer.

Further, a third invention is to provide a parallel computer capable of executing matrix multiplication even when the memory amount for each PE is small.

[0066]

In order to achieve the above object, the first invention comprises a plurality of arithmetic units that can be executed in parallel, and generates a target program used in a computer that processes instructions in a pipeline. A compiler that configures an instruction group for each instruction that has a dependency relationship with the instruction sequence in the basic block, and uses the instruction group as a unit to reduce the execution order of the instruction groups so that the empty state of the pipeline becomes smaller. Swap
It has an instruction scheduling unit that moves up or down.

The second invention uses a parallel computer in which a plurality of processors are one-dimensionally arranged as shown in FIG. 6 when the physical area to be simulated is two-dimensional. Each processor has a calculation means for calculating the physical data of the lattice points, a storage means for storing the calculated data,
It has a transmitting means for transmitting the stored data to the adjacent processor on the right and a receiving means for receiving the data transmitted from the adjacent processor on the left.

Alternatively, the second invention uses a parallel computer in which a plurality of processors are two-dimensionally arranged as shown in FIG. 7 when the physical area to be simulated is three-dimensional. Each processor includes calculation means for calculating data at a lattice point, storage means for storing the calculated data, transmission means for sending the stored data to a right adjacent processor and a lower adjacent processor, and a left And a receiving means for receiving data sent from the adjacent processor.

Furthermore, a third invention is a parallel processor which is composed of a plurality of arithmetic element processors arranged in a two-dimensional manner, and is a parallel computer which obtains the product of two matrices. Means for performing the same allocation of the second matrix data in the two matrices, and broadcasting the data from one arithmetic processor to another plurality of arithmetic processors among the arithmetic processors having data in the row direction of the matrix; Means for broadcasting data from one arithmetic processor to another arithmetic processor among arithmetic processors having data in the column direction of the matrix, means for controlling the number of repetitions,
The data broadcasting and the control means for controlling the arithmetic operation in the arithmetic processor are provided.

[0070]

With the above means, in the first aspect of the present invention, an instruction group is composed of instructions having a dependency relationship, and scheduling is performed for each instruction group, so that optimal scheduling is performed even when the execution time differs depending on the instruction. You can

According to the first invention, as described above,
Since scheduling is performed in units of instructions, it is possible to fix the issue time of an instruction that has a dependency relationship with one instruction, so that an instruction that has a dependency relationship is selected as a candidate for the next instruction when it has no effect. That is, the efficiency in selecting the next instruction is improved.

Further, in the first invention, the instruction groups that can be exchanged in the issuance order and the issuance time are advanced by associating the instruction groups which can be executed in parallel with each other by using parentheses or the like. Redundancy can be eliminated.

On the other hand, in the second invention, when the simulation target is two-dimensional, the one having the same y coordinate is held in the storage means of one processor. That is, one row of the grid is assigned to one processor.

The processing procedure for solution is as follows. First, the receiving means of the processor receives data from the adjacent processor on the left side, and the received data and the variable values, matrix elements and constant vector elements previously calculated by the self processor are used to calculate grid points. The variable value is calculated by the calculation means. Next, the calculation result is stored in the storage means and is sent from the transmission means to the adjacent processor on the right. This process is repeated on all processors until all variables are obtained.

However, not all the processors start this processing at the same time, and either wait or receive a processing irrelevant to the solution processing until data required for calculation is received from the adjacent processor on the left.

Here, it is considered that the calculating means solves the simultaneous linear equations Lx = b having the lower triangular matrix as a coefficient. Here, L is a lower triangular matrix, x is a variable vector, and b is a constant vector.

At this time, for example, incomplete LU decomposition (1,
When 1) is used, x [i] = (b [i]-L [i, i-1] * x [i-1]-L [i, im] * x [i-
m]) / L [i, i] is used to obtain the variable value. Incomplete LU decomposition (1,
When 2) is used, x [i] = (b [i]-L [i, i-1] * x [i-1]-L [i, im] * x [i-
m]-L [i, i-m + 1] * x [i-m + 1]) / L [i, i] is used to obtain the variable value.

Alternatively, in the second aspect of the invention, when the simulation target is three-dimensional, the receiving means receives and holds the data transmitted by the left adjacent processor and the upper adjacent processor. The calculation means calculates the variable value as in the two-dimensional case, and stores the result in the storage means. The transmitting means transmits the variable value calculated by the calculating means to the processor on the right side and the processor on the lower side.

Further, in the third invention, each arithmetic processor of the first matrix, which holds one column of data designated by the number of repetitions, has a plurality of data processors each of which holds data belonging to the same row as each column data. Each column data is transferred to the arithmetic processor in parallel at the same time. Similarly, each arithmetic processor that holds one row of data specified by the number of repetitions of the second matrix simultaneously transmits each row data to a plurality of arithmetic processors that retain data belonging to the same column as each row data. Transfer in parallel.

In each arithmetic processor, the first transferred data is transferred.
The product of two numbers of the matrix data and the transferred second data is calculated, and this product is accumulated for each repetition. The product of the matrices is obtained by repeating such an operation a predetermined number of times obtained from the size of the matrix.

[0081]

Embodiments of the present invention will be described below with reference to the drawings.

First Invention First, the first invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of an embodiment relating to the compiler of the first invention.

The compiler shown in FIG. 1 has a source program input section 2 for inputting a source program 1 and a lexical analysis section 3 for analyzing a lexical term of the input source program 1.
And a parser 4 for interpreting the grammar of the source program 1
And an intermediate code generation section 5 having an intermediate code generation section 5 for converting the source program 1 into an intermediate language program, an instruction scheduling section 6 which is the core of the first invention, and an optimization section 7 for performing other optimizations. 8 and an object code generator 9 for converting the intermediate code into the object program 11,
It is composed of a target program output unit 10 which outputs and supplies the target program 11.

The instruction scheduling unit 6 schedules the instruction sequence of the intermediate code according to the flowchart shown in FIG.

The steps of the flowchart of FIG. 2 will be described below.

Step A: For the instructions in the basic block represented by the intermediate code, a group (hereinafter simply referred to as "instruction group") is formed for each instruction having a data dependency relationship,
The instruction groups that can be executed in parallel are associated with each other. The instruction groups that can be executed in parallel can be associated with each other by using parentheses as an example.

An instruction that can be independently operated with only one instruction is 1
An instruction group consists of only instructions.

Step B: For each instruction group, the total execution time from the first issued instruction to the last finished instruction, and after the first instruction of each instruction group is issued, other instruction groups (other (Instruction belonging to the instruction group of 1) is calculated.

Step C: Focusing on the first instruction group, the processing from step D is executed for all instruction groups.

Step D: It is judged whether or not there is an instruction group that can be executed in parallel with the instruction group of interest (that is, the issuing order can be changed or the issue time can be increased) in the instruction group after the instruction group of interest. . Judgment is based on the parentheses. If yes, go to step E; if no, go to step G.

Step E: It is judged whether or not there is an instruction group that can reduce the total execution time of the two instruction groups by advancing the issue time of the instruction group obtained in step D for the instruction group of interest. To do.

Here, raising the issue time of an instruction group means that the issue time of an instruction group that can be executed in parallel with the instruction group of interest is equal to another instruction group between the execution times of the already issued instruction groups. Is moved to a time at which it is possible to issue, or the issue order of two instruction groups is exchanged.

If there is at least one instruction group whose execution time can be shortened by carrying it up, the process proceeds to step F. If the corresponding instruction group does not exist, the process proceeds to step G.

Step F: The instruction group obtained in Step E is 2
If there are two or more instruction groups, the instruction group that can shorten the total execution time of the two instruction groups is selected, the issue time for the instruction group of interest is advanced, and the process proceeds to step G.

Step G: It is judged whether or not all the instruction groups have been processed, and if they have been processed, the processing ends, and if there are unprocessed instruction groups, the processing shifts to Step H.

The program of FIG. 3A and the instruction sequence of FIG. 3B are the same as the program of FIG. 27B and the instruction sequence of FIG. 27C used in the conventional example, respectively. This embodiment will be described below with reference to the instruction sequence shown in FIG.

In the instruction scheduling unit 6, FIG.
The instruction sequence of (b) is optimized according to the flowchart of FIG. How the instruction sequence shown in FIG. 3B is optimized by the instruction scheduling unit 6 will be described below with reference to the flowchart in FIG.

(1) With respect to the instruction sequence shown in FIG. 3B, an instruction group is formed for each instruction having a dependency relationship, and an instruction group that can be executed in parallel is associated (step A). Instructions that can be independently operated with only one instruction form an instruction group with only one instruction.
As an example, FIG. 4A shows a diagram in which instruction groups that can be executed in parallel are associated with '()', and FIG. 4B shows a diagram in which each instruction group is numbered. The instruction groups that can be executed in parallel are represented by the correspondence of '()'.

In FIG. 4A, an instruction 1, an instruction 2, an instruction 4, and an instruction 7, which are surrounded by '()' with only one instruction, represent instructions which can be independently executed with only one instruction. . Also, 1 out of 3 commands, command 1, command 2, and command 3.
One instruction group (instruction group 3) is formed, and instruction group 3 and instruction 4,
5 indicates that one instruction group (instruction group 5) is configured. Similarly, the instruction group 6, the instruction group 8 and the instruction group 9 are also composed of a plurality of instructions having a dependency relationship.

(2) For each instruction group, the total execution time from the first issued instruction to the last finished instruction, and after the first instruction of each instruction group is issued, other instruction groups (other (Instruction belonging to the instruction group) is calculated at what clock time (step B). FIG. 4C shows the total execution time of each instruction group and the issuable time of the next instruction group.
Shown in.

In FIG. 4C, for example, the instruction group 3 is
Since the F stage of the instruction 3 in FIG. 28A can be delayed to the 5th clock, it is shown that the next instruction group issuable time is other than the 1st and 5th clocks.

(3) Focusing on the instruction group 1, the processing after step D is performed.

(4) An instruction group that can be executed in parallel with the instruction group 1 is searched from the instruction groups after the instruction group 2 (step D). Here, the instruction group 2 is applicable, and the process proceeds to step E.

(5) Even if the issuance time of the instruction group 2 is advanced with respect to the instruction group 1, the total execution time of the two instructions remains unchanged at 6 clocks. Since there is no instruction group whose execution time can be shortened by advancing the issue time (step E), the process moves to step G. (6) Since the processing after the instruction group 2 remains, the process proceeds to step H and the instruction group 2 is focused.

(7) A command group that can be executed in parallel with the command group 2 is searched from the command groups after the command group 3 (step D). From the correspondence of the parentheses, the instruction group 1 is the only instruction group that can be executed in parallel with the instruction group 2. However, since the instruction group 1 is not the target of replacement here, the processing shifts to steps G and H.

(8) A command group that can be executed in parallel with the command group 3 is searched from the command groups after the command group 4 (step D). Here, the instruction group 4 is applicable, and the process proceeds to step E.

(9) In this case, even if the issue time of the instruction group 4 is advanced with respect to the instruction group 3, the total execution time of the instruction groups 3 and 4 does not change. However, when the instruction group 9 is scheduled later, if the F stage of the instruction 3 is moved down by 3 clocks and the instruction group 9 is moved up by 4 clocks, the issue time of the instruction 8 in the instruction group 9 becomes equal to the issue time of the instruction 4. It will share.

Since instruction 8 has a dependency relationship with instruction 7,
Since the issue cannot be advanced, the execution time of the instruction group 9 can be shortened by advancing the issue time of the instruction 4 by one clock. Go to step F.

(10) The issue time of the instruction 4 is advanced by 1 clock, the issue time of the instruction 3 is advanced by 3 clocks, and the process shifts to steps G and H.

(11) Since the instruction group 3 is the only instruction group that can be executed in parallel with the instruction group 4, it is not a target here. Go to steps G and H.

(12) Since there is no instruction group that can be executed in parallel with the instruction group 5, the process proceeds to steps G and H.

(13) The instruction group 9 can be executed in parallel with the instruction group 6. Since there is a corresponding instruction group,
Go to step E.

(14) When the issue time of the instruction group 9 is advanced with respect to the instruction group 6, the total execution time of the two instruction groups is shortened, so that the process proceeds to step F.

(15) In step F, the total execution time is set to a higher value by either advancing the issuance time of the subsequent instruction or exchanging the issuance time of two instructions with respect to the previously issued instruction group. Select the one that can be shortened.

The total execution time of two instruction groups can be shortened more by exchanging the issue times of the two instruction groups than by issuing the instruction group 6 first and advancing the issue time of the instruction group 9. Therefore, in this step, the issue times of the two instruction groups are exchanged. Go to steps G and H.

(16) Since there is no instruction group that can be executed in parallel with the instruction group 7, the process proceeds to steps G and H.

(17) Similarly, since there is no instruction group that can be executed in parallel with the instruction group 8, the process shifts to steps G and H.

(18) The instruction group 6 that can be executed in parallel with the instruction group 9 is the instruction group 6, but since it is not the target here, the process moves to step G and all the instruction groups are processed. finish.

By the above processing, the instruction sequence of FIG. 3B is converted into the instruction sequence of FIG. 5A, the execution becomes that of FIG. 5B, and the total execution time of the instruction sequence is the instruction scheduling. It was shortened to 19 clocks from 24 clocks before execution, which is 20 in the conventional instruction scheduling method.
It can be shortened by one clock compared with the clock.

Second Invention Next, the second invention will be described with reference to FIGS.

First, a case will be described in which the area to be simulated is divided into a 4 × 4 two-dimensional lattice and the incomplete LU decomposition (1, 1) is applied.

The lower triangular matrix obtained by the incomplete LU decomposition (1,1) has the form shown in FIG. When solving a simultaneous linear equation having this lower triangular matrix as a coefficient matrix, FIG.
The dependency relationship of the variable solution is obtained as shown in. In FIG. 11, i → j indicates that the value of i is required to calculate j.

FIG. 6 shows a parallel computer for solving the simultaneous linear equations. In this parallel computer, processors (1) to (4) corresponding to the number of rows of a grid are arranged one-dimensionally. The i-th processor can transfer data to the (i + 1) -th processor.

Each processor has a memory 13 serving as its own local storage means, and a reception means, a calculation means, and a transmission means (not shown).

In order to solve the above simultaneous linear equations on this computer, first, the data of each grid point is arranged in the local memory 13 of the processor in charge of the calculation of each grid point. The first processor (1) has a grid point (1 ...
Place the data of 4). The data of the grid points (5 to 8) in the second row are arranged in the second processor (2). Similarly, the grid points (9 to 12) in the third row and the grid points (13 to 16) in the fourth row are arranged for the third and fourth processors (3) and (4).

FIG. 8 is a flow chart showing the rough operation of the parallel computer in which the data is arranged. First, the receiving means of the processor receives the data from the adjacent processor (step 91), and the variable value of the lattice point is calculated by the calculating means using the received data (step 92). Next, the calculation result is stored in the storage means and is transmitted from the transmission means to the adjacent processor (step 93). This process
Repeat until all variables for which this processor is responsible have been calculated (step 94).

The specific operation of each processor will be described below.

First, in the first stage, in the first processor,
The variable of the first grid point is calculated. The second to fourth processors do nothing. After the calculation is completed, the variable value of the first grid point is transferred to the second processor.

In the second stage, the first processor calculates the variable of the second lattice point using the variable value calculated in the first stage. At the same time, the second processor calculates the variable of the fifth lattice point. At this time, the variable value of the first grid point transferred from the first processor in the first stage is used.
After the calculation is completed, the value of the variable at the second lattice point is transferred from the first processor to the second processor, and the value of the variable at the fifth lattice point is transferred from the second processor to the third processor.

In the third stage, the first processor calculates the variable of the third lattice point using the variable value calculated in the second stage. At the same time, in the second processor, the variable of the sixth grid point,
The third processor calculates the variables of the ninth lattice point. The values of the lattice point variables calculated by the respective processors are transferred to the respective adjacent processors.

Thereafter, the same processing is performed in the seventh stage, the 16th stage.
Repeat until the variables at the grid points are calculated.

As a result of this calculation, the values of the variables of the grid on the i-th row are obtained in the local memory 13 of the i-th processor.

As can be seen from FIG. 11, the state of the calculation at this time is such that the lattice points arranged in the same row in the horizontal direction are assigned to one processor, and the lattice points arranged in the same column in the vertical direction are , Are calculated simultaneously in each processor. Overall, the calculation starts from the grid points in the left column.

The numbers (1) to (7) shown above each column indicate at what stage the variables of the lattice points on that column are calculated. Data transfer between processors is performed between lattice points having diagonal arrows. The horizontal arrows do not represent data transfers between processors.

Assuming that the time required for data transfer can be ignored, compared to the case where calculation is performed by only one processor,
The calculation time will be 7/16 = 0.44 times.

Next, for the same two-dimensional area, the incomplete L
A case where the U decomposition (1, 2) is applied will be described.

The lower triangular matrix when the incomplete LU decomposition (1,2) is used is as shown in FIG. A parallel computer used to solve simultaneous linear equations with this matrix as a coefficient is
This is the same as in the case of incomplete LU decomposition (1,1). The data of each grid point is also arranged in the same way. The solution dependency relationship is as shown in FIG.

First, in the first stage, in the first processor,
The variable of the first grid point is calculated. At this time, the second to fourth processors do nothing. After the calculation is completed, the variable value of the first grid point is transferred to the second processor and held.

In the second stage, the first processor calculates the variable of the second lattice point using the variable value calculated in the first stage. At this time, the second to fourth processors do nothing. After the calculation is completed, the calculated variable value of the second grid point is transferred to the second processor and held.

In the third stage, the first processor calculates the variable of the third lattice point using the variable value calculated in the second stage. At the same time, the second processor calculates the variable of the fifth lattice point. At this time, the variable values of the first and second lattice points calculated in the first step and the second step are used.

The third and fourth processors do nothing. After the calculation is completed, the first processor transfers and holds the variable value of the third lattice point to the second processor. The second processor transfers and holds the variable value of the fifth grid point to the third processor.

Thereafter, the same processing is repeated until the variable of the 16th lattice point is calculated by the fourth processor.

As a result of this calculation, the incomplete LU decomposition (1,
As in the case of 1), the value of the variable of the grid of the i-th row is
It is available in the local memory 13 of the processor.

As can be seen from FIG. 13, the state of the calculation at this time is that the grid points arranged in the same row in the horizontal direction are assigned to one processor, and the grid points arranged in the same column in the vertical direction are , Are calculated simultaneously in each processor. Overall, the calculation starts from the grid points in the left column.

The numbers (1) to (10) shown above each column indicate in what stage the variables of the lattice points on that column are calculated. Data transfer between processors is performed between lattice points having diagonal arrows. Two arrows are drawn for one grid point, but actually, data transfer between processors is not performed twice, but data transfer is performed immediately after the calculation result of the grid point is obtained, and the transfer destination If it is memorized by the processor, it will be possible to transfer the data only once. The horizontal arrows do not represent data transfers between processors.

Assuming that the time required for data transfer can be ignored, compared to the case where calculation is performed by only one processor,
The calculation time will be 10/16 = 0.63 times.

Next, the case where the incomplete LU decomposition (1, 1, 1) is applied when the simulation area is a three-dimensional area having a size of 3 × 3 × 3 as shown in FIG. 14 will be described. . The lower triangular matrix obtained by the incomplete LU decomposition (1,1,1) is as shown in FIG. When solving simultaneous linear equations with this lower triangular matrix in the coefficient matrix,
There is a dependency relationship of variable solution such as 6.

FIG. 7 shows a parallel computer for solving the simultaneous linear equations. In this parallel computer, 3 × 3 processors (1,1) to (3,3) are two-dimensionally arranged. The (i, j) processor can transfer data to two adjacent processors, the (i + 1, j) processor and the (i, j + 1) processor. Although not shown, each processor has a memory serving as its own local storage means, a reception means, a calculation means,
And has transmission means.

In order to solve the simultaneous linear equations described above on this computer, the data at each lattice point is arranged in the local memory of each processor as follows. That is, the y coordinate,
Data of three grid points having the same z coordinate is arranged in one processor. For example, the data of grid points 1 to 3 is
The data of the lattice points of 4 to 6 are arranged in the (1,1) processor, and the data of the lattice points of 4 to 6 are arranged in the (1,2) processor. Furthermore, 10
The data of the grid points of ~ 12 are arranged in the (2, 1) processor.

First, in the first stage, the (1,1) processor calculates the variable at the first grid point. At this time, the other processors do nothing. After the calculation is completed, the calculated variable value of the first grid point is transferred to two adjacent processors of the (1, 2) processor and the (2, 1) processor.

In the second stage, the (1,1) processor calculates the variable of the second grid point, the (1,2) processor calculates the variable of the fourth grid point, and the (2,1 ) The processor calculates the variable of the tenth grid point.

After the calculation is completed, the variable values of the lattice points calculated by the respective processors are transferred to the right and lower adjacent processors of the respective processors. That is, (1,1)
Processors are (1,2) and (2,1) processors, and (1,2) processors are (1,3) and (2,2
2) to processor, (2,1) processor to (2,1)
2) Transfer the calculation result to the (3, 1) processor.

Thereafter, similar processing is repeated until the variable of the 27th grid point is calculated in the 7th step.

As a result of the above calculation, the variable value of each grid point is
The data of each grid point is obtained on the processor in which the data is arranged.

As can be seen from FIG. 16, the calculation state at this time is such that the grid points arranged in the same row in the horizontal direction are assigned to one processor, and the grid points arranged in the same column in the vertical direction are , Are calculated simultaneously in each processor. Overall, the calculation starts from the grid points in the left column.

The numbers (1) to (7) shown above each column indicate in what stage the variables of the grid points on that column are calculated. Data transfer between processors is performed between lattice points having diagonal arrows. The horizontal arrows do not represent data transfers between processors.

Assuming that the time required for data transfer can be ignored, it is 7 compared to the case where calculation is performed by only one processor.
/27=0.26 times the calculation time is required. 40
In the case of x40x40, the calculation time of 118/64000 = 0.0018 times is required with 40x40 processors.

Although the second invention may have a small matrix for each matrix element as in the so-called couple method used in the semiconductor device simulation, it can be similarly implemented in this case.

Third Invention Finally, the third invention will be described with reference to FIGS.

FIG. 17 is a block diagram showing the configuration of an embodiment relating to the parallel computer of the third invention.

In the figure, the parallel computer of the third invention is roughly composed of an arithmetic control unit 21 and an arithmetic execution unit 22. The arithmetic control unit 21 and the arithmetic execution unit 22 are connected by a data bus 23. The arithmetic control unit 21 is connected to the instruction memory 24. The instruction memory 24 stores a program that describes a matrix multiplication procedure.

The arithmetic control unit 21 reads the instruction from the instruction memory 24 and decodes it. If the read instruction directs the operation in the operation executing unit 22, it is expanded into a microcode for PE and transferred to the operation executing unit 22 via the data bus 23.

The read instruction is used to update the loop variable, etc.
If the instruction is for processing in the arithmetic control unit 21, the processing is performed in the arithmetic control unit 21.

The operation executing section 22 is composed of a plurality of processing element processors PE25.
Each PE 25 has its own data memory 26 and processes the data in the data memory 26. The PEs 25 are connected to each other via a network 27 and can perform data communication with other PEs 25. The PE 25 operates according to the microcode broadcast from the arithmetic control unit 21.

The network 27 connects the PEs 25 to each other to enable communication between PEs. The form thereof is, for example, a two-dimensional lattice connection as shown in FIG. 18 or the one shown in FIG.
The x-y bus connection shown in FIG. 9 and the hyper-cube connection not shown are well known.

In the following, the description will be continued by taking the two-dimensional lattice connection of FIG. 18 as an example, but other network forms such as xy bus connection and hypercube connection are also applicable.

The arithmetic control unit 21 controls each P of the arithmetic execution unit 22.
The following control can be performed on E25.

(1) All PEs 25 simultaneously perform the same processing.

(2) At least all the PEs 25 arranged in one row or all the columns of the PEs 25 arranged two-dimensionally are selected, and the same processing is simultaneously performed only on the selected PEs 25. A procedure for multiplying two matrices by using the parallel computer described above will be described.

Here, let us consider a case where a product of n × n matrices, C = A * B, is obtained on a PE array arranged in a two-dimensional n × n array. PE 25 located at i-th row and j-th column is PE
Let (i, j) represent (0≤i≤n-1, 0≤j
≤n-1). Each PE 25 arranges the data so that it has one element in each of the matrices A and B as initial data.

That is, PE (i, j) (0≤i≤n-
1, 0 ≦ j ≦ n−1) is initial data a [i] [j], b [i]
Holds [j]. PE (i, j) (0≤i≤n-1, 0≤j
In the case of ≤n-1), each of the PEs 25 is in charge of the calculation of the element c [i] [j] of the matrix C, and all PEs 25 perform the calculation simultaneously. PE
The calculation performed in (i, j) (0≤i≤n-1, 0≤j≤n-1) is as follows.

C [i] [j] = 0; k = 0 to n−1 c [i] [j] = c [i] [j] + a [i] [k] * b [k] [j ];repeat. (I) The multiplication procedure 1 will be described with reference to the flowchart of FIG.

(1) In each PE (i, j), c [i] [j] =
Initialize c as 0 (step 101).

(2) The first operation in PE (i, j) is c [i] [j] = c [i] [j] + a [i] [0] * b [0] [j] ; (II).

Here, PE (i, j) (1≤i≤n-
In 1, 1 ≤ j ≤ n-1), a [i] [0] and b [0] [j] do not exist in the own data memory 26, so data transfer is necessary. a [i] [0] is PE (i, 0) in the first column
(0≤i≤n-1), and b [0] [j] is PE (0,
j) (1 ≦ j ≦ n−1).

First, PE (i, 0) (O ≦
i ≦ n−1) is another PE (i, 1) existing in the same row.
~ A (i] [0] is transferred to PE (i, n-1). This will be a 1 to n broadcast format.

The one-to-n broadcast of a [i] [0] is PE (i, 0).
First transfers a [i] [0] to the adjacent PE (i, 1),
Next, PE (i, 1) converts PE (i, 2) into a [i] [0].
, And finally, P (i, n-1), a [i] [0] is transferred, and data a [i] [0] is broadcast.
Can be executed in n-1 cycles by shifting between PEs.

The one-to-n broadcast in the row direction can be simultaneously executed in all the rows (0≤i≤n-1) (steps 102 to 103). FIG. 21 shows a state of 1-to-n broadcasting in the row direction when n = 4.

(3) Next, in order to transfer b [0] [j],
PE [0] [j] (0≤j≤n-1) in the first row is similarly processed to other PE [0] [j] to PE [n-1] [j] existing in the same column. Broadcast 1 to n (step 104). This 1-to-n broadcast can be performed simultaneously on all columns. FIG. 22 shows a state of 1-to-n broadcasting in the column direction when n = 4.

(4) Each PE (i, j) (0 ≦ i ≦ n−1, 0 ≦ j ≦ n−) by the above-mentioned two times of 1-to-n broadcasting.
In 1), since a [i] [0] and b [0] [j] have been acquired, the first calculation of equation (II) is performed (step 105).

(5) The second operation is c [i] [j] = c [i] [j] + a [i] [1] * b [1] [j]; (III).

That is, PE (i, j) (0≤i≤n-
1, 0 ≦ j ≦ n−1) requires a [i] [1] and b [1] [j] to be data-transferred. For this purpose, PE (i, 1) in the second column (0 ≦ i ≦ n−1) broadcasts a [i] [1] to another PE 25 in the same row in a 1-to-n broadcast, and then Second
PE (1, j) (0 ≦ j ≦ n−1) of the line is b [1] [j]
1 to n is broadcast to other PEs 25 in the same row.

23 and 24 show the state of 1-to-n broadcasting in the column direction and row direction of the second column and the second row when n = 4. Each PE (i, j) (0 ≦ i ≦ n-1, 0 ≦
In the case of j ≦ n−1), the calculation of formula (III) is performed.

(6) By repeating the above n times, each PE (i, j) (0≤i≤n-1, 0≤j≤n-
In 1), c [i] [j], which is the product of the matrices, is obtained (steps 103 to 107).

According to the multiplication procedure 1 described above, since the results are accumulated in each PE 25 each time an operation is performed, it is not necessary to have all the data in advance, and matrix multiplication can be executed with a small memory amount. That is, the amount of memory required for each PE 25 may be two initial data, two data transferred in one iteration, and one for the solution c, that is, a memory 26 for a total of 5 data, It does not depend on the value of n. That is, even if the value of n becomes large, the memory amount of each PE 25 can be small.

However, in the multiplication procedure 1, the time required for data broadcasting is slower than that of the conventional method. In this method, one-to-n broadcasts in the row and column directions are performed once by one repetition. Since 1-to-n broadcasting takes n-1 cycles,
The data transfer time of the entire matrix multiplication is 2 * n * (n-1) cycles. On the other hand, in the conventional method, the data transfer is 2 *
(N-1) cycles, and the data transfer time is
The larger n is, the more disadvantageous.

Therefore, the following solutions can be considered.
As for the row direction, n: n is previously set as in the conventional method.
Hold all data necessary for calculation by broadcasting. In the column direction, 1-to-n broadcasting is repeated according to the multiplication procedure 1 described above. This is shown as multiplication procedure 2 in FIG.
A description will be given according to the flowchart of FIG.

(1) First, all necessary data are acquired in the row direction. That is, PE (i, j) (0 ≦
i≤n-1, 0≤j≤n-1) is a [i] [0] to a [i] [n-
1] is obtained from another PE 25 in the same row. The method for this is the same as the conventional method. That is, first, each PE 25 simultaneously transfers its own data to the PE 25 on the right side (steps 111 to 113).

Next, each PE (i, j) (0≤i≤n-1,
0.ltoreq.j.ltoreq.n-1) transfers a [i] [j-1] received from the PE (i, j-1) on the left side to the PE 25 on the right side. As a result, PE (i, j) is transmitted from PE 25 on the left to a
[i] [j-2] will be received and stored in the memory 26.

By repeating this processing n-1 times, PE (i, j) can receive a [i] [0] to a [i] [n-1] (steps 114 to 116). . From the above, all necessary data in the row direction can be obtained. This n-to-n broadcast can be executed in parallel in each row. The time required for broadcasting is n-1 cycles.

(2) In the following, data transfer in the column direction and calculation are repeated. As the data necessary for the first calculation, PE (0, j) in the first row (0 ≦ j ≦ n−
1) broadcasts b [0] [j] 1: n to PE 25 in the column direction. For 1-to-n broadcasting, first, b is transmitted to the adjacent PE (1, j).
[0] [j] is transferred, and then PE (1, j) becomes PE (2, j).
Data b [0] [j] is transferred to PE (n-1, j) and b [0] [j] is transferred to PE (n-1, j). j] is shifted between PEs so that n
-1 cycle can be executed (steps 117 to 11)
8).

(3) Each PE (i, j) (0≤i≤n-
The equation (II) is calculated with 1,0 ≦ j ≦ n−1) (step 119).

(4) As the data required for the second calculation, PE (1, j) (0≤j≤n-1) in the second row sets b [1] [j] to PE 25 in the column direction. Broadcast 1 to n (steps 120 to 118).

(5) As the second calculation, the formula (III) is calculated (step 119).

(6) By repeating the above, matrix multiplication can be performed (steps 118 to 12).
1).

Here, a method has been shown in which all data is held in advance in the n-to-n broadcast in the row direction and the calculation is repeated with the 1-to-n broadcast in the column direction. The same can be done when retaining the data.

In the multiplication procedure 2, since the memory amount required for the calculation in each PE 25 is all the data of either the row or the column, it may be n, which is 1/2 of the conventional method. The data transfer time is n for the first n-to-n broadcast in the row direction.
-1 cycle, and subsequent 1-to-n broadcasting in the column direction is n-1 times n times, so the total number of transfer cycles is n * (n-
1) + n-1 cycles, which is shortened to 1/2 of 1-to-n broadcasting in both row and column directions.

Further, as shown in FIG. 19, in the row direction,
It is also possible to consider an xy bus coupling system in which the PEs 25 in the column direction can be broadcast to all PEs in the row direction or all PEs in the column direction in one cycle. x-
y-bus coupling is PE (i, 0) to PE existing in the same row.
(I, n-1) (0≤i≤n-1) are bus-coupled and PE (0, j) to PE (n-1,
j) (0 ≦ j ≦ n−1) is a bus coupling method.

As the procedure for performing matrix multiplication using this xy bus combination method, the above-described method can be applied as it is, except for the 1-to-n broadcast described in multiplication procedures 1 and 2. Data broadcasting can be realized by reading the broadcast data from the broadcasting PE 25 to the bus and reading the data from the remaining PEs 25 from the bus, so the time required for one data broadcasting is 1
It is a cycle.

In the matrix multiplication as a whole, the time required for data transfer is 2 * n cycles, which is almost the same as the transfer time when the conventional multiplication method is used in the two-dimensional lattice coupling method. Of course, the amount of memory required for calculation can be extremely small as compared with the conventional method.

As described in detail above, the parallel computer of the third invention can significantly reduce the amount of memory used per PE as compared with the conventional system. Therefore, even if the amount of memory per PE is small, multiplication is performed. Can be executed. Although the data transfer time increases twice as much as the two-dimensional lattice connection, the data transfer time can be suppressed to the same level as the conventional method by introducing the xy bus connection or the like.

The arithmetic expression (I) used here performs the same arithmetic operation on all PEs 25 in each iteration. Also,
Since data transfer also performs the same processing row by row or column by column, it can be said that this is a multiplication method suitable for SIMD computers. However, MIMD (Multiple Instruction Multipl)
Of course, it can be executed on an e Data Stream type parallel computer. This MIMD computer is characterized in that each PE 25 has an instruction memory and an instruction decoder unit, and each PE 25 can perform different processing, but the multiplication method of the third invention can also be executed.

[0204]

According to the first aspect of the present invention, an instruction group is formed for each instruction having a dependency relationship, and instruction scheduling is performed with the instruction group as one unit, so that even when the execution time differs depending on the instruction, the execution is executed. It can be compiled into a sequence of instructions that saves the most time. Moreover, since scheduling is performed in units of instructions, scheduling can be performed efficiently.

According to the parallel computer of the second invention,
On a parallel computer with multiple processors arranged in a one-dimensional or two-dimensional manner, it is only necessary to perform data communication between adjacent processors without compromising the numerical characteristics for solving simultaneous linear equations. It becomes possible to execute at high speed.

Further, according to the parallel computer of the third invention, matrix multiplication can be executed even if the memory amount per each arithmetic element processor is small. Large-scale matrix multiplication,
It is composed of a large number of arithmetic element processors, and is particularly effective when the memory amount per arithmetic element processor is limited.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a compiler of a first invention.

FIG. 2 is a flowchart of the instruction scheduling unit shown in FIG.

FIG. 3 is a source program and an instruction sequence before scheduling, which are used when explaining the scheduling method by the compiler of the first invention.

FIG. 4 is a list of instruction group configuration, execution time of each instruction group, and next instruction issuable time for explaining the scheduling in the first invention.

FIG. 5 shows an instruction sequence and execution state after instruction scheduling according to the first invention.

FIG. 6 is a configuration diagram of a parallel computer when simulating a two-dimensional area in the second invention.

FIG. 7 is a configuration diagram of a parallel computer when simulating a three-dimensional area in the second invention.

FIG. 8 is a flowchart showing the operation of the parallel computer according to the second invention.

FIG. 9 is a grid point when a physical area is divided into two dimensions.

FIG. 10 shows an incomplete LU decomposition (1,
The lower triangular matrix L obtained by performing 1).

FIG. 11 shows the incomplete LU decomposition (1,
The figure showing the dependence of calculation of a solution at the time of using 1).

FIG. 12 shows an incomplete LU decomposition (1,
2) The lower triangular matrix L obtained by performing.

FIG. 13 is an incomplete LU decomposition (1,
The figure showing the dependence of calculation of a solution at the time of using 2).

FIG. 14 is a grid point when a physical area is divided into three dimensions.

FIG. 15 shows the incomplete LU decomposition (1,
The lower triangular matrix L obtained by performing 1, 1).

FIG. 16 shows an incomplete LU decomposition (1,
The figure showing the dependency of calculation of a solution when using 1, 1).

FIG. 17 is a block diagram showing the configuration of an embodiment of a parallel computer according to the third invention.

FIG. 18 is a configuration example of the arithmetic execution unit shown in FIG.

FIG. 19 is a configuration example of an arithmetic execution unit different from FIG.

FIG. 20 is a flowchart showing a matrix multiplication procedure in the third invention.

FIG. 21 is a diagram showing a state of row-direction data broadcasting in the third invention.

FIG. 22 is a diagram showing a state of column-direction data broadcasting in the third invention.

23 is a diagram showing a state of data broadcasting in the row direction similar to FIG.

FIG. 24 is a diagram showing a state of data broadcasting in the column direction similar to FIG. 22.

FIG. 25 is a flowchart showing a matrix multiplication procedure different from FIG. 20.

FIG. 26 shows a typical pipeline and a state of execution.

FIG. 27 shows a configuration of a computer, a source program, and an instruction sequence before scheduling for explaining a conventional compiler.

28A and 28B are states of execution of the instruction sequence shown in FIG. 27 and a dependency directed graph for the instruction sequence.

FIG. 29 is a pattern obtained by a conventional compiler.

FIG. 30 shows how the patterns shown in FIG. 29 are executed.

FIG. 31 is a configuration example of a conventional parallel computer for the third invention.

32 is a diagram showing a state in which initial data is arranged in each PE shown in FIG. 31. FIG.

FIG. 33 is an equation showing the product of two 4 × 4 matrices.

FIG. 34 is a flowchart showing a conventional matrix multiplication procedure for the third invention.

FIG. 35 is a diagram showing a state in which each PE shown in FIG. 31 holds all necessary data.

[Explanation of symbols]

 1 Source Program 2 Source Program Input Section 3 Lexical Analysis Section 4 Syntax Analysis Section 5 Intermediate Code Generation Section 6 Instruction Scheduling Section 7 Optimization Section 8 Intermediate Code Optimization Section 9 Object Code Generation Section 10 Objective Program Output Section 11 Objective Program (1 )-(4), (1,1)-(3,3) Processor 13 Local memory 21 Arithmetic control unit 22 Arithmetic execution unit 23 Data bus 24 Instruction memory 25 PE (arithmetic processor) 26 Data memory 27 Network

Claims (4)

[Claims] 1. A plurality of arithmetic units that can be executed in parallel are provided,
A compiler that generates a target program used in a computer that processes instructions in a pipeline, and configures an instruction group for each instruction that has a dependency relationship with an instruction sequence in a basic block, and uses the instruction group as a unit. It is characterized by an instruction scheduling unit that changes the execution order of instructions, moves up or down so that the empty state of the pipeline becomes small, and optimizes the execution time of the instruction sequence to be the shortest. compiler. 2. A parallel computer composed of a plurality of processors for solving simultaneous linear equations, which is represented by a simulation of a physical phenomenon in a two-dimensional area divided into a two-dimensional lattice, wherein the i-th processor is -1) Receiving means for receiving the physical quantity sent from the processor, calculating means for calculating the physical quantity of the lattice point for this i-th processor using the received physical quantity, storage means for storing the calculated physical quantity, and calculating A physical quantity to a (i + 1) th processor, and a physical quantity calculation of a grid point on the i-th row of the two-dimensional grid.
The i-th processor allocates the physical quantity transmitted by the transmitting means of the (i-1) th processor to the receiving means after the calculation of the physical quantity of the assigned lattice point on the i-th row becomes possible. The receiving means calculates the physical quantity of the lattice point allocated using the received physical quantity by the calculating means, stores the calculated physical quantity in the storing means, and sends the calculated physical quantity to the (i + 1) th processor by the i-th processor. A parallel computer characterized by repeating all grid points in a row. 3. A parallel computer composed of a plurality of processors for solving simultaneous linear equations, which is represented by a simulation of a physical phenomenon in a three-dimensional region divided into a three-dimensional lattice, wherein (i, j) processors are: The (i-1, j) processor and the receiving means for receiving the physical quantity sent from the (i, j-1) processor, and the (i, j
j) calculating means for calculating the physical quantity of the lattice point for the processor; storage means for storing the calculated physical quantity; and the calculated physical quantity for the (i, j + 1) processor and (i + 1,
j) processor and transmitting means for sending to the processor, the physical quantity calculation of grid points on the same axis of the three-dimensional grid is assigned to the same processor, and (i, j) processor is the assigned grid on the same axis. Since the calculation of the physical quantity of points becomes possible, the (i-1, j) processor and (i, j-)
1) The receiving means receives the physical quantity transmitted by the transmitting means of the processor, the calculating means calculates the physical quantity of the assigned lattice point using the received physical quantity, and the calculated physical quantity is stored in the storage means and transmitted. By means (i + 1,
j) A parallel computer characterized in that sending to the processor and the (i, j + 1) processor is repeated for all assigned lattice points on the same axis. 4. A parallel processor composed of a plurality of arithmetic element processors arranged in a two-dimensional manner, which is a parallel computer for obtaining the product of two matrices, wherein the first matrix data and the second matrix data are , The same allocation is performed on the two matrices, and 1 is set between the arithmetic processors having row-direction data of the matrices.
Means for broadcasting data from one arithmetic processor to other plural arithmetic processors, and means for broadcasting data from one arithmetic processor to other plural arithmetic processors between arithmetic processors having data in the column direction of the matrix Each arithmetic processor having means for controlling the number of repetitions and control means for controlling the operation of the data broadcast and the arithmetic processor, and holding one column of data in the first matrix designated by the number of repetitions Transfers each column data simultaneously in parallel to a plurality of arithmetic processors holding data belonging to the same row as each column data, and holds one row of data specified by the number of repetitions of the second matrix. Each arithmetic processor that transfers the row data simultaneously and in parallel to a plurality of arithmetic processors that hold data belonging to the same column as the row data, In Tsu service obtains the data of the transferred first matrix, the product of two numbers of the transferred second of data,
A parallel computer characterized in that a product of a matrix is obtained by accumulating the products for each repetition and repeating the above operation a predetermined number of times obtained from the size of the matrix.