JPH06282511A - Fault processing device of computer system having network - Google Patents

Abstract

PURPOSE:To provide a network which does not affect on other message transfer even if any fault occurs in the process of a message transfer. CONSTITUTION:The fault detected by a fault detector 102 is held in a fault holding register A 110 or a fault holding register B 111, and the detected word number is held in a fault word number holding register 112. When a message generation circuit 120 judges that they are inputted and the fault is detected by a transfer destination processor number, the circuit 120 outputs a message to the processor shown by the transfer destination processor number at the time of the occurrence of the fault to be delivered from a selector 109. Because the message is made to be transferred to a proper processor in place of the transfer destination processor when a fault occurs in the transfer destination processor number of the message, the message does not stop in the network and does not affect on other message transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for transferring data between a plurality of processors via a network, and more particularly to a failure processing device when a failure occurs on a data transfer path connecting the processors to the network.

[0002]

2. Description of the Related Art Conventionally, a parity bit or an error collecting code (ECC) has been used as a means for detecting an error in data transfer due to a hardware fault.
A method of adding rrecting code) to data and transferring the data is known. Error detection and error control using parity bits are discussed, for example, in Kozo Kayashima, "System Design of Computers" (Industry Co., Ltd.), pages 216 to 218. Here, the parity is checked on a byte-by-byte basis, the result of the parity check is recorded in a flip-flop, and the timing pulse of the entire system is stored in order to preserve the error state as accurately as possible and prevent it from affecting the normal logic part. Controlled to stop. By stopping the timing pulse, the execution of the entire system is frozen in that state, and the frozen state is logged out to the storage device as a record. The information logged out is analyzed and it is determined whether it can be re-executed.

[0003]

When the above-mentioned conventional technique is applied to a network of a system having a plurality of processors such as a parallel computer, if a failure is detected in one message transfer, the entire network is frozen. All other message transfers in the network that are unrelated to the failure are also temporarily suppressed. For example, in a parallel computer having a network topology disclosed in Japanese Patent Laid-Open No. 63-124162, two messages having different transmission sources and different reception destinations may pass through the same route on the way, resulting in a faulty message. If you prevent the forwarding of the message there, the other message will be blocked along that route. Especially in an operation mode in which multiple user programs are executed at the same time, that is, in a so-called multi-job execution environment, as a result, the network freezes, which affects the message transfer of jobs unrelated to the message that caused the failure, and degrades performance. In some cases, it can even cause abnormal termination of the job. As an example of applying ECC to a transfer message between processors of a parallel computer, Japanese Patent Application Laid-Open No. 4-1395
66. The present invention has an ECC in the receiver processor number, corrects when a failure occurs in the transfer of the receiver processor number, and transmits it to the processor to which it should be sent. There is no mention of how to deal with a failure that cannot be corrected even by using ECC, and this is a problem to be solved.

An object of the present invention is to provide an intermittent (intermittent) fault caused by fluctuations in power supply voltage or noise during message transfer between processors via wires or cables on the board. It is an object of the present invention to provide a failure processing device capable of performing the failure processing without affecting other jobs.

[0005]

SUMMARY OF THE INVENTION The present invention does not freeze the network (thus, does not stop the transfer of messages in the network) even if such a failure occurs in the middle of message transfer, and the message can be transmitted appropriately. The above object is achieved by transferring the data to a processor or a host computer and performing failure processing there.

To this end, the present invention provides a field for setting a fault occurrence bit in a message indicating that a fault has occurred during the transfer of a message between processors, and for detecting a fault in a network. A failure detecting means, and first, if the failure detecting means detects a failure, enabling the failure occurrence bit provided in the message;
And setting means of.

Further, the fault identifying means for identifying whether or not the fault is detected in the receiving processor number setting field in the message, and the fault identifying means for detecting the fault in the receiving processor number setting field. In this case, it has a replacement means for replacing the receiving processor number with the processor number in order to transfer it to the appropriate processor.

Further, a field is provided in the message for setting information relating to a fault, and when the fault is detected by the fault detecting means, the word position or byte position where the fault is detected, or the location where the fault is detected. A second setting means for setting information for identifying is provided.

[0009]

The present invention has the following actions due to the above-mentioned configuration. The message in which the failure is detected by the failure detection means is further related to the failure when the failure occurrence bit in the message is validated and the failure identification means identifies that the failure is not in the receiving processor number. The appropriate fault information is set in the field for setting the information, and the message is transferred to the destination processor specified in the message.

When the fault identifying means identifies a fault in the receiving processor number, the fault occurrence bit is validated and appropriate fault information is set in a field for setting information relating to the fault. Is set to the appropriate replaced processor in place of the failed destination processor number.

In any of the above cases, the message is forwarded to either processor so that the failed message does not stop in the network. Further, since the fault information is also transferred together, it is possible for the processor that receives the message to perform appropriate fault processing.

[0012]

【Example】

(Embodiment 1) The present invention can be applied to all systems in which a plurality of processors transfer data via a network, but as an embodiment, an example applied to a parallel computer as shown in FIG. 1 will be described. To do.

The feature of this embodiment is that when a failure is detected in the message receiver processor number and the receiver becomes unknown, the receiver processor number is replaced with an appropriate processor number so that the message is not stopped in the network. In addition, the failure processing of the message or job by the processor that received the failed message is to limit the effect of the failure to only the message or the job and not to affect the execution of other jobs.

FIG. 1 shows the configuration of a parallel computer in this embodiment. In FIG. 1, 10, 11, 12
Is a processor PE (1), PE that constitutes a parallel computer
(2), ..., Represents PE (n). Although not shown in FIG. 1, each of the processors PE (1), PE (2), ..., PE (n) has a memory for storing data and a program therein, and a program using the data. It is composed of a CPU for executing the above and can operate independently. 20 is each processor PE (1), PE
(2), ..., Jobs are assigned to PE (n), that is, programs and data required for execution are loaded into each processor before the start of the job, and obtained by each processor after the end of the job. It is a host computer that reads the resulting data. Reference numeral 30 is a network for transferring messages between a plurality of processors and between each processor and a host computer. Here, a crossbar network is assumed. Reference numeral 40 is a service processor having a maintenance / diagnosis function.

In the present embodiment, it is assumed that the network 30 is composed of one LSI, and the data transfer in the LSI is more reliable than the transfer via the cable or the wiring on the board. It is assumed that no failure will occur. Signal lines 10X, 11X, 12X, 20X, 60X, 61 connecting the network 30 to the processors 10, 11, 12 or the host computer 20.
X, 62X, 63X assume cabling or wiring on the board, on which messages may be transferred and failures may occur.

In the present embodiment, it is assumed that a plurality of jobs can be executed at the same time, and that two jobs, job 1 and job 2, are executed by each processor as shown below.

Job 1: PE (1), PE (2), PE (n) Job 2: PE (1), PE (2) Two processors, PE (1) and PE (2), have two processors. Jobs are time-divided and executed simultaneously.

Next, the message transfer of the parallel computer according to the present invention will be described with reference to FIG. The processors to which the same job is assigned transfer messages required for execution to each other via the network and execute the programs independently. PE (1) 10, PE (2) 11, PE (n) 1 to execute job 1
The message is transferred between two PEs, and the message is transferred between PE (1) 10 and PE (2) 11 in order to execute job 2. Here, the message transfer from the PE (1) 10 to the PE (2) 11 will be described as an example.

The message is the processor PE of the transmission source.
(1) 10 is assembled according to the format shown in FIG. The message may be assembled by a program or by dedicated hardware. As shown in FIG. 3, the message is based on a word which is a unit to be transferred at one time, and one message is composed of a plurality of words.

Each word has a "fault detection code A" for detecting a "field A" and a field A transfer error, and a "fault detection code B" for detecting a "field B" and a field B transfer error. Consists of. Many fault detection codes have been proposed depending on the difference in the faults that can be detected, and any code that can be added in word units such as ECC (Error Correcting Code) or parity may be used, but in the present embodiment, a parity bit is used. This is explained using an example that employs. When ECC is used, a 1-bit error can be corrected, but a 2-bit error can only be detected and cannot be corrected. Using ECC in this embodiment, the following description applies when a 2-bit fault occurs in the message.

The second to third words are message attribute information. The 4th word to the (m-1) th word are data transferred between processors necessary for executing a user's job. The m-th word is information regarding the failure of the message. In this embodiment, the limitation on the message length is not particularly mentioned.

The field A of the first word contains the receiving processor number A10 and the receiving processor number failure bit A.
It consists of 11. Receiver processor number failure bit A11
Indicates that a failure has occurred in this field A. The network 30 controls internal switches (switches 60 to 63 to be described later) according to the receiver processor number A10. When the destination is the host computer, the value "n + 1" is set as the destination processor number. The receiver processor number failure bit A11 has been previously cleared to 0 by the sender processor, and is set to 1 when a failure occurs in the field A of the first word during the transfer of the message. The field B of the first word is a field for setting transfer control information of a message that is not directly related to the recipient, such as priority information added to the message.

The field A of the second word is a field for setting the source processor number A20. The field B of the second word is a field for setting the transfer destination processor number B20 at the time of failure occurrence, and when the failure occurs during message transfer and the destination processor becomes unknown, the message is fixed. The number of the processor to be transferred is set.

The field A of the third word is the job ID.
It is composed of A30 and message ID A31. The job ID A30 is a value given to identify the job with respect to the job assigned to the processor. The message ID A31 is a value given to identify the message.

The field B of the third word comprises a data transfer length B30, a job cancel request bit B31, a resend request bit B32 and a transfer mode B33. The length of data included in the message is designated by the data transfer length B30. The transfer mode B33 is a field that indicates whether the message is a retransmittable message. A message that can be retransmitted is a message that the sender processor holds in its memory until a reply message indicating that the message was successfully received is received from the receiver processor. When a resend request arrives from, it becomes possible to send again. When the resend request bit B32 is 1, it indicates that the message is a request for resending the message. When the job cancellation request bit B31 is 1, it indicates that the message is a message requesting cancellation of the job indicated by the job ID A30. How to use the job cancel request bit B31, the resend request bit B32, and the transfer mode B33 will be described later.

The field A of the m-th word sets a message failure bit indicating that a failure has occurred in any word in the message and a failure word number indicating which word the failure word is. It is a field to do. The message fault bit is reset to 0 in advance by the transmission source and transmitted. The field B is a field for setting failure location information indicating which of the transfer paths between the transmission source and the reception destination has a failure.

In FIG. 1, the processor PE of the transmission source
(1) The message composed of 10 is transferred to the network 30 via the signal line 10X. Signal line 10X
Is composed of three types of signal lines 10A, 10B and 10C for carrying signals as shown in FIG. As shown in FIG. 2, the signal line 10B carries a signal indicating the start of message transfer, the signal line 10A carries a message, and the signal line 10C carries a signal indicating the end of message transfer. Is. The message transfer start signal is the first
It becomes 1 when the word is transferred. The message transfer end signal becomes 1 when the mth word is transferred. The message transfer start signal and the message transfer end signal enable the network to know the start and end of the message.

A signal line 11X for transferring a message from another processor or a host computer to the network.
., 12X, and 20X are also composed of the same three types of signal lines. In addition, the message controllers 100, 200,
... 300, 400 to switches 60, 61, ...
.., signal line 122 for transferring messages to 62, 63
, 222, 422X, and switches 60, 61, ..., 62, 63 to processor PE (1) 10, processor PE (2) 11 ,.
Signal lines 60X, 61X, ..., 62 for transferring messages to the processor PE (n) 12 and the host computer 20.
X and 63X are also composed of the same three types of signal lines.

Signal line 1 from processor PE (1) 10
0X is input to the message controller 100 inside the network 30. Message controller 100
Indicates the receiver processor number set in the field A of the first word of the message via the signal line 105A to the switch controllers 50, 51, ..., 52, 53.
To the switches 60, 61, ..., 62, 63 via signal line 122X. The other message controllers 200, ..., 300, 400 are the same except that the source of the input signal is different.

Switch controllers 50, 51, ...
., 52, 53 are corresponding switches 60, 6
Generate control signals to control the selection of messages at 1, ..., 62, 63. Each switch controller recognizes the destination processor number sent from the message controller and, when the destination processor number indicates the corresponding processor, controls the switch to select the message sent from that message controller. When the destination processors compete, the switches are controlled so that the messages are transferred to the processors in the order in which they arrived at the switch controller.

Each switch 60, 61, ..., 62, or 63 corresponds to a corresponding switch controller 5
According to the control signals sent from 0, 51, ..., 52, 53, the message controllers 100, 200,
This circuit selects one of the messages sent from 300 and 400. Each switch 60, 61, 62, or 6
The message selected in 3 is the signal lines 60X, 61X,
..., processor PE via 62X or 63X
(1) 10, PE (2) 11, ..., PE (3) 1
2, sent to the host computer 20. In this case of transferring a message from PE (1) 10 to PE (2) 11, switch controller 51 controls switch 61 to select the message sent from message controller 100 via signal line 122X. The signal line 122X is selected by the switch 61, and the signal line 61X is selected.
Is output to. At this time, the other switch controller 5
0, 52 and 53 are switches 60, 62 and 63, and the signal line 1
22X is controlled not to be selected.

Next, message control in the message controller 100 will be described with reference to FIG.

The signal line 10X is input to the sequencer 101. FIG. 7 shows the internal configuration of the sequencer 101. The sequencer 101 internally has a counter 130 which is reset by a message transfer start signal of the signal line 10B and which is incremented by 1 each time one word is transferred to the signal line 10A for transferring a message. When the value of the counter 130 is 1, that is, when the first word is sent, the '1' detector 131 recognizes that the value is 1, and the signal on the signal line 101A causes the register B 113 to store the field A of the message. Set the receiver processor number included in. Also, when the value of the counter is 2, that is, when the second word is sent, the '2' detector 132 recognizes that the value is 2, and the signal of the signal line 101B also sends a message to the register C106. The source processor number in field A is
The transfer destination processor number at the time of occurrence of a failure in the field B of the message is set in the register D107. Signal line 10
The value of the counter 130 at that time is output to 1C. The signal line 101D is a signal for instructing the fault detector 102 to detect a fault when one word of a message is received. Signal line 122B, signal line 122C
Correspond to the input signal lines 10B and 10C,
After being set once in the registers 133 and 134, the message transfer start and the message transfer end are output at the timing of FIG.

The fault detector 102 has a function of detecting a fault for each field when the signal line 10A to which a message is sent is input and the message is sent, that is, when the signal line 101D is 1. When a failure is detected in the field A, 1 is set in the failure holding register A110, and when a failure is detected in the field B, 1 is set in the failure holding register B111 by the signal line 102A. When a fault is detected, the faulted word number (transmitted from the sequencer 101 via the signal line 101C) is similarly held in the faulty word number holding register 112 regardless of the detected field. The fault holding register A110 and the fault holding register B111 are reset in preparation for the transfer of the next message when the transfer of one message is completed (not shown because it can be realized by a known technique).

The data buffer 108 is a data holding circuit that holds data until a message is read.

The register A103 is a holding circuit for holding a transfer destination of a message, which is sent from the service processor via the signal line 40A when a failure occurs, in advance when the system is started up. The mode register 104 similarly
Selector 1 for selecting the message transfer destination when a failure occurs
Holds the mode bit that controls 09.

FIG. 5 shows the relationship between the value held in the mode register 104 and the register selected by the selector 109. When 0 is set in the mode register 104, the register A 103 is selected, when 1 is set, the register C 106 is selected, and when 2 is set, the register D 107 is selected. This function allows the receiver processor number A1 in the message being transferred.
When a failure occurs in 0, the transfer destination of the message is
It can be set appropriately according to the failure processing method.

The setting value of the mode register 104 is used to control how the system is operated, for example, to manage jobs.
It depends on which processor executes S, whether the message can be retransmitted, etc., and is set in advance prior to job execution when the system is started up.

For example, in the transfer mode in which all messages can be retransmitted, the mode register 104 is set to 1 and the message in which the failure has occurred in the receiver processor number is designated by the sender processor number A20 in the message. Return to the sender. In that case, it is not necessary to include the transfer destination processor number B20 at the time of occurrence of a failure in the message. When the retransmittable and non-retransmittable messages are mixed, the mode register 104 is set to 2, and the message is sent to the processor of the transfer destination processor number B20 at the time of the failure in the message in which the failure has occurred and the message is transferred. Fault processing is performed by the OS running on the preceding processor. If the operating system that manages the job is executed only on a specific processor, 0 is set in the mode register 104 and the processor number is set in the register A 103. Even in that case, the transfer destination processor number B20 at the time of occurrence of a failure in the message is not necessary.
In this embodiment, the case where 2 is set in the mode register 104 will be mainly described below, but the same applies to other cases.

The "1" detector 115 outputs 1 when the value held in the fault word number holding register 112 is "1", and the AND circuit 114 logically ANDs the output and the value of the fault holding register A110. To generate. AND circuit 114
When the output of 1 is 1, the signal line 109 is selected by the selector 105, and when it is 0, the signal line 113A is selected. Details of the operation of these circuits will be described later.

When a failure occurs, the message generation circuit 120 receives the signal line 108A from the data buffer 108.
Is a circuit for generating a message in which failure information and the like are added to a message sent via the.

FIG. 6 shows the inside of the message generation circuit 120. In FIG. 6, the selector control circuit 123
Is the selector 122 according to the value of the input signal.
To control. That is, the signal line 110A is 1 (indicating that a failure is detected in the field A), the signal line 122B is 1 (indicating the first word transfer cycle), and the signal line 112A is the value "1"("1".'Indicating that 1 is detected by the detector 124 and a failure is detected in the first word), AND circuit 1 for generating a logical product of input signals
The output of 26 becomes 1, and the message A is displayed by the selector 122.
Select. The signal line 110A is 1 (indicating that a failure is detected in the field A) or the signal line 111A is 1 (indicating that a failure is detected in the field B) and the signal line 122C is 1 (the transfer cycle of the mth word). , The output of the OR circuit 125 for generating the logical sum of the input signals is 1, and the output of the AND circuit 127 for generating the logical product of the input signals is 1, and the selector 122 outputs the message B. Select. In other cases, the output of the NOR circuit 128 becomes 1 and the message C is selected.

The fault detection code generation circuit 121 takes the exclusive OR of all the input signal lines to generate the parity. However, the fault detection code B for the message A and the message C is the field B of the message sent from the data buffer 108 via the signal line 108A.
Similarly, the fault detection code A of the message C is newly generated by inputting only the field A.
If no fault is detected, a new fault detection code will not generate a logical contradiction. Further, when a failure is detected and the transfer is performed with the failure left, the same failure will be detected on the next transfer path, and the location of the failure cannot be uniquely specified. Therefore, mth
Fault information is added to a word, and a faulty code is regenerated and transmitted for a faulty word. Therefore, both the failure detection code A and failure detection code B fields of the message sent via the signal line 108A are not used.

The OR circuit 124 is a circuit for generating a logical sum of the signal line 110A and the signal line 111A.

The operation of the message generating circuit 120 will be described below with reference to FIG. 6 by classifying each field and word in which a failure has been detected. The case where no failure is detected in any word, the case where a failure is detected in the field A of the first word, and the case where a failure is detected in a field other than the field A of the first word will be described separately.

(1) When no fault is detected in any of the words, the input message is output as it is.

In this case, the signal lines 110A and 111
During the message transfer, A, 112A:

Signal line 110A: = 0 (no fault in field A) Signal line 111A: = 0 (no fault in field B) Signal line 112A: = value 0 (reset when message arrives In this case, in this case, in every word transfer cycle, the message C, which is the message sent from the data buffer 108 via the signal line 108A, is selected and output to the signal line 122A.

(2) When a failure is detected in the field A of the first word In this case, the failure causes an error in the receiver processor number and the receiver processor becomes unknown. In this case, the destination processor is replaced with an appropriate processor or host computer for transfer.

In this case, the signal lines 110A and 111
During the message transfer, A, 112A:

Signal line 110A: = 1 (failure detected in field A) Signal line 111A: = 0 (no problem in field B) Signal line 112A: = value 1 (failure detected in the first word) ) Therefore, the transfer cycle of the first word (122B: =
In 1), the message A is selected, and the destination processor number is replaced with the destination processor number sent via the signal line 109A. Further, the fault bit field is replaced with 1 of the signal line 110A (indicating that the receiver processor number has a fault). Signal line 109
The receiver processor number sent via A is the register receiver A103 (the message receiver processor number at the time of occurrence of a failure set by the service processor) selected by the value of the mode register set in advance by the service processor. ), The register C106 (source processor number), or the register D107 (transfer destination processor number when a failure occurs in the field B of the second word of the message), as described above.

Message C is selected from the second word to the m-1th word.

Message B is selected as the mth word.
At this time, the message failure bit is 1 (indicating that there is a failure somewhere in the message), the failure word number is also 1 (indicating that the failure is detected in the first word), and the failure point information is in the signal line 10A. Information "1A" indicating that a failure has occurred is sent. Also, in this case, the output of the '1' detector 115 is 1, and the output of the AND circuit 114 is also 1.
In 53, the signal line 109 indicating the receiver when the receiver processor number is incorrect is selected by the selector 105 and sent via the signal line 105A.

If the fault bit is erroneously transferred instead of the destination processor number, the field A of the first word
Fault is detected. However, since it cannot be distinguished from the failure in the receiving processor number, it is considered that there is a failure in the receiving processor number. If it is desired to limit the detection of the fault to the destination processor number, the fault bit may be held in another word or the field B of the first word instead of the field A of the first word.

The object of the present invention is to prevent the influence of a fault during the message transfer between processors via the network from affecting the other jobs especially in the multi-job execution environment. Processor 10, 11 to 12 or a host computer 2 on which an OS that manages a process that is a unit of
It is preferably 0. The processor or host computer that has received the failure message performs failure processing in the same procedure as described below.

First, the receiving processor number failure bit is 1
Recognizing that is, the CPU generates an interrupt, and passes control to the fault message processing routine. The failure message processing routine recognizes the sender processor number, job ID, message ID and transfer mode bit in the message.

When the transfer mode bit is 1, that is, indicating a retransmittable message, a resend request message containing the following information is returned to the sender.

Recipient processor number ← Source processor number in fault packet Job ID ← Job I in fault packet
D Message ID ← Message ID in failure packet Resend request bit ← 1 The processor receiving this resend request message recognizes that the resend request bit is 1, and the message to be retransmitted is determined from the job ID and the message ID. Read from memory and send again.

When the transfer mode bit is 0, that is, it indicates that the message is not a retransmittable message, in order to cancel the execution of the job to which the fault message belongs,
Send a job cancel request message to _the processor that is executing the job. The processors to be sent are all the processors to which the job is assigned. The OS manages the allocation of jobs.
The relation between the job and the assigned processor is described in the table managed by S.

The job cancel request message includes the following information.

Recipient processor number ← Processor number to which the job is assigned Job ID ← Job I in the fault packet
D Job Cancel ← 1 Request Bit The resend request message and the job cancel request message may be generated by any means (hardware means or software means). The job cancel request message is sent from the sender and the recipient.
It may be sent to all applicable processors using a one-to-one message, or sent to all processors using a one-to-all processor broadcast message, and should be canceled using the job ID on the receiving processor side. You may select a job.

The fault location information includes signal lines 10Y and 11Y for the purpose of pointing out a component (cable or board) related to the fault location and notifying the system administrator of the component to be replaced.
It is sent to the service processor via 12Y and 20Y. The system administrator can know the occurrence of a failure from the failure point information displayed on the service processor, and can replace the part and take noise countermeasures.

Each of the processors 10, 11 to 12 and the host computer 20 has a detection circuit for detecting a parity fault therein, and each processor 1 from the network 20.
0, 11 to 12 or a failure in the middle of transferring a message to the host computer 20 is detected. When a failure is detected in the field A of the first word of the received message, the same processing as when the message having the reception destination processor number failure bit of 1 is received is performed.

(3) When a failure is detected in the field B of the first word This is a case where an error has occurred in the transfer control information due to the failure. Although this case is a failure of the first word, since there is no error in the receiver processor number, the fact that there is a failure is added, and it is transferred to the processor specified by the receiver processor number.

In this case, the signal lines 110A and 111
During the message transfer, A, 112A:

Signal line 110A: = 0 (no failure in field A) Signal line 111A: = 1 (failure detected in field B) Signal line 112A: = value 1 (failure detected in the first word) ) Therefore, the first word transmission cycle (122B: = 1)
Message C is selected, the destination processor number is not replaced, and the fault bit remains 0. A fault detection code B is generated and added to the message for the transfer control information in which the fault is detected.

Message C is selected in the transmission cycle from the second word to the m-1th word.

Mth word transmission cycle (122C: =
In 1), the message B is selected. At this time, the message fault bit is 1 (indicates that there is a fault somewhere in the message), the fault word number is also 1 (indicates that the fault is detected in the first word), and the fault line information is signal line "10A". Information indicating that a failure has occurred is sent.

Even if a failure is detected in the same first word, if a failure is detected in the field B, it is distinguished from the failure of the receiver processor number in the field A, and a message is sent to the receiver processor designated by the sender processor. Will be sent, and failure processing can be performed without entrusting the failure processing to another processor or host computer unrelated to the message transfer.

(4) When a failure is detected in a word other than the first word This is a case in which a failure occurs in the second word and thereafter, that is, in words that do not directly affect the message recipient. In this case, as in the case of (3) above, since there is no error in the receiver processor number, the fact that there is a failure is simply added to the message and transferred to the processor specified by the receiver processor number.

In this case, the signal lines 110A and 111
During the message transfer, A, 112A:

Signal line 110A or signal line 111A: =
1 (a failure is detected somewhere) Signal line 112A: = value k (a failure is detected in the kth word, where k ≠ 1) Therefore, the message C is selected from the first word to the m-1th word . A failure detection code is generated again for the kth word in which the failure is detected and added to the message.

Message B is selected as the mth word.
At this time, the message fault bit is 1 (indicates that there is a fault somewhere in the message), the fault word number is k (indicates that the fault is detected in the kth word), and the fault line information is the signal line "10A". Information indicating that a failure has occurred is sent.

Finally, in the cases of (1), (3) and (4) where there is no failure in the destination processor number, the message has a failure in the destination processor designated by the sender and in the recipient processor number ( In the case of 2), it is transferred to an appropriate processor or host computer according to the value of the mode register.

As described above, even if a failure is detected during the transfer of a message, the receiving processor is changed and transferred according to the status of the failure, or the information on the failure is captured in a part of the message. , Can be transferred to the destination processor without suppressing the message transfer.

Example 2 This example provides a network that uses a different message format than Example 1 and yet uses a simpler message controller.

The message format of this embodiment is shown in FIG. In the present embodiment, the transfer destination processor number B used in the first embodiment when a failure occurs in the message (FIG. 3)
Twenty (FIG. 3) was not specified in the message and the circuitry in the message controller that responded to that processor number was omitted. That is, when the receiver processor number in the message being transferred fails, a specific processor defined by a circuit in the network, for example, P
I tried to send the message to E (1). further,
When the message needs to be retransmitted, the circuit for transferring the message to the source processor is omitted from the message controller, and the specific processor transfers the message requesting the retransmission to the source processor. did. In addition, except for the destination processor number failure bit A11 in the first word of the message and the mth word, the circuits associated with them have been deleted from the message controller.

As described above, in this embodiment, the structure of the message controller of the network is simplified. In the following, the same reference numbers as used in the first example refer to the same. Also in this embodiment, it is assumed that programs belonging to a plurality of jobs are executed by a plurality of processors, and the relationship between the programs executed by each processor and the jobs is the same as in the first embodiment.

In FIG. 8, when sending a message, each processor uses the information in field A of this word and this code as the fault detection code A of each word of the message, as in the first embodiment. Determines the value of the fault detection code so that has a predetermined parity. The same applies to the fault detection code B of each word.

FIG. 9 shows the configuration of the message controller 100A according to this embodiment. Since the transfer destination processor number B20 when a failure occurs is omitted from the message, the mode register 104, the register A103, and the register C10 of the message controller 100 in FIG.
6, the register D107 and the selector 109 are unnecessary.
Further, since the fault bit A11 and the m-th word of the first word are removed from the message, there is no place in the field of the message to be changed when the fault is detected, and the message generation circuit 120 is also unnecessary.

When a message is input to the message controller shown in the figure, the receiver processor number A10 in the field A of the first word of the message is set in the register 113 in the same manner as in the first embodiment, and is further set in the selector 105. Transferred.

In this embodiment, PE is used as a specific processor to which a fault message in which a fault is detected in the field A (reception destination message number A10) of the first word is to be transmitted.
(1) is used. Therefore, the selector 105 has
The number "1" of this processor is entered.

Fault detector 1 in the message controller
When 02 detects a failure of the field A of the first word in the message to be transferred, the same as in the first embodiment AN
The D circuit 114 becomes 1 and the number of the specific processor PE (1) to which the selector 105 should send the failure message is'
1'is selected and sent to the signal line 105A.

In the fault detector 102, as in the second embodiment, this message controller determines whether or not there is a parity error in the field A of the first word of the message input thereto. If there is a parity error in this field, register 1
'1' is set to 10, and the register 112
Is set to the word number 1. Register 11
The content of 0 is sent to the AND circuit 114. When the content of the register 112 is "1", the output of the "1" detector 115 is "1". Therefore, the output of the AND circuit 114 becomes 1. Similarly to the first embodiment, the selector 105 determines whether the register 11 has a value corresponding to whether the output of the AND circuit is 1 or not.
Select the content of 3 or the constant '1'.

When the fault detection circuit 102 does not detect the fault, the output of the AND circuit 114 becomes "0", and the selector 105 selects the receiver processor number designated by the message in the register 113, When a failure is detected, the constant '1' is selected.
The processor number of the selected receiver is the signal line 105A.
To the plurality of switch controllers 50, 51, etc. provided corresponding to the plurality of output ports of this network, and these switch controllers are input / output corresponding to the receiving processor number selected by the selector 105. Control the switch of the port to select the message.

As a result, when the fault detector 102 does not detect the fault, the inputted message is transferred to the processor having the receiver processor number designated by the processor. When the above-mentioned fault is detected, this message is transferred to the processor PE (1).

In this embodiment, unlike the first embodiment,
When the fault detector 102 detects a fault in the following word, it will not rewrite the fault detection code A or B in the message.

In this embodiment, the processor PE (1) is used.
Determines whether or not there is a failure in the combination of the information in each field A or B of each word of that message and the failure detection code A or B added to that field when receiving any message, It has a circuit (not shown) for determining whether or not there is a fault in the field A or B, and transferring the result of the determination together with the received message to the processing unit (not shown) in the processor. In this embodiment, specifically, this determination circuit includes a parity check circuit.

In this processing device, the message is appropriately processed by the program depending on whether or not the parity determination result for each field of each word of the received message is a normal value.

(1) When there is an error in the receiver processor number This message was a message to be transferred to another processor, but this processor has an error in the receiver processor number. P
The following process is performed assuming that the fault message is transferred to E (1).

(1a) When the transfer mode bit B33 of the third word in the message requests retransmission, a message requesting retransmission of this failure message is sent to the processor having the source processor number A20 in the message. send. That is, the processor having this processor number includes the received job ID (A30) and message ID (A31), and the resend request bit B32.
Sends a message in which is 1.

(1b) If the transfer mode bit B33 of the received failure message prohibits resending, a message for requesting job cancellation is sent to the processor managing the job specified by the job ID in the message. send. The processor number and each job I
The relationship with D is stored in this processor PE (1). The message for cancel includes the job ID (A30) and the message ID (A31) in the received message, and the job cancel request bit B31 is 1. Furthermore, this processor PE
From (1), the host processor 20 (FIG. 1) is notified, and accordingly, the occurrence of a failure is notified to the system management program running on the host processor 40.

Note that the processor which has received the message requesting the job cancel request causes the plurality of processors executing the program belonging to the job specified by the job ID included in the message to cancel the execution of those programs. Send a message asking for.

The above processing is performed when the above determination circuit determines that the field A of the second word and the fields A and B of the third word are normal. If any of these fields are more unusual,
The above processing cannot be performed. However, in reality, there is little possibility of multiple errors in which the error of the destination processor number in this message and the error of the above three fields occur at the same time. If any of the above three fields has an error, an executable process is selected based on the information indicated by the normal field among the above three fields. For example, when there is an error in the transmission source processor number of the field A of the second word, even when both the fields A and B of the third word are normal,
The received fault message is sent to the host processor 20.
(FIG. 1), and accordingly, the occurrence of a failure is notified to the system management program running on the host processor 40.

(2) When there is no error in the destination processor number When the determination circuit determines that the destination processor number A10 of the first word of the received message is a normal value, this number is the processor PE ( It is determined whether or not it matches the number of 1).

(2a) When the receiver processor number A10 of the first word of the received message is a normal value and coincides with the number of the processor PE (1), the following measures are taken.

In this case, assuming that the message is originally a normal message addressed to the processor, the data in the fourth word to the m-1th word in the message is processed.

Originally, the destination processor number in this message was different from the number of this processor PE (1), but 2 bits of the original number were inverted due to an error during the transfer of the message, As a result, the destination processor number after the error happens to be PE (1).
If it matches the number of (1), it is not judged as an error by the parity check, and in this case as well, it cannot be distinguished from the case of (b1). However, in this embodiment, it is assumed that such a multiple error is unlikely to occur. In order to process such multiple errors, an ECC code may be used as the fault detection code A in the message and an ECC circuit may be used as the determination circuit. In this case, 2
Since even bit errors can be corrected, message errors can be determined more accurately.

(2b) The receiver processor number A10 of the first word of the received message is a normal value, and
When this number does not match the number of the processor PE (1), the following measures are taken.

If this message is normal, it is unlikely that such a message will arrive at PE (1).
Therefore, such a message is processed by the above (1) in the same manner as the message in which the failure has occurred.

(Embodiment 3) This embodiment is an example in which a network using a plurality of interconnected partial networks, which is disclosed in JP-A-63-124162, is used in place of the network of Embodiment 2. is there. This network is suitable for fast transfer of messages between many processors.

FIG. 10 shows the configuration of a parallel computer having the above network. In this embodiment, processors (PE (11) to PE (44), 16 units in total) are arranged two-dimensionally, and each is arranged in the X direction crossbar network (X1).
~ X4), Y direction crossbar network (Y1 to Y4)
And a parallel computer interconnected by relay switches (EX (11) to EX (44)). The host processor 40 and the service processor used in the first embodiment are also connected to this network, but they are not shown in FIG. 10 for simplification.

Each crossbar network is the same as the network used in the first embodiment, and each has a plurality of pairs of input / output ports and transfers messages in parallel between them. In this embodiment, each input / output port is connected to one relay switch. Each processor has a two-dimensional address (YX), and each X-direction crossbar network (X1 to X4) has X coordinates 1, 2, and
3 and 4, Y-direction crossbar networks (Y1 to Y4) are provided corresponding to Y coordinates 1, 2, 3, and 4, respectively, and each relay switch EX (ij) is one Y Directional crossbar network Yi (i = 1, 2, 3
Or 4) and one X-direction crossbar network Xj
(J = 1, 2, 3, or 4) and are connected to the input / output ports of the crossbar network and the processor PE (ij).

That is, each relay switch EX (ij)
Is one Y-direction crossbar network Yi (i = 1,
2, 3 or 4) and one X-direction crossbar network Xj (j = 1, 2, 3 or 4) are provided corresponding to the input / output ports of these crossbar networks and the processor PE (ij). It is connected to the.

After all, the Y direction crossbar network Yi
(I = 1, 2, 3 or 4) has a plurality of processors PE (i having an X coordinate address i and different Y coordinates).
1) is a partial network for connecting PE (i4) to each other, and is an X-direction crossbar network Xj (j
= 1, 2, 3, or 4) has a Y coordinate address of j and a plurality of processors PE (1
j) is a partial network for connecting PEs (4j) to each other.

In this network, message transfer between processors is performed as follows. For example,
When a message is transferred from the processor PE (12) to another PE (43) having different X and Y coordinates, the PE (12) sends the message to the relay switch EX (12) provided correspondingly. , Send a message with (43) as the destination processor number. The relay switch EX (12) first sends this message to the lateral crossbar network X2.

In the network, from the input / output port for Y coordinate 4 of this message to the relay switch EX.
This message is transferred to (42). When the relay switch EX (42) determines that the X coordinate 3 of the destination processor number of this message is different from its own X coordinate, it further transfers this message to the Y-direction crossbar network Y4. In this network, the message is output to the relay switch EX (43) via the input / output port corresponding to the X coordinate 3 of the destination address of this message. When this relay switch determines that both the X coordinate and the Y coordinate of the destination address of this message match those of its own, it transfers this message to the processor PE (43) connected to itself. As described above, in the network used in the present embodiment, the X and Y coordinates are used as the destination address in the message, and the message further includes the first relay switch to which the source processor is connected and the connection to the first relay switch. The X-direction crossbar network, the Y-direction crossbar switch to which the second relay switch corresponding to the destination processor is connected, and the second relay switch are connected to the destination processor. Transferred.

If the processor PE (11) has another Y-coordinate, for example, PE (14).
When sending a message to the relay switch EX
(11) transfers the message to be transmitted to the Y-direction crossbar switch Y1 common to these processors. This message is then transferred to the target processor PE (14) via the relay switch EX (14).

As described above, this network has a merit that the message transfer to the distant processor is fast because the number of times of changing the network is small as compared with other known networks called mesh and torus.

In this embodiment, each X-direction crossbar network, each Y-direction crossbar network, each relay switch, and each PE are configured in one LSI. Therefore, when a message is transferred on the line connecting these, an error may occur in the message.

In this embodiment, as in the first and second embodiments, it is assumed that a plurality of programs belonging to a plurality of jobs are executed in parallel by these plurality of processors. For example, a plurality of processors having the same X coordinate and different Y coordinates form a job group that executes a plurality of programs belonging to the same job. Alternatively, a plurality of processors having the same Y-coordinate but different X-coordinates form one job group that executes a plurality of programs belonging to the same job. Alternatively, the X coordinate is within a certain range, and
A plurality of processors having a Y coordinate within a certain range may configure one job group that executes a plurality of programs executed for the same job.

In the present embodiment, when it is found that the receiver processor number in the message input from any relay switch to any X-direction crossbar switch, for example, X1 is faulty, that message is sent to that crossbar switch X1. The data is transferred to a specific processor PE (11) connected to it via a specific relay switch determined by the crossbar switch, for example, EX11. In the present embodiment, this particular relay switch EX (11) is selected as the one having the smallest Y coordinate among the four relay switches connected to this crossbar switch.

Similarly, when it is found that the receiver processor number in the message input from any relay switch to any Y-direction crossbar switch, for example Y4, is faulty, the message is sent to that crossbar switch Y.
4 is transferred to a specific processor PE (41) connected to it via a specific relay switch determined by this crossbar switch, for example, EX41. In this embodiment, this specific relay switch EX (41) is connected to this crossbar switch 4
Of the two relay switches, the switch with the smallest X coordinate is selected.

Subsequent processing of the fault message transferred to these specific processors is basically the same as that in the second embodiment.

The format of the message of this embodiment is shown in FIG. This is the X-coordinate A100 and Y-coordinate A of the receiving processor as the receiving processor number of the message.
This is different from the second embodiment in that 101 sets are included.

In this embodiment, each X-direction crossbar network and each Y-direction crossbar network are different from the message controller 100, 20 in comparison with the network 30 of FIG.
It is basically the same except the internal configuration such as 0 and the connection between the host processor 20 and the service processor 40. In this embodiment, not all X or Y direction crossbar networks need to be directly connected to the host processor, but one or more X or Y direction crossbar networks may be connected to the host processor by appropriate paths. Good. The same applies to the service processor.

As shown in FIG. 12, the internal structure of the message controller used in each X-direction crossbar network and each Y-direction crossbar network of this embodiment is a partial modification of the message controller of the second embodiment. The message controller of FIG. 12 is obtained by adding the coordinate cutout circuit 116 to the message controller of the second embodiment shown in FIG.

The message controller of the X-direction crossbar network and the message controller of the Y-direction crossbar network have output ports for transferring the respective input messages, only the X coordinate and the Y coordinate of the receiving processor in the message, respectively. To decide from.

The coordinate cutout circuit 116 in the X direction crossbar network cuts out the X coordinate in the message input to the message controller to which it belongs and sends it to the register B113. Similarly, the coordinate cutout circuit 116 in the Y direction crossbar network cuts out the Y coordinate in the message input to the message controller to which it belongs and sends it to the register B113. Register B11
The coordinates held in 3 are input to the selector 105.
When a failure is detected in the field A of the first word of the message, the selector 105 outputs the message to the port No. 1. Therefore, when the failure occurs, the constant '1' is input to another input. Is being supplied as.

In the fault detector 102, as in the first and second embodiments, this message controller determines whether or not there is a parity error in the field A of the first word of the message input thereto. If there is a parity error in this field, A
The output of the ND circuit 114 becomes 1. The selector 105 is
Similar to the first embodiment, the content of the register 113 or the constant "1" is selected depending on whether the output of the AND circuit is 1 or not.

When the fault detection circuit 102 does not detect the fault, the selector 105 causes the register 11
When the address of the output destination port in 3 is selected and the fault is detected, the constant '1' is selected. The selected output destination port address is sent via the signal line 105A to the three switch controllers provided corresponding to the above three input / output ports in the relay switch.
The switch of the input / output port having the output destination port address selected by is controlled to select the message.

In this embodiment, the relay switch EX (11)
1 are basically the same as those of the network 30 of FIG. 1 except for the number of input / output ports, the internal configuration of the message controllers 100 and 200, and the connection between the host processor 20 and the service processor 40. That is, the number of input / output ports of each relay switch is 3, as can be seen from FIG. In this embodiment, neither relay switch is directly connected to the host processor and service processor.

As shown in FIG. 13, the internal structure of the message controller used in each relay switch is different from that of FIG. 12 in that a destination determination circuit 117 is used instead of the coordinate cutout circuit 116 of the message controller of FIG.

The destination determining circuit 117 stores a register (not shown) for holding the X and Y coordinates of the processor connected to the relay switch and a message input to the message controller to which the circuit 117 belongs. A comparator (not shown) that compares the X and Y coordinates as the receiver processor number with the coordinates of the processor held in this register, and the address of the port to which the message should be output based on the result. And a circuit (not shown) for determining

In this embodiment, the addresses of the input / output ports of each relay switch are assumed as follows. The address of the input / output port connected to the processor is 0, the address of the input / output port connected to the Y direction crossbar network is 2, and the address of the input / output port connected to the X direction crossbar network is 1.

As a result of the comparison, the destination determining circuit 117 is connected to the processor when the X and Y coordinates in the input message both match the X and Y coordinates of the processor. When only the input / output port address (0) and their X-coordinates match, only the input / output port address (2) and their Y-coordinates that are connected to the Y crossbar switch to which the relay switch is connected match. At this time and when their X and Y coordinates do not match, the address (1) of the input / output port connected to the X-direction crossbar switch to which the relay switch is connected is output. The values indicating these output destinations are held in the register B113 and sent to the selector 105.

The other input of this selector 105 is
The I / O port connected to the processor connected to the relay switch is used as the I / O port used when the failure detection circuit 102 detects the failure of the destination processor number of the message input to the message controller. Address (0) is supplied.

When the fault detection circuit 102 does not detect the fault, the selector 105 causes the register B1.
The address of the output destination port in 13 is selected, and when the fault is detected, the constant '0' is selected.
The selected output destination port address is the signal line 105A.
To the three switch controllers provided corresponding to the above three input / output ports in the relay switch.
The switch of the input / output port having the output destination port address selected by 5 controls the message to be selected.

As described above, in this embodiment, the logical scale of the message controller is reduced as compared with the first embodiment, and the failure processing of the failure message can be executed.

Message transfer using this network is performed from the processor PE (12) to the processor PE (3
4) will be described as an example. Since the recipient of this message is the PE (34), the recipient processor number of the message is set to 3 for the X coordinate A100 and 4 for the Y coordinate A101.

The message sent from PE (12) is relay switch EX (12), X-direction network (X
2), the relay switch EX (32), the Y-direction network (Y3), and the relay switch EX (34) in this order to P.
E (34).

Processor P of relay switch EX (12)
In the message controller of the port to which E (12) is connected, the X coordinate 1 of the processor PE (12) connected in the destination determination circuit 117 (this value is held in the destination determination circuit 117). Then, the X coordinate 3 and the Y coordinate 2 of the message (this value is also held in the transmission destination determining circuit 117) and the Y coordinate 4 of the message are compared. In this case, since both do not match, the output value of the transmission destination determination circuit 117 is 1, and this is set in the register B113. When there is no obstacle in the field A of the first word,
The value is selected by the selector 105, sent to the signal line 105, and controlled by the switch controller to be sent to the X-direction network (X2). When a failure is detected in the field A of the first word, the AND circuit 1
The output of 14 becomes 1, the value “0” is selected by the selector 105, and the processor PE (1
It is controlled to be sent to 2). This allows the failed message to be forwarded to the processor.

In the message controller of the port to which the relay switch EX (12) in the X-direction network (X2) is connected, the coordinate cut-out circuit 116 cuts out the value 3 of the X-coordinate of the message and sets it in the register B113. When there is no fault in the field A of the first word, the value 3 is selected by the selector 105 and the signal line 10
5 is sent to the relay controller E by the switch controller.
It is controlled to be sent to X (32). When a fault is detected in the field A of the first word, the output of the AND circuit 114 becomes 1, the value “1” is selected by the selector 105, and the relay switch EX is selected by the switch controller.
It is controlled to be sent to (12). As a result, the faulty message can be transferred to the relay switch and further to the processor via the relay switch.

The processing in the specific processor that has received the failure message is the same as that in the second embodiment.

(Modification) (1) In the first embodiment, the transfer destination processor number B20 (FIG. 3) at the time of occurrence of a failure can be designated in the message, but this can be omitted.

(2) Although the message transfer destination processor number specified by the service processor in the register A (103) in the first embodiment can be specified, it can be omitted.

(3) In the first, second, and third embodiments, the resend request message can be sent to the sender processor designated by the message, but it is also possible to omit it.

(4) In the first, second and third embodiments, the parity bit is used to detect the message failure, but the ECC code that can correct the error of 1 bit and detect the error of 2 bits or more is used. It is also effective to do.

(5) In the third embodiment, the fault message is transferred to the end processor in each X crossbar network or Y crossbar network, but among all the processors used in that embodiment, It is also effective to transfer to a processor at the end of the network such as PE (11).

(6) In the second or third embodiment, the processor to which the message having the fault in the destination processor number is transferred, for example PE (11), is the job to which the program being executed by the processor that issued the message belongs. Although the message requesting the cancellation of the execution of the job is transferred to the program executing the program managing the execution of the job, the message may be transferred from the specific processor to the host processor (not shown).

(7) In the first, second, and third embodiments, as a processor for transferring a failure occurrence message, of the plurality of jobs executed in parallel in each embodiment, connected to the failed input / output port. It is also effective to change the transfer destination processor depending on the location where the failure occurs so that the executed processor transfers the execution of the job to which the executed program belongs. According to this method, when a message sent from any one of a group of processors executing a program belonging to a job fails in the network, a plurality of processors executing the program belonging to the job are managed. It becomes possible to automatically notify the occurrence of the failure to the processor executing the program to be executed.

(8) In the third embodiment, the processors are arranged two-dimensionally and they are connected by the X-direction network, the Y-direction network and the relay switch. The relay switch is a 4-input 4-output crossbar switch. By constructing and further adding a network in the depth direction, a parallel computer having processors arranged three-dimensionally can be easily realized.

The feature of the present invention is that when a failure occurs in the processor number of the receiving destination during the message transfer via the network, the failure message is transferred to an appropriate processor without stopping the message in the network and the failure occurs. It is to entrust the processing. Therefore, it can be applied to all parallel computers that transfer messages using the processor number of the receiver regardless of the topology of the network.

[0144]

According to the present invention, even if an error occurs in the destination processor number in the transfer path due to some failure,
The message can be transferred to any of the processors or the host computer by adding information regarding the failure. Therefore, it is possible to prevent a message whose recipient has been lost from stopping in the middle of the network and obstructing message transfer of other jobs. Further, since information related to a failure is added to the message and transferred, failure processing in the processor or the host computer receiving the message becomes easy.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a parallel computer according to a first embodiment and a second embodiment of the present invention.

FIG. 2 is a diagram showing a timing structure of an interface in the embodiment of the invention.

FIG. 3 is a diagram showing a message format according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an internal configuration of the message controller of FIG. 1 in the embodiment.

5 is a diagram showing a control method of a selector 109 in FIG.

6 is a diagram showing an internal configuration of a message generation circuit 120 of FIG.

7 is a diagram showing an internal configuration of a sequencer 101 of FIG.

FIG. 8 is a diagram showing a message format according to the second embodiment of the present invention.

FIG. 9 illustrates an internal configuration of a message controller according to a second exemplary embodiment.

FIG. 10 is a diagram illustrating a configuration of a parallel computer according to a third embodiment.

FIG. 11 is a diagram showing a message format according to the third embodiment of the present invention.

FIG. 12 is an X-direction network and Y according to the third embodiment of the present invention.
It is a figure which shows the internal structure of the message controller in a directional network.

FIG. 13 is a diagram showing an internal configuration of a message controller in a relay switch according to a third embodiment of the present invention.

[Explanation of symbols]

10-12 ... Processor, 20 ... Host computer, 30 ...
Network, 40 ... Service processor, 50-53
... switch controller, 60-63 ... switch, 10
0, 200, 300, 400 ... Message controller, 101 ... Sequencer, 102 ... Fault detector, 10
3, 106, 107, 1113 ... Processor number register, 104 ... Mode register, 108 ... Data buffer, 110, 111 ... Fault holding register, 112 ... Fault word number register, 120 ... Message generation circuit, 1
21 ... Fault detection code generation circuit, 123 ... Selector control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Inoue 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Junji Nakaetsu 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Hitachi Ltd. (72) Inventor Shinichi Suto 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Tatsuo Higuchi 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Co., Ltd. (72) Inventor Hiroaki Fujii 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Yoshiko Yasuda 1-280 Higashi Koikeku, Kokubunji City, Tokyo Inside Hitachi Central Research Center (72) Inventor Kiyohiro Ohara East, Kokubunji, Tokyo Koigokubo 1-chome 280, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tatsu Toba 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hiratsuru ELS Engineering Co., Ltd. (72) Inventor Masahiro Yamada 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hirate RLS Engineering Co., Ltd.

Claims (10)

[Claims] 1. A computer system for transferring a message between a plurality of processors via a network, wherein a message is transferred from an arbitrary first processor to an arbitrary second processor of the plurality of processors. A transfer destination of the message is specified by first transfer destination specifying information for specifying a transfer destination processor included in the message, wherein a failure occurs in the first transfer destination specifying information in the network. Fault identifying means for identifying whether or not it has been detected in a portion including the above, and the first forwarding destination designation when the fault identifying means identifies a fault in the first forwarding destination designation information. A computer system characterized by having first replacing means for replacing information with second transfer destination specifying information for specifying a new transfer destination processor. Harm processing apparatus. 2. The fault processing apparatus according to claim 1, wherein the message is divided into appropriate units as a whole, is added to each unit, and is capable of detecting a fault for each unit. A fault detection code having a fault detection code and a fault occurrence bit indicating that a fault has occurred during message transfer, and a fault detection unit that detects a fault using the first fault detection code in the network, and the fault detection unit. A fault processing apparatus comprising: a first setting unit that validates the fault occurrence bit when a fault is detected by. 3. The fault processing device according to claim 1 or 2, wherein third forwarding destination designation information for forwarding the message to the first processor is added to the message, and the third forwarding destination designation information is added.
The transfer destination designation information is used as the second transfer destination designation information. 4. The fault processing apparatus according to claim 1, wherein fourth transfer destination designation information for transferring the message to an arbitrary processor is added to the message, and the fourth message is added to the message.
The transfer destination designation information is used as the second transfer destination designation information. 5. The fault processing apparatus according to claim 1, wherein the network is provided with holding means for holding fifth transfer destination designation information for transferring a message to an arbitrary processor. A failure processing apparatus, wherein the fifth transfer destination designation information held in the holding means is used as the second transfer destination designation information. 6. The fault processing apparatus according to any one of claims 2 to 5, wherein a first field for storing information regarding a fault is provided in a message, and the fault is detected by the fault detecting means in the network. A fault processing apparatus, further comprising: second setting means for setting fault information relating to a fault in the first field. 7. The fault processing apparatus according to claim 6, wherein the fault information is information for identifying a unit in which a fault is detected. 8. The fault processing apparatus according to claim 6, wherein the fault information is information for identifying a location where a fault is detected. 9. The fault processing device according to claim 2, wherein when a fault is detected by the fault detecting means in the network, the second fault detection is newly performed from the data of the unit. Generating means for generating a code, and a second means for replacing the first failure detection code with the second failure detection code
A failure processing device, characterized in that the replacement means is provided. 10. The fault processing device according to claim 1, which is effective when it is detected that the message is a fault of a unit including the first transfer destination designation information. Two
A third field that enables the second field when the failure identification unit detects a failure in a unit including the first transfer destination designation information in the network. A failure processing device comprising setting means.