JPH0628060A - Reset circuit for cpu - Google Patents

Abstract

PURPOSE:To obtain a CPU reset circuit capable of holding contents stored in an internal RAM without clearing them even when a reset switch is operated. CONSTITUTION:A reset switch 6 is connected to an interruption terminal INT of a CPU 1, which includes an initializing routine for the reset switch 6 independently of an initializing routine for power ON. When a reset signal is inputted from the switch 6, the CPU 1 transfers processing to the reset switch initializing routine and initializes only another circuit without clearing the stored contents of the internal RAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit for a CPU.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a reset circuit of a conventional one-chip microcomputer incorporated as a controller in a control device or the like. In the figure, 1 is C
PU, 2 is ROM, 3 is RAM, 4 is an input / output (I / O) interface connecting with a controlled object, and 5 is power ON
A power-on reset circuit for automatically resetting at times, and 6 is a reset switch for manually resetting. The power-on reset circuit 5 and the reset switch 6 are connected to the reset terminal RST of the CPU 1, respectively.

Next, referring to the flow chart of FIG.
The operation of the conventional reset circuit will be described. When the power is turned on (step S41), the power-on reset circuit 5 operates (step S42), and a reset signal is given to the reset terminal RST of the CPU 1.

That is, when the power is turned on, the capacitor 51 in the power-on reset circuit 5 is charged with a predetermined time constant through the resistor 52, and is kept below a predetermined threshold level for a fixed time determined by this time constant. Is input to the reset terminal RST of the CPU 1.
The diode 53 is the capacitor 5 when the power is off.
1 for discharge.

Upon the input of this reset signal, the CPU 1 shifts to the initialization routine, checks the RAM 3 (step S43), then clears the stored contents of the RAM 3 to zero (step S44), and other necessary circuits. ,
For example, peripheral circuits such as registers in the CPU 1 and I / O interfaces are initialized. When this initialization process ends, the process moves to the main routine (step S4).
5) The predetermined control determined by the main routine is repeatedly executed.

When the reset switch 6 is turned on and a reset signal is input to the reset terminal RST (step S46), the process of the CPU 1 jumps from the main routine (step S45) to the initialization routine of steps S43 and S44. After checking the RAM 3 and clearing the stored contents to zero, the main routine is executed again (step S
The process returns to 45) and the process of the main routine is restarted from the beginning.

[0007]

In the case of a conventional CPU reset circuit, when the reset switch 6 is operated to perform a reset, the contents stored in the RAM 3 until then are cleared. Depending on the control target incorporating the microcomputer, it may be better to hold the stored contents of the RAM 3 as they are without clearing them at the time of reset, and restart the processing of the main routine using the held data. The conventional reset circuit cannot cope with such a case at all.

The present invention has been made to solve the above problems, and provides a CPU reset circuit that does not clear the contents stored in the internal RAM even if the reset switch is operated. It is intended to be provided.

[0009]

In order to achieve the above object, a reset circuit for a CPU according to the present invention connects a reset switch to an interrupt terminal of the CPU, and
A reset switch initialization routine independent of the power-on initialization routine is incorporated, and when a reset signal is input from the reset switch, the process proceeds to the reset switch initialization routine, and the internal RAM The memory contents of are not cleared but only other circuits are initialized.

[0010]

In the case of the reset circuit of the CPU according to the present invention,
When reset is applied from the reset switch, the process jumps to the initialization routine for the reset switch, and the internal RA
The memory contents of M are retained without being cleared, and only the other circuits are initialized. Therefore, the contents of the RAM remain intact even after a reset, so this RA
The processing of the main routine can be restarted using the stored contents of M.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the reset circuit according to the present invention. In the figure, 1 is a CPU, 2 is a ROM, and 3
Is RAM, and 4 is an input / output (I / O) connecting with the control target
Interface 5 is a power-on reset circuit that automatically resets when the power is turned on, and 6 is a reset switch for manually resetting.

In the case of the present invention, the power-on reset circuit 5
Is connected to the reset terminal RST of the CPU 1 like the conventional reset circuit, but the reset switch 6 is connected to the interrupt terminal INT of the CPU 1. Further, in the ROM 2, in addition to an initialization routine for resetting by the power-on reset circuit 5 (processing of steps S43 and 44 in FIG. 2), an initialization routine for reset switch (steps in FIG. 2). The process of S47) is prepared. This reset switch initialization routine is a program that does not clear at least the contents stored in the RAM 3.

Next, referring to the flowchart of FIG.
The operation of the above embodiment will be described. When the power is turned on (step S41), the power-on reset circuit 5 performs power-on reset as in the conventional case (step S42), and the initialization routine for power-on reset (steps S43 and 44) is executed. After that, the process proceeds to the main routine (step S45).

When the reset switch 6 is turned on to reset (step S46), this reset signal is input to the interrupt terminal INT of the CPU 1. CP
When U1 detects that a reset signal has been applied to the interrupt terminal INT, it jumps from the main routine that has been executed up to that point to the reset switch initialization routine (step S46), and clears the contents stored in RAM3. Instead, only other circuits, for example, peripheral circuits such as registers in the CPU 1 and I / O interfaces are initialized. Then, when the processing of the initialization routine for the reset switch is completed, the processing returns to the head of the main routine 45 and the processing of the main routine is restarted using the data stored in the RAM 3.

[0015]

As described above, the CP according to the present invention
According to the reset circuit of U, when a reset signal is input from the reset switch, the stored contents of the internal RAM are retained as they are without being cleared. Therefore, the main routine is performed using the data before the reset signal is input. The processing of can be restarted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a reset circuit of a CPU according to the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment.

FIG. 3 is a circuit diagram showing a reset circuit of a conventional CPU.

FIG. 4 is a flowchart showing the operation of the conventional circuit.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 4 I / O interface 5 Power-on reset circuit 6 Reset switch RST Reset terminal INT interrupt terminal

Claims (1)

[Claims] 1. A reset switch is connected to an interrupt terminal of a CPU, and an initialization routine for a reset switch, which is independent of an initialization routine at power-on, is incorporated, and when a reset signal is input from the reset switch. CP shifts the processing to the resetting routine for the reset switch and initializes only the other circuits without clearing the contents stored in the internal RAM.
U reset circuit.