JPH06276458A - Voice mute circuit for muse signal - Google Patents

Abstract

PURPOSE:To operate the mute circuit even when a MUSE signal is tentatively interrupted by detecting an HD pulse in the MUSE signal and executing muting when no HD pulse is detected thereby quickening the reply speed of the voice mute circuit. CONSTITUTION:The circuit is provided with a memory 3 receiving an HD pulse extracted from a MUSE signal input and converted into a digital signal, an output of a counter starting count with the HD signal synchronously with the MUSE signal input to provide a signal, and a discrimination signal discriminating a form of the HD pulse at each address, and writing data in advance to said address and storing the data, a serial parallel conversion circuit 6 converting data read from the memory 3 into a parallel digital signal, a gate circuit 7 making the gate through in response to an output of the serial parallel conversion circuit 6, a latch circuit 8 latching an output from the gate circuit 7 with the HD signal to provide an output and mutes the voice output signal based on the output of the latch circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an audio mute circuit for a MUSE signal receiver.

[0002]

2. Description of the Related Art In a conventional audio mute circuit of a MUSE signal receiver, a frame pulse detection circuit is provided in an audio decoding circuit so that the frame pulse detection circuit detects continuous four frame pulses. Then, when the frame pulse of 4 frames cannot be detected, the mute signal is output to perform the muting of the audio output signal.

[0003]

Therefore, when the MUSE signal is temporarily interrupted (for example, when the LD software is switched or when the BS tuner is switched to another channel), frame pulses of four frames continue. Muting is performed when it cannot be detected due to a slow response speed of the audio mute circuit, and the audio mute circuit does not operate and the audio signal disappears and only the noise sound is output. . The present invention detects the HD pulse signal of the MUSE signal, and when the HD pulse signal cannot be detected,
By muting the audio output signal, the response speed of the audio mute circuit is increased, and even if the MUSE signal is temporarily interrupted, the mute circuit operates to prevent noise sound from being output. The purpose is to

[0004]

[Means for Solving the Problems] As shown in FIG.
An HD pulse signal extracted from the SE signal input and converted into a digital signal, a counter output that starts counting and outputs a signal with the HD signal synchronized with the MUSE signal input, and a determination signal that determines the shape of the HD pulse To the respective addresses to write and store data in advance at the same address portion, a serial-parallel conversion circuit 6 for converting the data read from the memory 3 into a parallel digital signal, and a serial-parallel conversion circuit 6 A gate circuit 7 that opens a gate according to an output, and a latch circuit 8 that latches an output from the gate circuit 7 with an HD signal and outputs the same.
And mutes the audio output signal of the MUSE signal receiver based on the output.

[0005]

According to the present invention, with the above-mentioned configuration, the HD pulse signal in the MUSE signal is detected.
HD extracted from signal input and converted to digital signal
A pulse signal, a counter output that starts counting with a HD signal synchronized with the MUSE signal input and outputs a signal, and H
Memory 3 for inputting a discrimination signal for discriminating the shape of D pulse
For example, data 0 is written in advance in the address portion of 1 and 1 is written in the portion corresponding to other addresses, 0 is normally read from the memory 3 and output, and MUSE signal input, especially HD pulse signal input When the data is interrupted, data containing 1 or 1 and 0 is read from the memory 3, the read data is discriminated by the gate circuit 7 and a signal is output, and a mute signal is output based on the output. Therefore, the response speed of the audio mute circuit can be made faster than that of the conventional method.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, MUSE.
It is an electric circuit block diagram which shows the audio | voice mute circuit of a signal. Reference numeral 1 is a MUSE signal input terminal, which receives a MUSE signal from a BS tuner or a MUSE signal source such as a laser disk (LD).
Using the sampling frequency of 16.2MHz in the / D converter 2, one line of the horizontal scanning line of the MUSE signal is sampled at 480 points, converted into an 8-bit digital signal and output, and the MUSE decoding circuit 11 and audio decoding Input to circuit 12 and memory 3, MUSE decoding circuit 11
Then, the MUSE signal is decoded to output a video signal, and the audio decoding circuit 12 decodes the audio data in the MUSE signal to output an audio signal.

FIG. 2 is an explanatory diagram of signals of respective parts, which is used for explaining the embodiment of FIG. The HD pulse signal in the MUSE signal sampled by the A / D converter 2 is located between sample numbers 1 to 12 as shown by the waveform a, and the HD pulse signal a is inverted every 1H of the horizontal scanning line. The signal has a waveform that rises when sample number 6 is line number n, and falls when line number n + 1 is sample number 6, and the level of sample number 6 is 1
It is quantized to have a level of 28/256.
ROM is used as the memory 3, and the A / D converter 2 uses 8
HD of MUSE signal converted to bit digital signal
The pulse signal a is input to the address numbers A0 to A7. 4 is an input terminal for HD signals, for example, MUSE
An HD signal as shown by a waveform c generated inside the MUSE decoding circuit 11 is input in synchronization with the signal input, and the HD signal is input to the control terminal of the counter 5 and the latch circuit 8.

A 4-bit counter is used as the counter 5, for example, resetting is performed at the rising edge of the HD signal of the waveform c, and counting is started at the falling edge so that the 4-bit counter output outputs the address numbers A8 to A1 of the memory 3.
You have entered 1. The horizontal counter 9 and the counter 10 are used as the determination means for determining the waveform of the HD pulse signal a that is inverted every 1H. The horizontal counter 9 starts counting at the trailing edge of the HD signal waveform c and is sampled. One horizontal scanning line is counted up to 480 and reset, and the MSB (most significant bit) is output and input to the counter 10. The counter 10 outputs a 1-bit signal in response to the same input and inputs it to the address number A12 of the memory 3.

For example, 0 is written in advance in the portion corresponding to the address numbers A0 to A12 of the lookup table of the memory 3, and 1 is written in the portion corresponding to the other addresses, and the data read from the memory 3 is read. It is converted into a parallel digital signal by the serial / parallel conversion circuit 6 and input to the gate circuit 7. An OR gate is used as the gate circuit 7, and the OR gate takes the logical sum of the outputs from the serial / parallel conversion circuit 6 and outputs the logical sum to the latch circuit 8. As the latch circuit 8, for example, a D-type flip-flop circuit is used, and the gate circuit 7
Is input to the data input terminal, the HD signal from the input terminal 4 is input to the control terminal, and the signal input to the data input terminal is latched and output at the rising edge of the HD signal waveform c. .

Therefore, when the MUSE signal is input to the input terminal 1, 0 is read from the memory 3, converted into a parallel digital signal by the serial / parallel conversion circuit 6, and the logical sum is obtained by the gate circuit 7. The output from the gate circuit 7 becomes an L level signal as shown by the signal d. Since the latch circuit 8 latches the L level input and outputs the output signal from the output pin (O bar), the H level signal as shown by the signal e is output. The audio output signal from the audio decoding circuit 12 is input to the mute circuit 13. For example, a switching device is used as the mute circuit 13, and the output from the latch circuit 8 is input to the control terminal of the switching device. , H level signal e is input, the audio decoding circuit 12
The audio output signal from is output.

When the MUSE signal input, especially the HD pulse signal input is interrupted, the memory 3 outputs 1 or 1 and 0.
Data is read out, converted into a parallel digital signal by the serial / parallel conversion circuit 6, and ORed by the gate circuit 7. Therefore, the output from the gate circuit 7 becomes an H level signal, and the latch circuit 8 outputs the H level signal. Since the input is latched and an output signal is output from the output pin (O bar), an L level signal is output. If the mute circuit 13 mutes the audio output signal by the L level signal input, the response of the audio mute circuit can be made faster than before, and when the MUSE signal is interrupted (LD software It is possible to prevent a noise sound from being output at the time of switching, at the time of switching channel selection by the BS tuner, etc.). The output from the output pin (O) of the latch circuit 8 is input to the mute circuit 13 so that the audio output signal is muted by the H level signal input and is muted by the L level signal input. An audio signal may be output via 13.

When 0 is written in the portion corresponding to the address numbers A0 to A7 of the look-up table of the memory 3, data is written with a certain width so that the MUS
The mute circuit may not operate due to noise included in the E signal input. For example, in FIG. 2, sample number 6 is 128/256 of a signal quantized with 8 bits.
And the signals input to the address numbers A0 to A7 are 10000000B (binary number). The output (b) of the 4-bit counter at this time counts 5, so the signals input to the address numbers A8 to A11 are 0101B. If the output of the counter 10 is 0 at the nth line, the address numbers A0 to A12
The signal input to is 0 0101 10000000
B, and the lookup table of the memory 3 is 580h.
If 0 is written in the address part of 0, and a width is written in the place where 0 is written so that 0 is also written in the address part of 570h to 590h, noise will be generated in the signals input to the address numbers A0 to A7. Even if it is included, 0 is read and output, and the noise resistance of the mute circuit can be improved.

FIG. 3 shows another embodiment of the present invention,
It is an electric circuit block diagram which shows the audio mute circuit of a MUSE signal. In the figure, the same parts as those shown in FIG. 1 are shown by the same symbols, and the difference from the embodiment of FIG. 1 is that the AND gate circuit 14 is used as the gate circuit 7. Further, for example, 1 is written in advance in a portion corresponding to the address numbers A0 to A12 of the lookup table of the memory 3, and 0 is written in a portion corresponding to other addresses. MUS for input terminal 1
When the E signal is input, 1 is read from the memory 3, and the AND gate circuit 14 performs a logical product on the signal input from the serial-parallel conversion circuit 6 to output an H level signal, and the latch circuit At 8, the H level input is latched so that the L level signal as shown by the signal e is output from the output pin (O bar), and when the HD pulse signal input is interrupted, 0 from the memory 3 or 1
The data of 0 and 0 are read out, converted into parallel digital signals by the serial / parallel conversion circuit 6, and ANDed by the AND gate circuit 14. Therefore, the output from the gate circuit 7 becomes an L level signal, and the latch circuit 8 Since the L level input is latched and the output signal is output from the output pin (O bar), the H level signal is output, and the H level signal is input to the mute circuit 13. The audio output signal may be muted.

[0014]

As described above, according to the present invention,
When the HD pulse signal in the MUSE signal is detected and the HD pulse signal cannot be detected, the mute signal is output to perform the muting of the audio output signal, so that the response of the audio mute circuit can be made faster. Yes, M
It is possible to prevent noise noise from being output even when the USE signal is temporarily interrupted (when switching the LD software, when switching to the BS tuner, etc.).
It greatly contributes to the performance improvement of the audio mute circuit for the E signal.

[Brief description of drawings]

FIG. 1 is an electric circuit block diagram showing an audio mute circuit for a MUSE signal, showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of signals of respective parts, which is used for explaining the embodiment of FIG.

FIG. 3 is an electric circuit block diagram showing an audio mute circuit for a MUSE signal, showing another embodiment of the present invention.

[Explanation of symbols]

 1 Input Terminal 2 A / D Converter 3 Memory 4 Input Terminal 5 Counter 6 Serial Parallel Conversion Circuit 7 Gate Circuit 8 Latch Circuit 9 Horizontal Counter 10 Counter 11 MUSE Decoding Circuit 12 Audio Decoding Circuit 13 Mute Circuit 14 AND Gate Circuit

Claims (4)

[Claims] 1. An HD pulse signal extracted from a MUSE signal input and converted into a digital signal, a counter output for starting counting and outputting a signal with an HD signal synchronized with the MUSE signal input, and an HD pulse shape A discrimination signal for discriminating is inputted to each address, data is written and stored in advance at the same address portion, a serial-parallel conversion circuit for converting data read from the memory into a parallel digital signal, and a serial-parallel conversion. It consists of a gate circuit that opens the gate according to the output from the circuit, and a latch circuit that latches the output from the gate circuit with an HD signal and outputs it. Based on this output, the audio output signal of the MUSE signal receiver is muted. MU characterized by
SE signal audio muting circuit. 2. The memory comprises a ROM, and the ROM
Of the look-up table, 0 is written in advance in a portion corresponding to an address to which the HD pulse signal, the counter output, and the discrimination signal are input, and 1 is written in a portion corresponding to another address. O
2. An audio mute circuit for a MUSE signal according to claim 1, wherein an R gate is used, and the OR gate outputs the logical sum of outputs from the serial-parallel conversion circuit. 3. The ROM comprises the ROM, and the ROM
Of the lookup table, 1 is written in advance in a portion corresponding to an address to which the HD pulse signal, the counter output, and the discrimination signal are input, and 0 is written in a portion corresponding to another address, thereby forming the gate circuit. A
The audio mute circuit for the MUSE signal according to claim 1, wherein an ND gate is used, and the AND gate takes the logical product of the outputs from the serial-parallel conversion circuit and outputs the logical product. 4. The voice of the MUSE signal according to claim 2, wherein the ROM is formed by writing data with a width in advance in a portion of the lookup table corresponding to an address for inputting the HD pulse signal. Mute circuit.