JPH06276090A - Pll circuit - Google Patents

Abstract

PURPOSE:To effectively realize a high-speed response and to obtain sufficient noise suppression effect after locking. CONSTITUTION:The PLL circuit is provided with a phase comparator 1, a charge pump circuit 2, a loop filter 30, and a voltage-controlled oscillator 4 and further provided additionally with charge pump circuits 21 and 22; and the charge pump circuits 21 and 22 charge capacitors 36 and 37 of the loop filter 30 quickly in high-speed mode to realize a high-speed response and obtain sufficient noise suppression effect after locking.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop circuit (hereinafter referred to as a PLL circuit), and more particularly to a PLL circuit used in a mobile communication device such as a car telephone or a cordless telephone to perform phase synchronization.

[0002]

2. Description of the Related Art In recent years, mobile communication devices such as car phones and cordless telephones have become widespread.
Circuits are an essential part of these communication devices.

FIG. 4 is a block diagram showing a conventional PLL circuit. In FIG. 4, an input signal 5 is given to the phase comparator 1, and the phase comparator 1 compares the input signal 5 with the output signal 6 of the voltage controlled oscillator (VCO) 4 to detect a phase error, An error signal is given to the charge pump circuit 2. The charge pump circuit 2 supplies a current corresponding to the phase error signal to the loop filter 3, and the loop filter 3 removes unnecessary frequency components such as input noise and phase jitter and supplies the voltage controlled oscillator 4. Voltage controlled oscillator 4
Oscillates a signal having a frequency corresponding to the output of the loop filter 3 and outputs it as an output signal 6, and the phase comparator 1
Give feedback to.

The operation of the PLL circuit shown in FIG. 4 will be described in more detail. The input signal 5 and a part of the output signal 6 of the voltage controlled oscillator 4 oscillating at the free-running frequency are phased by the phase comparator 1. It is compared and a phase error signal is output. This phase error signal is converted into a current by the charge pump circuit 2 and given to the loop filter 3, noise and phase jitter components superimposed on the input signal 5 are removed and given to the control input of the voltage controlled oscillator 4. Since the output signal 6 of the voltage controlled oscillator 4 is supplied to the phase comparator 1, this circuit forms a loop, and the lock state is established when the phases of the input signal 5 and the output signal 6 match. The bandwidth of the loop filter 3 is determined by the balance between the amount of residual noise during tracking in the locked state and the response speed.

By the way, in the PLL circuit, when noise is superimposed on the input signal or phase jitter is superimposed, the loop also follows these disturbances, so that frequency noise is generated. In order to reduce this, it is necessary to narrow the bandwidth of the loop filter, but this has the disadvantage that the transient response becomes slow and the time required for phase locking of the loop becomes long.

In order to avoid such drawbacks, FIG.
A method as shown in FIGS. 6 and 7 has been proposed.

FIG. 5 is proposed in Japanese Patent Laid-Open No. 61-87427, and among the PLL circuits shown in FIG.
A wide band loop filter 7 and a narrow band loop filter 8 are provided in place of the loop filter 3, and these can be switched by switch circuits 9 and 10. And
When the channel is switched, a wide band filter 7 is used to realize a high-speed response, and when the channel is locked, a narrow band filter is switched to realize low noise.

The example shown in FIG. 6 is disclosed in JP-A-62-1991.
This is described in Japanese Patent Publication No. 19 and uses one loop filter 3, and a resistor 3 included in the loop filter 3 is used.
The switch circuit 32 is connected to both ends of the switch circuit 1.
By switching 2 the time constant of the loop filter 3 is switched to achieve high speed lock and low noise.

The example shown in FIG. 7 is disclosed in Japanese Unexamined Patent Publication No. 62-9252.
It is described in Japanese Patent No. 1 Publication No. 1 and realizes high-speed response by increasing the charge pump current of the charge pump circuit 2 at the time of channel switching, and realizes low noise by setting the charge pump current to a normal level at the time of locking. is there.

[0010]

However, in the example shown in FIG. 5 described above, if the wide band loop filter 7 comes close to the lock and then the narrow band loop filter 8 is switched to, the narrow band loop filter immediately before switching is obtained. The voltage is pushed back to the vicinity of the output voltage of 8, and then the state of locking due to the response of the narrow band loop filter 8 is generated, so that there is almost no advantage of using the wide band filter 7. Further, in FIG. 6, since the capacitor is charged through the resistor, there is a drawback that the channel switching speed cannot be greatly improved. The example shown in FIG. 7 also has a drawback that a great improvement in channel switching speed cannot be expected as in the resistance switching method.

Therefore, a main object of the present invention is to provide a PLL circuit capable of realizing a high-speed response by rapidly charging a capacitor forming a loop filter to a voltage equal to a voltage in a locked state. Is to provide.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an output signal of a phase comparator for detecting a phase error between an input signal and an output signal of a voltage controlled oscillator to a charge pump and a loop. In a PLL circuit connected to input to a voltage controlled oscillator via a filter, another charge pump that rapidly charges and discharges a capacitor provided in a loop filter, and another charge pump that is used when switching the oscillation frequency are provided. It is characterized by further comprising a switching means.

[0013]

In the PLL circuit according to the present invention, the charge pump circuit is connected to each of the capacitors forming the loop filter in addition to the normal charge pump circuit connected to the loop filter, and the charge pump is switched at the time of channel switching. By the means, the capacitor is charged at high speed to realize a high speed response. Further, by adjusting the charging current to each capacitor according to the capacitance of the capacitor, the rise of the voltage of each capacitor can be made uniform, which is most effective.

[0014]

1 is a block diagram showing a first embodiment of the present invention. 1, the phase comparator 1, the charge pump circuit 2, and the voltage controlled oscillator 4 are configured in the same manner as in FIG. 4, but in addition to the charge pump circuit 2, two charge pump circuits 21 and 22 and a charge pump switching circuit are provided. Means 50 are provided. The error signal from the phase comparator 1 is input to the charge pump circuit 2, the error signal from the phase comparator 1 and the external control signal 40 are input to the charge pump switching means 50, and the output of the charge pump switching means 50 is It is input to the charge pump circuits 21 and 22. The loop filter 30 is composed of resistors 33, 34 and 35 and capacitors 36 and 37. Resistors 33 and 34
Is connected in series between the output end of the charge pump circuit 2 and the input end of the voltage controlled oscillator 4, and the capacitor 36 is connected between the input end of the voltage controlled oscillator 4 and the ground, and is connected to the input end of the voltage controlled oscillator 4. The output of the charge pump circuit 21 is connected. Further, a series circuit of a resistor 35 and a capacitor 37 is connected between the connection point between the resistors 33 and 34 and the ground, and an output of the charge pump circuit 22 is connected at a connection point between the resistor 35 and the capacitor 37.

The operation of the embodiment shown in FIG. 1 will be described. Similar to the description of FIG. 4, the lock state is established when the output signal 6 of the voltage controlled oscillator 4 and the input signal 5 are in phase with each other. . In the locked state, the potential difference across the capacitors 36 and 37 in the loop filter 30 becomes a constant voltage determined by the set frequency. In general,
This constant voltage is the voltage controlled oscillator 4 corresponding to the set frequency.
Equal to the input voltage of. In the first embodiment of the present invention,
By turning on the charge pumps 21 and 22 by the charge pump switching means via the external control signal 40 and quickly charging the capacitors 36 and 37 until a constant voltage determined by the set frequency is reached, high-speed lock becomes possible. After locking, the charge pump circuits 21 and 22 connected to the capacitors 36 and 37 are turned off, and the normal lock state (low noise lock state) is set.

FIG. 2 is a concrete block diagram showing the main part of the first embodiment of the present invention. In FIG. 2, charge pump circuits 2, 21 and 22 are respectively provided with a transistor 23.
And 24, 25 and 26, 27 and 28. One output of the phase comparator 1 is given to the base of the transistor 23, and the other output is given to the base of the transistor 24. Further, in order to switch whether or not to give the respective outputs of the phase comparator 1 to the charge pump circuits 21 and 22, an inverter 11, an OR gate 12 and an AN are provided.
A switching circuit including the D gate 13 is provided. The external control signal 40 is given to one input end of the AND gate 13, inverted by the inverter 11, and given to one input end of the OR gate 12. One output of the phase comparator 1 is applied to the other input terminal of the OR gate 12,
The other input of the gate 13 is supplied with the other output of the phase comparator 1. The output of the OR gate 12 is the transistor 25.
And 27 and the output of AND gate 13 is provided to the bases of transistors 26 and 28.

FIG. 8 and FIG. 9 are waveform charts of the respective parts of FIG. 2, and FIG. 10 is a diagram showing the response characteristics of the first embodiment of the present invention and the conventional example in comparison.

Next, a specific operation of the first embodiment of the present invention will be described with reference to FIGS. 1, 2 and 8 to 10. First, the change in the direction of increasing the input voltage of the voltage controlled oscillator 4 has a waveform as shown in FIG. That is, when the channel is switched, the external control signal 4 shown in FIG.
When 0 becomes the “H” level for a certain period as shown in FIG. 8A, the AND gate 13 is opened. In addition, the external control signal 40 is inverted by the inverter 11, and as shown in FIG.
As shown in, the OR gate 12 is opened at the "L" level. Therefore, the output signals of the phase comparator 1 shown in FIGS.
The signals are gated by the ND gate 13 and given to the transistors 25, 26, 27 and 28 of the charge pump circuits 21 and 22 as signals shown in FIGS. 8E and 8F, and these transistors 25 to 28 are turned on. Alternatively, it is turned off and the charge pump circuits 21 and 22 are activated. At this time, the charge pump circuit 21 rapidly charges the capacitor 36 according to the output signal of the phase comparator 1 as shown in FIG.
Charge 7 quickly.

After that, when the external control signal 40 goes to "L" level, the OR gate 12 and the AND gate 13 are closed, and the transistors 25, 26, 27 and 28 of the charge pump circuits 21 and 22 are turned off. Therefore, the outputs of the charge pump circuits 21 and 22 are in a high impedance state, and the low noise mode in which only the charge pump circuit 2 operates is set.

Similarly, the operation of each part in the direction of decreasing the input voltage of the voltage controlled oscillator 4 has a waveform as shown in FIG. As described above, the charge pump circuit 21 is directly connected to the capacitor 36 and the charge pump circuit 22 is connected to the capacitor 37.
As shown in (a), a much faster response can be realized as compared with the conventional method of charging through a resistor (FIG. 10 (b)).

If the charging speeds of the capacitors 36 and 37 are varied, the one having the slowest charging speed is affected. Therefore, in order to suppress the variation of the charging speed, the charge pump current is changed according to the capacitance of the capacitors 36 and 37. It will be more effective if it can be set.

FIG. 3 shows a PLL showing a second embodiment of the present invention.
It is a block diagram of a circuit, and the same code | symbol is attached | subjected to the same element as the element of FIG.

In the second embodiment, in the loop circuit composed of the phase comparator 1, the charge pump circuit 2, the loop filter 30 and the voltage controlled oscillator 4 of FIG. 1, the output side of the voltage controlled oscillator 4 and the phase comparator 1 are connected. A frequency divider 50 is provided between the input side and the input side.

When the output signal 6 from the voltage controlled oscillator 4 is input to the frequency divider 60, the frequency of the output signal 6 changes according to the set frequency division ratio. The output signal 61 of the frequency divider 60 is input from the input side of the phase comparator 1, and the input signal 5
Then, the same operation as that of the first embodiment is performed thereafter. Therefore, the operation waveform is similar to that of the first embodiment, and is as shown in FIGS. When the frequency divider 60 is used, the oscillation frequency can be set in a wider range as compared with the first embodiment shown in FIG. 1, and it is suitable for setting a high frequency.

[0025]

As described above, according to the present invention, at least two charge pump circuits are provided and one of the charge pump circuits rapidly charges the loop filter capacitor in the high speed mode. A high-speed response can be realized, and a sufficient noise suppression effect can be obtained after locking.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a first embodiment of the present invention.

FIG. 2 is a specific block diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a schematic block diagram of a second embodiment of the present invention.

FIG. 4 is a schematic block diagram of a conventional basic PLL circuit.

FIG. 5 is a block diagram showing a conventional PLL circuit configured to switch between a wide band loop filter and a narrow band loop filter.

FIG. 6 is a block diagram of a conventional PLL circuit in which a time constant of a loop filter is switched.

FIG. 7 is a block diagram of a conventional PLL circuit configured to control a charge pump current given to a charge pump circuit.

FIG. 8 is a waveform chart of each part of FIG. 2, and particularly shows the operation in the direction of increasing the input voltage of the voltage controlled oscillator.

FIG. 9 is a waveform diagram of each part of FIG. 2, showing a case where the voltage controlled oscillator operates in a direction of decreasing the input voltage.

FIG. 10 shows the first and second embodiments of the present invention and the conventional P.
It is a figure which compares and shows the response characteristic of a LL circuit.

[Explanation of symbols]

 1 Phase Comparator 2, 21, 22 Charge Pump Circuit 4 Voltage Controlled Oscillator 11 Inverter 12 OR Gate 13 AND Gate 23-28 Transistor 30 Loop Filter 33, 34, 35 Resistor 36, 37 Capacitor 50 Charge Pump Switching Means 60 Frequency Divider

Claims (1)

[Claims] 1. An output signal of a phase comparator for detecting a phase error between an input signal and an output signal of the voltage controlled oscillator is connected to the voltage controlled oscillator via a charge pump and a loop filter. The PLL circuit further comprises another charge pump that rapidly charges and discharges the capacitor provided in the loop filter, and means that switches the other charge pump when switching the oscillation frequency.