JPH06268220A - Thin film transistor - Google Patents

Abstract

PURPOSE:To lessen the leakage current generating between a source and a drain, and to improve OFF-current characteristics in a thin film transistor(TFT). CONSTITUTION:(1) A source electrode 4S formed on an insulative substrate 1, an operating semiconductor layer 7C formed on the substrate covering the source electrode, and a drain electrode 10D, formed on the operating semiconductor layer leaving a space between the source electrode and the face direction, are provided. (2) The source electrode 4S and the drain electrode 10D are formed in parallel with each other in a rod-like form. (3) The substrate 1 is transparent, and the operating semiconductor layer 7 is interposed among the substrate, the drain electrode 10D and a drain buss.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to thin film transistors. In recent years, thin film transistors have been used as driving elements for liquid crystal displays and electroluminescence displays.
(TFT) is used. In TFTs, it is important to miniaturize the device in order to improve the display image quality and increase the aperture ratio by reducing the parasitic capacitance. Therefore, it is effective to shorten the TFT channel length.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional stagger type short channel TFT.
FIG. A light-shielding film 21 made of chromium (Cr) or the like is formed on a transparent insulating substrate 20 such as glass, and a transparent conductive film, such as a transparent conductive film, is formed on the light-shielding film 21 made of silicon dioxide (SiO ₂ ) film or the like. A source electrode 23S and a drain electrode 23D are formed of an ITO (indium tin oxide) film.

An insulating film is formed on the source electrode 23S and the drain electrode 23D via contact layers 24S and 24D, respectively.
An operating semiconductor layer 25, a gate insulating film 26 made of a silicon nitride (SiN) film or the like, and a gate electrode 27 made of aluminum (Al) or the like are sequentially stacked on the layer 22.

[0004]

In the TFT having the conventional structure as described above, the width of the film interface 28 where the operating semiconductor layer 25 and the insulating film 22 are in contact with each other becomes narrower as the channel becomes shorter. Leakage current easily occurs between the TFT and
However, there was a problem that the OFF current characteristic of was deteriorated. In addition,
The same problem occurred in the inverted staggered TFT.

An object of the present invention is to reduce the leak current between the source / drain and improve the OFF current characteristic of the TFT.

[0006]

Means for Solving the Problems To solve the above problems, 1) a source electrode 4S formed on an insulating substrate 1 and an operating semiconductor layer formed on the substrate covering the source electrode 4S.
7C and a thin film transistor having a drain electrode 10D formed on the operating semiconductor layer with a space between the source electrode and the source electrode, or 2) the shapes of the source electrode 4S and the drain electrode 10D are parallel to each other. And the substrate 1 is a transparent substrate, and the operating semiconductor layer 7C is interposed between the substrate and the drain electrode 10D and the drain bus. This is achieved by the thin film transistor described in 1) or 2) above.

[0007]

1 (A) and 1 (B) are explanatory views of the principle of the present invention. 1 (A) is a perspective view, and FIG. 1 (B) is a sectional view taken along line AA.

In the figure, 1 is a transparent insulating substrate, 2 is a light-shielding film, 3 is an insulating film, 4S is a source electrode (pixel electrode), 4DB is a drain bus line, 5S is a source side contact layer, and 7C is an operating semiconductor layer. , 8B is a drain side contact layer, 10D is a drain electrode, and 13 is a gate electrode.

In the present invention, the source electrode 4S and the drain electrode
Since 10D is arranged so as to have a space in the plane direction and to sandwich the operating semiconductor layer 7C, the operating semiconductor layer 7C and the insulating film 3 between the source electrode 4S and the drain electrode 10D are formed even if the channel is shortened.
By keeping the length of the film interface 29 with and sufficiently long, the leak current is suppressed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2A to 2G are sectional views for explaining an embodiment (1) of the present invention. In FIG. 2 (A), a Cr film is deposited on a transparent insulating substrate 1 such as glass by about 1000 Å by a sputtering method, and patterned at a predetermined position and shape to form a light shielding film 2.

Then, as the transparent insulating film 3, a SiO ₂ film is deposited on the entire surface of the substrate by plasma vapor deposition (CVD) to a thickness of about 6000 liters. Further, a transparent conductive film 4 such as ITO is deposited thereon by sputtering, for example, 500 Å.

Next, the thickness of 100
An n ⁺ -Si layer having a thickness of about 100 Å is grown as the Å n ⁺ type semiconductor layer 5. The growth conditions were the concentration of PH ₃ as the source gas.
Using this and SiH ₄ / H ₂ to about 1%, gas pressure 1.0
Torr, substrate temperature 350 ℃, applied power 50W.

Next, a photoresist is applied on the substrate,
Mask for patterning and covering the source and drain electrodes 6
Form S, 6D. In Fig. 2 (B), masks 6S, 6DB
Using the as an etching mask, the exposed n ⁺ type semiconductor layer 5
Is dry-etched with a CCl ₄ -based gas, and then the transparent conductive film 4 is selectively removed with a chlorine-based etching solution, and the transparent conductive films 4S, 4DB and n ^{+ are} added to the source region and the drain bus line region. The type semiconductor layers 5S and 5DB are left.

The transparent conductive film 4S serves as a source electrode, and the transparent conductive film 4DB serves as a drain bus line. As shown in FIG. 1A, by making the source electrode 4S elongated, the leak current from the side surface of the operating semiconductor layer on the source electrode can be reduced.

Next, the masks 6S and 6DB are removed. Figure 2
In (C), an i-Si layer with a thickness of approximately 300Å is grown as the i-type semiconductor layer 7 that will become the operating semiconductor layer by the plasma CVD method. The growth conditions were 20% diluted SiH ₄ / H as the source gas.
₂ , flow rate 200 SCCM, gas pressure 0.3 Torr, substrate temperature
The temperature is 250 ° C and the applied power is 30 W. Successively, similar to the process of FIG. 2B, the n ⁺ type semiconductor layer 8 has a thickness of about 100 Å n ⁺
-Grow Si layer.

Next, a resist mask 9 is formed on the operating semiconductor region by using photolithography. In FIG. 2D, the n ⁺ type semiconductor layer 8, the i type semiconductor layer 7 and the n ⁺ type semiconductor layer 7
The i-type semiconductor layer 5DB is dry-etched using a CCl ₄ -based gas, and the i-type semiconductor layer 7 is separated into islands to form the operating semiconductor layer 7C.
And the contact layer 8A is formed.

In FIG. 2 (E), a drain electrode film is formed on the entire surface of the substrate by a sputtering method, for example, C having a thickness of 500Å.
r film 10 is deposited. At this time, not only the Cr film but also the ITO film may be deposited similarly to the formation of the source and drain buses.
In this case, the resist pattern that is removed only in the drain electrode portion is used, and the region other than the drain electrode portion is removed by the lift-off process.

In FIG. 2 (F), the Cr film 10 is selectively removed by a chlorine-based etching solution to remove the drain bus line 4DB.
A drain electrode 10D connected to is formed. At this time, as shown in FIG. 1 (A), the contact surface between the drain electrode 10D and the film interface 29 is formed into an elongated rod shape so that the contact between the operating semiconductor layer 7C and the film interface 29 formed by the insulating layer 3 is formed. The contact area becomes smaller and the leak current due to the film interface decreases.

Further, the n ⁺ type semiconductor layer 8A on the operating semiconductor layer 7C is etched using a CCl ₄ -based gas to form a drain side contact layer 8D. In Fig. 2 (G), the thickness of the gate insulating film 12 is formed on the substrate by the plasma CVD method.
Grow 3000 Å silicon nitride (SiN _x ) film. The growth conditions were 20% diluted SiH ₄ / H ₂ and NH ₃ gas as the source gas, each flow rate 200 SCCM, gas pressure 1.0 T.
Orr, substrate temperature 250 ℃, applied power 300 W.

Then, an aluminum (Al) film having a thickness of about 600 Å is deposited on the entire surface of the substrate by the sputtering method and patterned to form the gate electrode 13 on the operating semiconductor layer 7A.
3 (A) to 3 (G) are sectional views for explaining an embodiment (2) of the present invention.

This example has a structure in which the operating semiconductor layer 7C is interposed between the drain electrode 10D and the drain bus line 4DB and the transparent insulating substrate.

In FIG. 3 (A), a Cr film is deposited on a transparent insulating substrate 1 such as glass by a sputtering method to a thickness of about 1000Å,
The light shielding film 2 is formed by patterning at a predetermined position and shape. Then, as a transparent insulating film 3, a SiO ₂ film is deposited on the entire surface of the substrate by the plasma CVD method at about 6000 liters. Further, a transparent conductive film 4 such as ITO is deposited thereon by sputtering, for example, 500 Å.

Next, a plasma CVD method is performed to obtain a thickness of 100
An n ⁺ -Si layer having a thickness of about 100 Å is grown as the Å n ⁺ type semiconductor layer 5. The growth conditions were the concentration of PH ₃ as the source gas.
Using this and SiH ₄ / H ₂ to about 1%, gas pressure 1.0
Torr, substrate temperature 350 ℃, applied power 50W.

Next, a photoresist is applied on the substrate,
Patterning is performed to form a mask 6S that covers the source electrode. In FIG. 3 (B), using the mask 6S as an etching mask, the exposed n ⁺ type semiconductor layer 5 is dry-etched using a CCl ₄ -based gas, and then the transparent conductive film 4 is selected by a chlorine-based etching solution. And the source electrode 4S made of a transparent conductive film and the source side contact layer 5S made of an n ⁺ type semiconductor layer are left in the source region. At this time, by making the shape of the source electrode 4S elongated as shown in FIG. 1A, the leakage current from the side surface of the operating semiconductor layer on the source electrode can be reduced.

Next, the mask 6S is removed. In Fig. 3 (C), the plasma CVD method is used to form the active semiconductor layer i
An i-Si layer having a thickness of about 300Å is grown as the type semiconductor layer 7.
The growth conditions were 20% diluted SiH ₄ / H ₂ as the source gas, flow rate 200 SCCM, gas pressure 0.3 Torr, substrate temperature 250.
℃, applied power 30 W. Continuously, as in the process of FIG. 3B, the n ⁺ -type semiconductor layer 8 has a thickness of about 100 Å n ⁺ -Si.
Grow layers.

Next, a resist mask 9A is formed on the operating semiconductor region by using photolithography. In FIG. 3 (D), the n ⁺ type semiconductor layer 8 and the i type semiconductor layer 7 are CCl ₄
I-type semiconductor layer 7
Remains in the drain bus line region and the operating semiconductor layer 7C
And the contact layer 8A is formed.

In FIG. 3 (E), a drain electrode film is formed on the entire surface of the substrate by a sputtering method, for example, with a thickness of 500 Å.
l Deposit the film 10. Next, a resist mask 11A is formed by photolithography so as to cover the drain electrode and the drain bus region.

At this time, the drain electrode film is not limited to the Al film, and another metal film having high conductivity may be used. Figure 3
At (F), the Al film 10 is selectively removed by an etching solution to form a drain electrode and a drain bus line 10D.

Further, the n ⁺ type semiconductor layer 8A on the operating semiconductor layer 7C is etched using a CCl ₄ -based gas to form a contact layer 8D on the drain side. In Fig. 3 (G), the thickness of the gate insulating film 12 is formed on the substrate by the plasma CVD method.
Grow 3000 Å silicon nitride (SiN _x ) film. The growth conditions were 20% diluted SiH ₄ / H ₂ and NH ₃ gas as the source gas, each flow rate 200 SCCM, gas pressure 1.0 T.
Orr, substrate temperature 250 ℃, applied power 300 W.

Then, an Al film having a thickness of about 600 Å is deposited on the entire surface of the substrate by the sputtering method and patterned to form the gate electrode 13 on the operating semiconductor layer 7A. With the above structure, the drain electrode and the film interface 29 are not in contact with each other.
There is no increase in leakage current due to 29, and the TFT device can be miniaturized.

FIG. 4 is an explanatory view showing the effect of the present invention.
The figure shows the drain current I (A) with respect to the gate voltage V _g (V).
It is an actual measurement value indicating the relationship. In the embodiment, the OFF current characteristic of the gate voltage of 0 V or less is improved by almost two digits as compared with the conventional example.

Further, it can be seen from FIG. 4 that g _m is equivalent to that of the conventional example, because the channel is formed in the thickness direction of the operating semiconductor layer having a thickness of 300 Å.

[0033]

According to the present invention, the leak current between the source / drain can be reduced and the OFF current characteristic of the TFT can be improved. Furthermore, since the channel formed in the operating semiconductor layer and the drain electrode are close to each other, the ON current characteristics of the TFT can be improved.

As a result, a clear and stable image can be obtained in the TFT driven display, which can contribute to the improvement of the display performance.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a sectional view illustrating an embodiment (1) of the present invention.

FIG. 3 is a sectional view illustrating an embodiment (2) of the present invention.

FIG. 4 is an explanatory diagram showing the effect of the present invention.

FIG. 5: Cross-sectional view of conventional staggered short channel TFT

[Explanation of symbols]

1 Transparent insulating substrate 2 Light shielding film 3 Insulating film 4 Conductive film 4S Source electrode 4DB Drain bus line 5 Source electrode film is n ⁺ type semiconductor layer 5S Source side contact layer 6S, 6DB Etching mask 7 i type semiconductor layer 7C Operating semiconductor Layer 8 n ⁺ type semiconductor layer 8D Drain side contact layer 9, 9A Etching mask 10 Drain electrode film n ⁺ type semiconductor layer 10D Drain electrode 11, 11A Etching mask 12 Gate insulating film 13 Gate electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Kakei 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenichi Oki 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (3)

[Claims] 1. A source electrode (4S) formed on an insulating substrate (1), an operating semiconductor layer (7C) formed on the substrate covering the source electrode, and an operating semiconductor layer (7C) on the substrate. The drain electrode (10) formed at a distance from the source electrode in the plane direction.
And D). 2. The source electrode (4S) and drain electrode
The thin film transistor according to claim 1, wherein the shapes of (10D) are parallel to each other and rod-like. 3. The substrate (1) is a transparent substrate, and the operating semiconductor layer (7C) is interposed between the substrate and the drain electrode (10D) and the drain bus. 1. The thin film transistor according to 1 or 2.