JPH06267943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration in reliability upon wiring due to moisture absorption into an interlayer insulating film by a method wherein rugged surfaces are transferred to a gel film formed on a substrate having an electrode by pressing down a stamper and after finishing the heat treating step, a metallic film is deposited on the transferred regions. CONSTITUTION:A conductive film for lower layer wiring is formed on a semiconductor substrate 101 so as to be patterned into a lower layer wiring 102. Next, an organic coated glass film 104 in gel state is formed by spin-coating step. Next, a stamper 106 is pressed down agaist said glass film 104 to transfer the recessed surfaces 111 and 110 corresponding to an upper layer wiring and a connecting hole. Later, the organic coated glass film 104 is set by heat- treating it in nitrogen stream. Furthermore, the lower layer wiring on the bottom part of the connecting hole 110 is completely exposed by etching back step. Finally, after the formation of an aluminum film 114 as another conductive film for upper layer wiring, the aluminum excluding the recessed surface of said glass film 104 is removed so as to turn the aluminum in the recessed surfaces into an upper layer wiring 115.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art A conventional method of manufacturing a semiconductor device is shown in FIGS. First, a conductive film for lower layer wiring is formed on the semiconductor substrate 301, and patterned by using a known dry etching technique to form a lower layer wiring 302 (FIG. 18). Then, a first plasma oxide film 303 is formed (see FIG.
9) After forming an organic coating glass film (organic spin-on glass) 304 for flattening (FIG. 20), the lower wiring 3
Etchback 308 is performed so that the coated glass film 304 does not remain on the upper part of 02 (FIG. 21). Further, a second plasma oxide film 309 is formed (FIG. 22). Next, a connection hole 310 for the upper layer wiring and the lower layer wiring is formed by using a known dry etching technique (FIG. 23). A conductive film for upper layer wiring is formed thereon, and patterned by using a known dry etching technique to form upper layer wiring 315 (FIG. 2).
4).

Here, the organic coating glass film is a general name for a polyorganosiloxane coating film, and is a film in which an alkyl group, an allyl group or the like is bonded as a side group to the main chain of a siloxane bond of silicon and oxygen.

[0004]

The problem with the conventional semiconductor device as described above is that the number of steps is large. Since the three-layered interlayer insulating film structure includes a dry etching process for etching back and forming the contact hole 310 in addition to three times of film formation, the number of processes is considerably larger than that of the single-layered interlayer insulating film structure, It will spur the cost increase.

The reason why the number of steps increases is that the organic coating glass film 304 must be prevented from being deteriorated by the asher process when removing the resist on the plasma oxide film 309 after forming the connection hole 310 and the upper wiring 315. Especially. That is, in the above-described conventional manufacturing method, the plasma oxide films 303 and 30 are formed above and below the organic coating glass film 304.
The upper coating 315 and the lower wiring 302 are sandwiched between the organic coating glass film 304 and the organic coating glass film 304 so that the organic coating glass film 304 does not come into contact with the upper wiring 315 and the lower wiring 302. In the organic coating glass film 304, the surface of the organic coating glass is made hydrophobic by the organic group and the amount of contained water is reduced, so that the hygroscopicity is low and usually contains almost no water.
In the step of removing the resist, oxygen plasma treatment (asher treatment) in a barrel type dry etching device is performed.
As a result, the organic groups are removed to contain water. The moisture that is absorbed from the organically coated glass film 304 reduces the reliability of the wiring. Therefore, if there is no step of removing the resist described above, it is not necessary to use the three-layer interlayer insulating film structure, and the number of steps can be reduced.

An object of the present invention is to form a multi-layered wiring structure in which the reliability of wiring is not deteriorated due to moisture absorption of an interlayer insulating film in a small number of steps.

[0007]

[Means for Solving the Problems] A solution in which an organosiloxane is dispersed in an organic solvent is spin-coated on a substrate to form a gel thin film (organic-coated glass film), and then a stamper is pressed against the gel thin film to form unevenness. After the surface is transferred, it is heat-cured at a temperature of 300 ° C. or higher and 600 ° C. or lower in a nitrogen stream.
Further, the surface of the gel thin film is etched to clean the bottom surface of the concave portion of the gel thin film corresponding to the convex portion of the stamper as needed, and metal is embedded in the concave portion to form wiring.

The stamper has an uneven surface patterned on the surface, and presses this on a gel thin film to transfer the uneven surface to the gel thin film. The material of the stamper needs to be easy to form an uneven surface by microfabrication, have poor adhesiveness to the gel thin film, and be easily peeled off. Examples of such materials include aluminum and tungsten. Alternatively, the surface treatment of the stamper may deteriorate the adhesion to the gel thin film. As an example of such surface treatment, there is a method of forming a Teflon thin film by a sputtering method.

Further, in order to align the uneven surface of the stamper to be transferred with the underlying wiring layer, etc., an alignment mark is formed on the stamper and both the alignment mark and the alignment mark of the semiconductor substrate are used to form the alignment mark. The position is detected and the position is adjusted.

[0010]

According to the present invention, since there is no step of removing the resist, it is not necessary to form a three-layered interlayer insulating film structure, and the number of steps for forming a multi-layered wiring structure using a single-layered interlayer insulating film made of an organic coating glass film is reduced. Can be formed with. By setting the water content in the organic coating glass film to 1% or less, it is possible to prevent the reliability of the wiring from being lowered due to the moisture absorption of the interlayer insulating film (organic coating glass film).

[0011]

【Example】

<Embodiment 1> An embodiment of a method for manufacturing a semiconductor device according to the present invention is shown in FIGS. First, a conductive film for lower layer wiring having a thickness of 0.5 μm is formed on the semiconductor substrate 101, and patterned by using a known dry etching technique to form the lower layer wiring 1.
02 (Fig. 1). Then, a gel-like organic coating glass film 104 was formed by spin coating. This organic coated glass has an organic group concentration of 10% by weight or more,
The water content was 1% or less. Organic coated glass film 10
The film thickness of 4 is 1.5 μm (FIG. 2). Next, the stamper 106 was pressed against the organic coating glass film 104 with a load of 2 Pa (FIG. 3), and the concave surfaces 111 and 110 having a depth of 0.5 μm and 1.0 μm corresponding to the upper layer wiring and the connection hole were transferred. Then, heat treatment was performed at 450 ° C. for 30 minutes in a nitrogen stream to cure the organic coating glass film 104. Further, etching back was performed in a parallel plate type dry etching apparatus to completely expose the lower layer wiring at the bottom of the connection hole (FIG. 4). Then, as a conductive film for upper wiring, the thickness is 0.5 μm.
Was formed by the CVD method (FIG. 5). Further, by chemical mechanical polishing, aluminum other than the concave surface of the organic coating glass film 104 is removed,
Aluminum in the concave surface was used as the upper wiring 115 (FIG. 6).

In the stamper used in this embodiment, aluminum 406 having a thickness of 2 μm is formed on a quartz substrate 416 by a sputtering method, and the aluminum 406 is patterned by a known dry etching technique to have a convex surface. (Fig. 25). On this stamper, an alignment mark 417 made of aluminum, which can be confirmed from the back surface through the quartz substrate 416, is formed by the same method as described above. The positions of the alignment mark 417 on the stamper and the alignment mark 418 formed of aluminum on the semiconductor substrate were measured while aligning them. In addition, the organic coating glass film 40
Immediately after spin coating of No. 4, while the semiconductor substrate 401 is still rotating, by spraying methyl alcohol to the end of the semiconductor substrate, the alignment mark 4 on the semiconductor substrate is obtained.
The gel-like organic coating glass film 404 near 18 was removed to prevent the organic coating glass film 404 from contacting the alignment mark 417 on the stamper.

<Embodiment 2> FIGS. 7 to 17 show an embodiment of a method of manufacturing a semiconductor device according to the present invention. The stamper material, manufacturing method, load, and alignment method are the same as in the first embodiment. First, a conductive film for lower layer wiring having a thickness of 0.5 μm was formed on a semiconductor substrate 201, and patterned by a known dry etching technique to form a lower layer wiring 202 (FIG. 7).
Then, a gel-like first organic coating glass film 204 was formed by a spin coating method (FIG. 8). The thickness of this first organic coating glass film 204 was 1.0 μm. A first stamper 206 having a convex surface of 0.5 μm in height is pressed against the first organic coated glass film 204 to form a connection hole 210.
The concave surface corresponding to was transferred (FIG. 9). The position of the stamper was the same as in Example 1. 80 ° C
After heat treatment in air for 3 minutes at 180 ° C for 3 minutes,
Heat treatment was performed at 450 ° C. for 30 minutes in a nitrogen stream to cure the first organic coated glass film 204. Further, etching back was performed in a parallel plate type dry etching apparatus to completely expose the lower layer wiring at the bottom of the connection hole (FIG. 10). Then, an aluminum film having a thickness of 0.5 μm was formed as the conductive film 212 for plugs by the CVD method (FIG. 11). Further, by chemical mechanical polishing, aluminum other than inside the connection hole 210 was removed to form a plug 213 (FIG. 12). Then, a gel-like second organic coating glass film 205 was formed by a spin coating method (FIG. 13). The thickness of the second organic coating glass film 205 was 0.5 μm. The second organic coated glass film 205 is aligned in the same manner as in Example 1 and a second stamper 207 having a convex surface of 0.5 μm in height is pressed (FIG. 14) to form a concave surface 211 corresponding to the upper layer wiring. It was transcribed. 3 minutes at 80 ℃,
After heat treatment in air at 180 ° C. for 3 minutes, heat treatment was performed at 450 ° C. for 30 minutes in a nitrogen stream to cure the second organic coating glass film 205. Further, the etch back 208 is performed in the parallel plate type dry etching apparatus to remove the plug 2
The upper part of 13 was completely exposed (FIG. 15). Then, an aluminum film having a thickness of 0.5 μm was formed as the upper layer conductive film 214 by the CVD method (FIG. 16). Further, the concave surface 21 corresponding to the upper wiring is formed by the chemical mechanical polishing method.
The aluminum other than 1 was removed, and the upper layer wiring 215 was formed (FIG. 17).

The organic group content of the organic coating glass film used in Examples 1 and 2 is 19% by weight. The water content of this organic coated glass was less than 0.3%, and the water content did not adversely affect the wiring. Further, in the first and second embodiments, aluminum is used as the upper layer wiring and the plug, but copper or tungsten formed by the CVD method can also be used to manufacture the same. When the concave aspect to be transferred to the organic coating glass film has a small aspect ratio, it was possible to similarly manufacture using any of aluminum, aluminum alloy, copper, and copper alloy formed by the sputtering method or the bias sputtering method. . Also,
The upper layer wiring and the plug may be a laminated film of any one of aluminum, aluminum alloy, copper, and copper alloy and another conductive material. When the concave surface of the organic coating glass film was completely filled with the conductive film, the upper layer wiring could be formed by using the etchback method instead of the chemical mechanical polishing method. The side wall of the uneven surface of the stamper was able to transfer the pattern sufficiently even if it was nearly vertical, but when the taper was forward tapered, it could be transferred more satisfactorily.

[0015]

According to the present invention, a single-layer interlayer insulating film structure is formed, and a multilayer wiring structure in which the reliability of the wiring is not deteriorated by moisture absorption of the insulating film can be formed in a small number of steps, which contributes to the suppression of manufacturing cost. To do.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 5 is a sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process showing the first embodiment of the present invention.

FIG. 7 is a sectional view of a manufacturing process showing a second embodiment of the present invention.

FIG. 8 is a manufacturing process sectional view showing a second embodiment of the present invention.

FIG. 9 is a sectional view of a manufacturing process showing a second embodiment of the present invention.

FIG. 10 is a sectional view of a manufacturing process showing a second embodiment of the present invention.

FIG. 11 is a manufacturing step sectional view showing Embodiment 2 of the present invention.

FIG. 12 is a sectional view of a manufacturing process showing a second embodiment of the present invention.

FIG. 13 is a manufacturing step sectional view showing Embodiment 2 of the present invention.

FIG. 14 is a manufacturing step sectional view showing Embodiment 2 of the present invention.

FIG. 15 is a sectional view of a manufacturing process showing a second embodiment of the present invention.

FIG. 16 is a manufacturing step sectional view showing Embodiment 2 of the present invention.

FIG. 17 is a manufacturing step sectional view showing Embodiment 2 of the present invention.

FIG. 18 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 19 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 20 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 21 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 22 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 23 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 24 is a process sectional view showing the method of manufacturing a conventional semiconductor device.

FIG. 25 is a sectional view showing a stamper used in Examples 1 and 2 of the present invention.

[Explanation of symbols]

101, 201, 301, 401 ... Semiconductor substrate, 10
2, 202, 302 ... Lower layer wiring, 303 ... First plasma oxide film, 104, 304, 404 ... Organic coated glass film, 204 ... First organic coated glass film, 205 ... Second organic coated glass film, 106 , 406 ... Stamper, 206
… The first stamper, 207… The second stamper, 108,
208, 308 ... Etch back, 309 ... Second plasma oxide film, 110, 210, 310 ... Connection hole, 111,
211 ... Recesses corresponding to the projections of the stamper, 212 ... Conductive film for plugs, 213 ... Plugs, 114, 214, 314
... conductive film for upper layer wiring, 115, 215, 315 ... upper layer wiring, 416 ... quartz substrate for stamper, 417 ... alignment mark on stamper substrate, 418 ... alignment mark on semiconductor substrate.

Claims (6)

[Claims] 1. A first step of forming a gel thin film on a substrate having an electrode, a second step of pressing the uneven surface of a stamper against the gel thin film to transfer the uneven surface, and a heat treatment for the gel thin film. And a fourth step of depositing a metal film on a region of the stamper to which the convex portions of the stamper have been transferred, the manufacturing method of the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the gel thin film is formed by spin coating. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching at least a part of the gel thin film after the third step. Method. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the material of the gel thin film is organic coated glass. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the temperature of the heat treatment is 300 ° C. or higher and 600 ° C. or lower. 6. The semiconductor device manufacturing method according to claim 1, wherein the metal film contains at least one of aluminum, aluminum alloy, copper, copper alloy, and tungsten. Device manufacturing method.