JPH06267203A - Detecting device for reproduced data - Google Patents

Abstract

PURPOSE:To improve an error rate for random errors by correcting bit errors making the most of a feature of this code fully, in reproducing data of a recorded code recorded as data bits whose inversion interval is 2 or more. CONSTITUTION:Input data D11 is converted into a NRZI code D12 by a pre- coder 11 in a recording side, and recorded as data bits whose inversion interval is 2 or more. After a reproducing head output signal D13 is detected as a reproduced signal D14 of a binary level (-1, 1) by a partial response PR (1, 1) equalization processing in a PR (1, 1) equalizer 12 in a reproducing side, viterbi decoding is performed according to a rule of binary four state transition in a viterbi decoder 13 and reproduced output data D15 is sent out. In this case, the rule of binary four state transition uses a feature in which (1) and (-1) of a binary reproduced signal D14 is surely continued with two bits or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction data detecting device applied to a digital VTR device, an optical disk device and the like, and more particularly to reproducing data for reproducing recorded data by converting a recording code into a data bit having an inversion interval of 2 or more. Regarding a detection device.

[0002]

2. Description of the Related Art Conventionally, when recording and reproducing high density digital data, as shown in FIGS. 11 and 12, on the recording side, input data D31 is recorded by an NRZI by a precoder 31.
It is converted and recorded as a recording code D32, and on the reproducing side, P
The reproducing head output signal D in the R (1,1) equalizer 32
After detecting 33 as a ternary reproduction signal D34 by the partial response PR (1,1) equalization processing, the Viterbi decoder 33 performs Viterbi decoding in the ternary binary state to convert the ternary reproduction signal D34 including noise from The reproduction output data D35 is determined and output. By using such a device, bit errors are corrected and the error rate for random errors is improved.

Here, the PR (1,1) equalizer 32 outputs "..., 0, ..." for the isolated pulse "..., 0,1,0, ...".
1, 1, 0, ... ”, and the signal waveform is shaped by utilizing intersymbol interference. The reproduction signal D33 detected as a differential waveform by the magnetic head is converted into a three-level signal D.
Convert to 34.

Further, when the Viterbi decoder 33 violates a state transition rule uniquely determined by an input, the Viterbi decoder 33 detects the state of the violation, estimates the most probable state transition, corrects a random error, and decodes it. .

FIG. 13 is a state transition diagram in Viterbi decoding in the ternary binary state. Here, in the state S0, "-
When "1" is input, it transits to state S0 and outputs "0". When "0" is input in state S0, it transits to state S1 and outputs "1" and "0" in state S1. Indicates that when "1" is input, the state transitions to state S0 and "1" is output, and when "1" is input in state S1, the state transitions to state S1 and "0" is output.

[0006]

The above-mentioned PR (1,
1) In the method adopting equalization and three-value two-state Viterbi decoding, bit error correction is performed by using the correlation due to the output signal of PR (1,1) equalization being three-valued, and reproduced data is detected. There is. However, when the recording side converts the code into a code having an inversion interval of 2 or more and records it, that is, when the recorded data bit “1” or “0” is always 2 bits or more, the inversion interval is 2 or more. Since it is not possible to perform bit error correction that makes full use of the feature of (3), the error rate for random errors cannot be further improved.

An object of the present invention is to improve the error rate against random errors by making full use of the characteristics of this code in data reproduction of a recording code recorded as data bits having an inversion interval of 2 or more, and performing bit error correction. An object of the present invention is to provide a reproduction data detecting device that can perform such reproduction.

[0008]

According to another aspect of the present invention, there is provided a reproduction data detecting device for recording a reproduction code of a recording code for NRZI converting input data and recording the data as a data bit having an inversion interval of 2 or more. It comprises means for receiving an output signal and converting it into a binary signal by partial response equalization, and means for performing Viterbi decoding according to four transition rules of the reproduction state according to the binary signal. Value signal level is "-1", "1"
When the four reproduction states are S0, S1, S2, and S3, when "-1" is input in the state S0, the state transits to the state S0 and the reproduction data "0" is output, and in the state S0, "1" is output.
Is input, the reproduction data "1" is output and the reproduction data "1" is output. When "1" is input in the state S1, the reproduction data "0" is output and "1" is output in the state S2. Is input, the reproduction data "0" is output and the reproduction data "0" is output. When "-1" is input in the state S2, the reproduction data "1" is output and "-" is output in the state S3. 1 "
Is inputted, the state is changed to the state S0 and the reproduction data “0” is outputted.

Further, the reproducing data detecting device of the present invention is a reproducing data detecting device of a recording code for directly recording input data consisting of data bits having an inversion interval of 2 or more, and receiving a reproducing head output signal of the recording code. Means for converting to a ternary signal by partial response equalization,
Means for performing Viterbi decoding according to transition rules of four reproduction states according to the ternary signal, wherein the transition rules are:
When the levels of the ternary signal are "-1,""0," and "1" and the four reproduction states are S0, S1, S2, and S3, when "-1" is input in the state S0, the state S0 is input. When "0" is input in the state S0, the reproduction data "0" is output, and the reproduction data "1" is output in the state S1. When "1" is input in the state S1, the state S2 is input. When the state transitions to, the reproduction data "1" is output, and when "1" is input in the state S2, the state transitions to the state S2, the reproduction data "1" is output, and when the state "0" is input, the state S3. The reproduction data "0" is output after transitioning to "0" and the reproduction data "0" is output after transitioning to state S0 when "-1" is input in state S3.

[0010]

The present invention will be described below with reference to the drawings. Generally, if the inversion interval of the recorded data bits is 2 or more, the reproduced signal is sent as a partial response PR.
When binary levels such as "-1" and "1" are detected by (1,1) equalization, "1" and "-1" are always consecutive for 2 bits or more. Further, if a ternary level such as “1”, “0” and “1” is detected by partial response PR (1,1) equalization of the reproduction signal, “0” is detected.
Is not consecutive for 2 bits or more, and "-1" →
After shifting to “0”, be sure to change to “1”, and also “1” →
After shifting to "0", it always changes to "-1". The present invention executes Viterbi decoding by utilizing such characteristics.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which a recording code recorded as a data bit having an inversion interval of 2 or more is used as a partial response PR (1,
1) A case where binary data is detected by equalization and data is reproduced is shown. Further, FIG. 2 shows an example of signals of the respective parts shown in FIG.

In FIG. 1, the precoder 1 is provided on the recording side.
The input data D11 is NRZI converted by 1 to be recorded as a recording code D12, and on the reproducing side, the reproducing head output signal D13 is processed by the PR (1,1) equalizer 12 by the partial response PR (1,1) equalizing process. After detecting the reproduction signal D14 of binary level, the Viterbi decoder 13
In, the Viterbi decoding in the binary 4 state is performed and the reproduction output data D15 is transmitted.

By the way, as shown in FIG. 2, the binary reproduction signal D14 of the code D12 recorded as data bits having an inversion interval of 2 or more takes binary levels of "-1" and "1". "1" and "-1" are always consecutive for 2 bits or more. The Viterbi decoder 13 executes the Viterbi decoding in the binary 4 state by utilizing such changes.

FIG. 3 is a state transition diagram of the Viterbi decoder 13. The state of reproduction is set to four states of S0, S1, S2 and S3, and state transitions for binary level inputs "-1" and "1". Is shown. In this case, the feature that the binary level inputs “1” and “−1” are always continuous for 2 bits or more is used.

That is, when the first "1" is input in the state S0, the state transitions to the state S1 and outputs "1". When the next "1" is input, the state S1 transitions to the state S2 and "0". Is output, and even if "1" is input, it stays in the state S2 and outputs "0". In the state S2, the first "-
When "1" is input, the state transits to state S3 and outputs "1", and when the next "-1" is input, state S3 to state S0.
Even if "-1" is input, the state stays in the state S0 and "0" is output. Viterbi decoder 1
When an input violating such a rule of state transition is detected, 3 detects the violating state, judges the original state, corrects the bit error, and decodes.

FIG. 4 is a trellis diagram showing the state transition shown in FIG. Here, it is assumed that the binary reproduction level y _k input to the Viterbi decoder at time k is detected with a probability of having a Gaussian distribution of height 1 centered on the recording level, and the previous time k−1 when transition from a state S _a to state S _b at time k in, it determines the most likely path the path length of the path represented by the negative logarithm of the transition probability is minimized.

Assuming that the path length at the time of transition from the state S _a to the state S _b is L _ab , L ₀₀ , L ₀₁ , L ₁₂ , L
₂₂ , L ₂₃ and L ₃₀ are L ₀₀ = (y _k +1) ² and L ₀₁ = (y _k −1) ² , L
₁₂ = (y _k -1) ² L ₂₂ = (y _k -1) ² , L ₂₃ = (y _k +1) ² , L
₃₀ = (y _k +1) ² . By the way, when comparing path lengths, it is sufficient to discuss relative values rather than absolute values. Therefore, by adding and multiplying the above values by a constant value, L ₀₀ = L ₂₃ = L ₃₀ = y _k ... (1) L ₀₁ = L ₁₂ = L ₂₂ = -y _{k It} can be converted into (2). Further, the metrics of the states S3, S2, S1, S0 at time k are M _k (S3), M _k (S2), M _k (S
1) and M _k (S0), state S at time k−1
3, S2, S1, S0 metrics are M _k-1 (S3),
If M _k-1 (S2), M _k-1 (S1), and M _k-1 (S0), then M _k (S3) = M _k-1 (S2) + L ₂₃ (3) M _{k (S2) = min {M} k-1 (S2) + L 22, M k-1 (S1) + L 12} ............ (4) M k (S1) = M k-1 (S0) + L 01 ... (5) M _k (S0) = min {M _k-1 (S0) + L ₀₀ , M _k-1 (S3) + L ₃₀ } (6)

Further, equations (1) and (6) are added to equations (3) to (6).
Substituting (2), M _k (S3) = M _k-1 (S2) + y _k (7) M _k (S2) = min {M _k-1 (S2) -y _k , M _{k-1 (S1) -y k} } ............ (8) M k (S1) = M k-1 (S0) -y k ............ (9) M k (S0) = min {M k ₋₁ (S0) + y _k , M _k−1 (S3) + y _k } (10)

Therefore, equations (7), (8), (9) and (1
From 0), the state transition can be classified into the following four.

1. In the case of M _k-1 (S2) <M _k-1 (S1) and M _k-1 (S0) <M _k-1 (S3). _{M k (S3) = M k} -1 (S2) + y k M k (S2) = M k-1 (S2) -y k M k (S1) = M k-1 (S0) -y k M k ( S0) = M _k−1 (S0) + y _k The state transition in this case is called merge 0, and the trellis diagram is shown in FIG. 5 (a).

2. In the case of M _k-1 (S2) <M _k-1 (S1) and M _k-1 (S0) ≧ M _k-1 (S3). _{M k (S3) = M k} -1 (S2) + y k M k (S2) = M k-1 (S2) -y k M k (S1) = M k-1 (S0) -y k M k ( S0) = M _k-1 (S3) + y _k The state transition in this case is called merge 1, and the trellis diagram is shown in FIG. 5 (b).

3. In the case of M _k-1 (S2) ≧ M _k-1 (S1) and M _k-1 (S0) <M _k-1 (S3). _{M k (S3) = M k} -1 (S2) + y k M k (S2) = M k-1 (S1) -y k M k (S1) = M k-1 (S0) -y k M k ( S0) = M _k−1 (S0) + y _k The state transition in this case is called merge 2, and the trellis diagram is shown in FIG. 5 (c).

4. In the case of M _k-1 (S2) ≧ M _k-1 (S1) and M _k-1 (S0) ≧ M _k-1 (S3). _{M k (S3) = M k} -1 (S2) + y k M k (S2) = M k-1 (S1) -y k M k (S1) = M k-1 (S0) -y k M k ( S0) = M _k-1 (S3) + y _k The state transition in this case is called merge 3, and the trellis diagram is shown in FIG. 5 (d). Thus, the merge can be determined from the input value by calculating the metric.

By the way, as shown in FIG. 6, when three continuous state transitions (merge) change from (merge 0 to merge 1) → merge 1 → (merge 0 to merge 1), When a plurality of paths converge to the state S2 (time t = 0 in FIG. 6) and change from (merge 0 or merge 2) → merge 2 → (merge 0 or merge 2), the plurality of paths are in a state. Since the reproduction output data sequence corresponding to S0 is converged, a bit error correction for a random error can be performed. That is, at time t = 4 in FIG. 6, the state converges to the state S0, and the reproduction output data “0,0,1,0” is obtained.

Viterbi decoder 1 for realizing such processing
As shown in FIG. 1, the reference numeral 3 denotes a metric calculation circuit 131 that receives the binary reproduction signal D14 and calculates the metric shown in Expressions (7) to (10), and a metric M _k-1 (S
2) and M _k-1 (S1), and the metric M _k-1 (S
0) and M _k-1 (S3) are respectively determined to determine which of merge 0 to merge 3 is to be performed, and a merge determination circuit 132 which detects three consecutive predetermined merges. The path determining circuit 133 determines the path that converges to one of the states S0 and S2 and sends the corresponding reproduction output data D15.

FIG. 7 is a block diagram showing a second embodiment of the present invention, in which a recording code recorded as a data bit having an inversion interval of 2 or more is converted into a partial response PR (1,
1) The case where three values are detected by equalization and data is reproduced is shown. Further, FIG. 8 shows an example of signals of the respective parts shown in FIG.

In FIG. 7, the reversal interval is 2 on the recording side.
The input data D21 consisting of the above data bits is recorded as it is as the recording code D22, and the reproducing head output signal D23 is reproduced by the PR (1,1) equalizer 22 on the reproducing side.
After detecting the value reproduction signal D24, the Viterbi decoder 2
In No. 3, Viterbi decoding in the three-value four-state is performed and reproduction output data D25 is transmitted.

FIG. 9 is a state transition diagram of the Viterbi decoder 23. The reproduction states are set to four states of S0, S1, S2 and S3, and input of three levels "-1", "0", "1". The state transition for ". In this case, ternary level inputs "-1", "0", "1" do not have "0" continuing for 2 bits or more, and after the transition from "-1" to "0". It utilizes the feature that it always changes to "1" and that it always changes to "-1" after shifting from "1" to "0".

That is, when "-1" is input in the state S0, it stays in the state S0 and outputs "0", and when "0" is input in the state S0, it transits to the state S1 and outputs "1". Then, when "1" is input in the state S1, the state transits to the state S2 and "1" is output. Further, even if "1" is input in the state S2, it stays in the state S2 and outputs "1".
When "0" is input, the state transits to state S3 and outputs "0", and when "-1" is input next, state S3 changes to state S3.
It shifts to 0 and outputs "0". The Viterbi decoder 23
When there is an input that violates such a rule of state transition, the state of the violation is detected, the original state is judged, bit error correction is performed, and decoding is performed.

FIG. 10 is a trellis diagram showing the state transition shown in FIG. 9, which is similar to the trellis diagram of the first embodiment shown in FIG. Here, if the ternary reproduction value y _k to be input to the Viterbi decoder at time k is set, the path length at the time of transition from the state S _a to the state S _b is L, as in the case of the first embodiment. _ab is L ₀₀ , L ₀₁ , L
₁₂ , L ₂₂ , L ₂₃ , and L ₃₀ are L ₀₀ = (y _k +1) ² , L ₀₁ = (y _k −0) ² , L
^{_{12 = (y k -1) 2}} L 22 = (y k -1) 2, L 23 = (y k -0) 2, L
₃₀ = (y _k +1) ² . By the way, when comparing path lengths, it is sufficient to discuss relative values instead of absolute values. Therefore, by adding and multiplying the above values by a constant value, L ₀₀ = L ₃₀ = + y _k +0. 5 (11) L ₀₁ = L ₂₃ = 0 (12) L ₁₂ = L ₂₂ = −y _k +0.5 (13) Further, the metrics of the states S3, S2, S1, S0 at time k are M _k (S3), M _k (S2), M _k (S
1) and M _k (S0), state S at time k−1
3, S2, S1, S0 metrics are M _k-1 (S3),
If M _k-1 (S2), M _k-1 (S1), and M _k-1 (S0), then M _k (S3) = M _k-1 (S2) + L ₂₃ ... (14) M _k (S2) = min {M _k-1 (S2) + L ₂₂ , M _k-1 (S1) + L ₁₂ } ... (15) M _k (S1) = M _k-1 (S0) + L ₀₁ ... (16) a _{M k (S0) = min {} M k-1 (S0) + L 00, M k-1 (S3) + L 30} ......... (17).

Further, the equation (11) is added to the equations (14) to (17).
Substituting (13) to _Mk (S3) = _Mk-1 (S2) ... (18) _Mk (S2) = min { _Mk-1 (S2) -yk ₊ 0.5, M _k-1 (S1) -y _k +0.5} (19) M _k (S1) = M _k-1 (S0) (20) M _k (S0) = min {M _{k- 1} (S0) + y _k +0.5, M _k-1 (S3) + y _k +0.5} (21)

Therefore, equations (18), (19), (2
From 0) and (21), the state transition can be classified into the following four.

1. In the case of M _k-1 (S2) <M _k-1 (S1) and M _k-1 (S0) <M _k-1 (S3). _{M k (S3) = M k} -1 (S2) M k (S2) = M k-1 (S2) -y k +0.5 M k (S1) = M k-1 (S0) M k (S0) _{= M k-1 (S0)} + y k +0.5 transition state in this case is the same as the trellis diagram of the merge 0 shown in Figure 5 (a).

2. In the case of M _k-1 (S2) <M _k-1 (S1) and M _k-1 (S0) ≧ M _k-1 (S3). _{M k (S3) = M k} -1 (S2) M k (S2) = M k-1 (S2) -y k +0.5 M k (S1) = M k-1 (S0) M k (S0) _{= M k-1 (S3)} + y k +0.5 in this case state transition is the same as the trellis diagram of the merge 1 shown in Figure 5 (b).

3. In the case of M _k-1 (S2) ≧ M _k-1 (S1) and M _k-1 (S0) <M _k-1 (S3). _{M k (S3) = M k} -1 (S2) M k (S2) = M k-1 (S1) -y k +0.5 M k (S1) = M k-1 (S0) M k (S0) = M _k-1 (S0) + y _k +0.5 The state transition in this case is the same as the trellis diagram of the merge 2 shown in FIG. 5 (c).

4. In the case of M _k-1 (S2) ≧ M _k-1 (S1) and M _k-1 (S0) ≧ M _k-1 (S3). _{M k (S3) = M k} -1 (S2) M k (S2) = M k-1 (S1) -y k +0.5 M k (S1) = M k-1 (S0) M k (S0) = M _k-1 (S3) + y _k +0.5 The state transition in this case is the same as the trellis diagram of the merge 3 shown in FIG. 5 (d). Thus, the merge can be determined from the input value by calculating the metric.

By the way, as in the case of the first embodiment,
When three consecutive state transitions (merge) change from (merge 0 to merge 1) → merge 1 → (merge 0 to merge 1), a plurality of paths converge to the state S2, and (merge 0 Or merge 2) → merge 2 → (merge 0 or merge 2), a plurality of paths converge to the state S0 and the corresponding reproduced output data sequence is obtained, so that a bit error correction for a random error is performed. be able to.

Viterbi decoder 2 for realizing such processing
Reference numeral 3 denotes a metric calculation circuit 231 which receives a ternary reproduction signal D24 and calculates a metric, as shown in FIG.
Of the merge 0 to merge 3, the magnitudes of the metrics M _k-1 (S2) and M _k-1 (S1) and the metrics M _k-1 (S0) and M _k-1 (S3) are determined. Of the merge determination circuit 232 for determining any of the following, and when three consecutive predetermined margins are detected, the path that converges to any one of the states S0 and S2 is determined and the corresponding reproduction output data The path determination circuit 233 sends out D15.

[0039]

As described above, according to the present invention, when input data is NRZI converted and recorded as data bits having an inversion interval of 2 or more and data is reproduced, the reproduced signal is a partial response PR (1, 1) When binary levels (“-1” and “1”) are detected by equalization,
Utilizing the feature that "1" and "-1" are always consecutive for 2 bits or more, Viterbi decoding is performed by setting a binary 4-state transition rule that sets the playback state to 4 states. It is possible to improve the error rate against random errors by performing the bit error correction that is utilized in.

Further, according to the present invention, when input data consisting of data bits having an inversion interval of 2 or more is recorded and data is reproduced, a reproduction signal is transmitted as a partial response PR.
When ternary levels (“1”, “0” and “1”) are detected by (1,1) equalization, “0” does not continue for 2 bits or more, and from “−1” Utilizing the feature that it always changes to "1" after shifting to "0", or always changes to "-1" after shifting from "1" to "0", the playback state is set to four states and three-value four By setting the state transition rule and performing Viterbi decoding, it is possible to improve the error rate against random errors by performing bit error correction that makes full use of the characteristics of the recording code.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of signals of respective units shown in FIG.

3 is a state transition diagram in the Viterbi decoder 13 shown in FIG.

FIG. 4 is a trellis diagram of the state transition shown in FIG.

FIG. 5 is a trellis diagram showing merge 0 to merge 3.

FIG. 6 is a diagram showing an example in which a path converges to a state S2.

FIG. 7 is a block diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing an example of signals of respective units shown in FIG.

9 is a state transition diagram in the Viterbi decoder 23 shown in FIG.

10 is a trellis diagram of the state transition shown in FIG.

FIG. 11 is a block diagram showing an example of a conventional reproduction data detecting device.

FIG. 12 is a diagram showing an example of signals of respective units shown in FIG. 11.

13 is a state transition diagram in the Viterbi decoder 33 shown in FIG.

[Explanation of symbols]

 12,22 PR (1,1) equalizer 13,23 Viterbi decoder 131,231 Metric operation circuit 132,232 Merge determination circuit 133,233 Path determination circuit D11, D21 Input data D12, D22 Recording code D13, D23 Reproduction Head output signal D14 binary reproduction signal D15, D25 reproduction output data D24 three-value reproduction signal

Claims (2)

[Claims] 1. A reproduction data detection device for a recording code for converting input data by NRZI conversion and recording as data bits having an inversion interval of 2 or more, and receiving a reproduction head output signal of the recording code and performing a binary response signal by partial response equalization. And means for performing Viterbi decoding according to four transition rules of the reproduction state according to the binary signal,
The transition rule sets the level of the binary signal to “−1”,
The four reproduction states are set to “1” and the four reproduction states are S0, S1, S2, S.
In the case of 3, the state transitions to the state S0 and outputs the reproduction data "0" when "-1" is input in the state S0, and the state S1 transitions to the state S1 when the "1" is input in the state S0. When "1" is output and state "1" is input in state S1, the state transitions to state S2 and reproduction data "0" is output. When state "1" is input in state S2, state transitions to state S2 and reproduction data "0" is output. "0" is output, and when "-1" is input in the state S2, the state shifts to the state S3, the reproduction data "1" is output, and the state S3
When "-1" is input, a transition is made to the state S0 and the reproduction data "0" is output. 2. A reproduction data detection device for a recording code, which directly records input data composed of data bits having an inversion interval of 2 or more, receives a reproduction head output signal of the recording code, and converts it into a ternary signal by partial response equalization. A means for converting and a means for performing Viterbi decoding according to four transition rules of the reproduction state according to the three-valued signal, wherein the transition rule sets the level of the three-valued signal to “−1”,
The reproduction states are set to “0” and “1”, and the four reproduction states are S0, S1,
When S2 and S3 are set, when "-1" is input in the state S0, the state transitions to the state S0 to output the reproduction data "0", and when "0" is input in the state S0, the state transitions to the state S1 and reproduces. When data "1" is output and "1" is input in state S1, transition is made to state S2, and reproduction data "1" is output. When "1" is input in state S2, transition is made to state S2 and reproduction is performed. When the data "1" is output and "0" is input in the state S2, the state shifts to the state S3 and the reproduction data "0" is output and the state S
A reproduction data detecting device characterized in that when "-1" is inputted in 3, the reproduction data "0" is outputted by transiting to the state S0.