JPH0625927B2 - Sequence controller - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller, and more particularly to a sequence control method and apparatus capable of speeding up arithmetic processing of a programmable controller.

[Background of the Invention]

With the development of semiconductor devices, programmable controllers have come to be used in many fields.

For example, as an example of editing a program using a CRT display device, IE ³ Conference Record1971, Oct. 18-
21, pp1043-1051.

Also, to search and display the sequence block, U. S. A.
Pat. No. 3964026, and U.S. S. A. Pat. There is No.4183462.

Conventionally, a programmable controller (hereinafter abbreviated as PCs) that employs a semiconductor digital logic circuit is the 16th.
As shown in the figure, the sequence program memory 2 of the PCs is stored.
The sequence control processor sequentially executes the sequence program 10 stored in 0 until the sequence program end instruction 14 is issued from the sequence program start address 11. That is, the storage unit 2 to be processed
The value of the address of 0, that is, the program counter 13
While updating the value of, the sequence control instruction 15 stored at the corresponding address is processed. Generally, all sequence control instructions are composed of 1 word, so the value of the program counter 13 is incremented by 1 during execution of the sequence program. When a sequence program end instruction 14 for setting the value of the program counter to the start address of the sequence program is output as the content of the corresponding address indicated by the program counter 13, the start address 11 of the sequence program is set as the value of the program counter 13. Set.

As described above, in normal PCs, the sequence program command is sequentially executed from the start address of the sequence program until the end command of the sequence program is issued, and when the program is returned to the start of the sequence program, the cycle is repeated. In addition, the sequence operation is performed in an infinite loop.

In addition, Japanese Patent Laid-Open No. 59-205605 proposes to avoid the above-mentioned infinite loop sequence operation and speed up the sequence processing. According to this, the sequence processing program should include a process processing program group including a plurality of sequence process processing programs divided for each process step, and whether each process processing program in the process processing program group should be executed. It is separated into a process step program that supervises sequence control including a plurality of process process execution determination commands for determining whether or not, and each is stored in a program memory. Further, the process input / output signal and the process process execution determination command that is determined based on the input / output signal are ON when the corresponding process process program should be executed, and the process process executed based on this ON. A step signal that turns off when the execution of the program is completed is linked to each of the plurality of process processing programs and stored in the input / output buffer memory. When the process step program is started at a predetermined cycle, the process process execution determination commands in the program are sequentially read and executed, and the process process program corresponding to the determination result should be executed, the step signal Is turned on to execute the corresponding process processing program, and when the execution of the process processing program is completed, the sequence processing means executes the process of turning off the step signal. This allows
Among the process processing programs, the programs that do not meet the execution conditions are not executed including the reading, so the sequence processing can be speeded up accordingly.

Further, since the above step signal indicates that the corresponding process processing program is being executed, it means that the sequence is congested when the step signal is on for a reason longer than necessary for some reason. . Therefore, when the ON state of the progress signal exceeds a predetermined time, the process related to the process processing program corresponding to the step signal is determined to be abnormal, and the alarm is notified to promptly know the abnormality of the control target. You can

However, in the above-mentioned conventional technique, since consideration is not given according to the target process of sequence control, there is a problem that speedup of processing and accuracy of abnormality detection are lacking.

[Object of the Invention]

An object of the present invention is to provide a sequence control device capable of speeding up sequence processing and accurately detecting an abnormality in a control target.

[Outline of Invention]

The present invention, in the above-mentioned conventional sequence control device, includes a plurality of independent processing stages in which process steps are executed in parallel, and the processing stages each include at least one of the process processing programs. Of a plurality of sub-programs corresponding to the process corresponding to the sub-process, and whether to execute any sub-program in the plurality of sub-programs is determined based on the input / output signal, An execution determination instruction for controlling the activation of the subprogram based on the determination result is included, and the abnormality is further determined for each processing stage.

That is, in the present invention, the process to be controlled is, for example, 1
This is suitable when a plurality of types of processing objects are processed on one processing stage. That is, even if a process processing program is necessary for a certain processing target object, an unnecessary process processing program may be present for another processing target object. In such a case, the process program is divided into a plurality of subprograms according to the type of the object to be processed in one processing stage, and each subprogram of the subprogram is changed according to the process input signal that changes according to the type of the object. It is decided whether or not it can be executed. Therefore, according to the present invention, the sequence processing can be further speeded up as compared with the case where all the processing including unnecessary processing is executed.

Further, in the case of a process in which a plurality of machining stages each consisting of a plurality of process processing programs are executed independently and in parallel, rather than determining whether the control target related to the process processing program in one stage is abnormal or not. Also, it is more convenient to judge by stage. Therefore, according to the present invention, the abnormality is judged on a stage-by-stage basis, so that the abnormality is accurately judged in correspondence with the process.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows an embodiment of the sequence control method of the present invention.
In this example, the step progress main program 10 is cyclically executed by activating a timer or the like, and each step of the main program 10 is executed by inputting desired information from the controlled system and executing a corresponding subdivided process processing program. If it is determined to be executed, an interrupt signal is generated and the process processing program is executed. For example, when an interrupt signal is generated by the nth step process execution determination command 70 of the main program 10, the nth sequence step process program 78 is activated. When the nth sequence process processing program 78 ends, the main program 1
Returning to 0, the n + 1th step process execution determination command 79 is executed. Similarly, the nth sequence process processing program 7
8 is provided with a step 78-n for determining whether to execute one 170 out of the plurality of subprograms having the further subdivided process processing.
The corresponding subprogram 78-n may be executed when it is determined that the subprogram 78-n should be executed in 8-n.

Now, let's look at how to create a plurality of process processing programs according to the present invention.

According to the method of the present invention, at the time of system initialization, a sequence process processing program end command 141 ... With a slight margin from the number of processing units of the sequence program.
14N is set. This is shown in FIG. That is, this state indicates that no process processing program is registered. Further, the top addresses of the respective sequence process processing programs are set in the program top address register 90 with the head address values 91 to 91N for the respective process programs.

Now, when the program maker tries to create the I-th sequence process processing program, by knowing the start address 9i of the process processing program of the specified process number from the program top address table 90, the process processing is performed. From the program memory 10 ', the address of the final instruction of the sequence process program of the specified process number is known, and a space is created therein for the capacity of the newly assembled process process program.
Register and store the new process program. At this time, all the instructions are moved backward by the number of words of the new program after the I-th program, and along with that, the contents of the start address of the program top address table 90 after the I-th program also correspond to the number of words of the new program. Each is automatically added. Such addition is a simple process, and only the start address of the address table 90 needs to be mechanically changed according to the change of the address due to the registration of the process program. Further, the registration of the process processing program is a very simple process. That is, the program creator may first specify the process number of the sequence process processing program to be registered and then input each process processing program (FIG. 3). According to the present invention, the change associated with the increase or decrease of the command word at the time of modification may be performed for the value of the head address table 90 of the program larger than the modified program number. If the subprogram 170 shown by the broken line in FIG. 1 is included, the correspondence between a plurality of subprograms and their addresses is shown in this address table 90.
I will remember it together.

Now, let's take a look at the creation of the process step main program 10 which controls the overall process step sequence. The main program 10 is also basically created by the relay circuit diagram image displayed on the CRT screen. The main program to be registered consists of a plurality of steps as shown by 10 in FIG. 1. In the embodiment of the present invention, as shown in FIG. 3, it is stored at the beginning of the process program 10 'in the sequence program memory 100. ing. If there is a subprogram 170 such as shown in FIG.
It is stored in 0 '.

The processing contents and operation of each item have been individually described above. FIG. 4 shows the overall configuration of sequence control, which is an example of the embodiment configuration of the present invention made by applying the functions of these items.

In the present invention, as the programs in the sequence program storage unit 100, a subdivided program group 10 '(that is, a sequence step processing program group) divided into processing units and these sequence step processing program groups 10'.
Among them, only the necessary sequence process processing program is started and the program is separately stored in the process step progress main program 10 which generally controls the entire program. Here, the process step main program 10 causes the cycle timer signal 216 generated by the cycle start timer 213.
Thus, all the main program instructions 10 are sweeped like a conventional PCs at regular intervals, and it is determined which sequence process processing program is activated at each step. This cycle start timer value is set in the cycle start timer 213 in advance by the sequence arithmetic processing unit (SP) 130. The SP 130 has a simple structure and is constructed of digital logic circuits. When a certain sequence step process execution decision command decision result in the step step main program 10 is true, the value of the program counter is stored in the waiting program storage register 215 and then the sequence operation processing device 130 divides it. The embedded signal 230 is a semiconductor integrated circuit (LSI)
Sequence management processor (CPU) 20
Issued for 0. As a result, the CPU 200 activates the program OS 214, knows to which sequence process processing program the activation request is made based on the identification information signal issued together with the interrupt signal, and activates it from the sequence process processing program top address table 90. Knowing the start address where the sequence process processing program to be stored is stored, the contents are set in the program counter 13 of the sequence processor, and the sequence arithmetic processing unit 130 is activated to process this process processing program. Then, when the processing of the started sequence process processing program proceeds and the sequence end command is executed, the sequence operation processing device 130 causes the CPU 2 to
The interrupt signal 218 is input to 00, and the address next to the address at the time of the interruption of the process step main program 10, which was interrupted earlier, enters the program counter 13 and restarts the processing.

In the relay circuit diagram as shown in FIG. 6, the determination condition 120 for activating the sequence process program of the first process is determined by the external input / output contact, the timer, the counter, and other internal processing function contacts. Described and the result is the sequence step processing command output coil 121 of the first step.
Express as. Actually, the hardware configuration of the main part of the PCs is as shown in FIG. Here, in the process input / output controller 131, the sequence command input / output buffer memory 140 shown in FIG. 6 has one address and one bit, and internal auxiliary functions such as external input / output, auxiliary relay, and latch relay (each of the sequence process step-by-step commands). The on / off state of all contacts and outputs (including bits) are reflected in this memory 140. That is, the on / off state of the input signal from the outside is calculated at the corresponding address 141 of the external input section of the buffer memory 140, and by the sequence command processing unit 130 of FIG. 5 according to the sequence command stored in the sequence program storage section 100. As for the external output ON / OFF command, if either ON or OFF is written in the corresponding address 142 of the external output section of the buffer memory 140, the process input / output device 131 of FIG. It is output as an off signal. Here, the on / off state, that is, the execution state of each sequence process instruction is also displayed in the corresponding address portion 144 of the sequence process instruction of the input / output buffer memory 140 according to the result of the sequence operation.

Here, for simplification of explanation, each sequence process instruction uses a latch type set / reset type element image type in terms of a relay circuit (this is not limited to the latch type and is realized. This is not to say that normal auxiliary relay contacts or coils can fulfill the same function as long as they are self-holding, so that function is not limited). Therefore, once the first sequence process processing set coil is excited, until the first sequence process processing reset coil input is applied,
Since the first step processing coil, that is, the sequence step processing (1) 1441 is in the ON state, the main program is skipped, and an interrupt is sent to the CPU 200 every time the first sequence step processing instruction is checked to be ON. The OS 214 sets the first sequence process processing program top address 91 from the program top address table 90 as the program counter value, and the sequence process of the first process processing is performed. When the sequence process of the first step is completed, the CPU 200 is interrupted again by the sequence end command, the process returns to the process step main program again by the priority determination of the OS 214, and the first sequence process command coil The process is restarted from the next command word.

Further, in this method, the number of steps to be processed in one step advance program (FIG. 3, FIG. 10) and one scan is not particularly limited, and one or a plurality of step processes can be simultaneously executed if necessary. You can

If the process of the process that has been processed up to now is unnecessary and the process of the next process is to be started, the sequence process process reset command coil of the process to be stopped in the process step main program 10 is excited. In this case, the scanning of the corresponding process is automatically stopped and the sequence command set command coil to be started next is excited.

The processing in the present invention will be described. In the case of sequence interlock control, when a failure or abnormality occurs in the control target equipment, the process step condition for transitioning from one process to the next is currently in process, and in most cases, the sequence Control stops. Therefore, if each process is normally normal, it will naturally
The process congestion check timer is set to a slightly longer time. Therefore, when a failure occurs, the process congestion check timer operates to determine in which process the abnormality has occurred. In order to know the failure process, there is also a method of making a determination by using the process congestion check timer in this way, but in the case of the present invention, when a time-out error occurs, a sequence process processing command that is a work area of the sequence operation is executed. The contact state of is ON, that is, the process number that is still in process processing is searched.
Then, while displaying the process name, from the process step main program, the step step condition of the sequence relay ladder diagram having the step step output name of the corresponding step number,
It is displayed on the CRT display, and the on / off state of each contact that constitutes the relay ladder in that case, and how much the voltage applied to the + common line is in the live line state in the relay ladder diagram , If the process is automatically displayed on the CRT screen, which process step condition does not hold, so the process processing is congested, and which part of the control circuit that caused the error is abnormal. ,
Can be determined.

Therefore, the abnormal process search unit 222 shown in FIG. 7 searches the sequence program 100 stored in the PCs for a program having as an output a process reset coil that operates as a connection of the process coil that has been turned ON. To do. Since the process is congested because the signal of the circuit having this output is not output, the cause of the failure can be determined by knowing why the reset output circuit does not output.

When the sequence program stored in the program storage unit 100 is being executed by the sequence arithmetic processing unit 130, the sequence command input / output buffer memory 131 is transferred to the sequence command input / output buffer memory 131 via the process input / output unit 226 according to the on / off state of the field device 227. Then, the signal of "0" is written.

Therefore, the abnormal process search unit 222 sets the sequence logic circuit block relating to the sequence process processing reset output command which causes the process congestion and cannot move to the next step from the process step main program stored in the program. The circuit is searched, the command word group is sent to the relay circuit diagram conversion unit 223, converted into the relay circuit diagram, and all contacts and output on / off signals 229 appearing in the circuit are taken in, and each contact, output Edit the on / off state and which part of the circuit is in the hot line state, and transfer it to the CRT display section. The wiring section and the circuit elements are displayed on the CRT screen 225 by the thick line and the thin line to turn the signal on and off and the live line section. Automatically displayed as a diagram image.

Since this is the transition condition itself to the next process related to the part where the failure has occurred, it is immediately recognizable as to which process condition is congested because which transition condition is not relevant.

Next, an apparent example of failure diagnosis will be described. FIG. 7 shows only the main part of the sequence control device. P in FIG.
The manufacturing line used as the control object of Cs is shown. On this manufacturing line, processing stages (301, 302, ...) Performing intensive processing are lined up at a fixed distance. In the first processing stage 301, the mounting processing of the component A group and the component B group is performed, and in the second processing stage, the mounting processing of the component C group is performed. Incidentally, in this manufacturing line, the conveying equipment 350 is connected by reciprocating motion by the distance between the respective processing stages (301, 302 ...) And sending the processing object (311, 312 ...) To the next processing stage with a constant pitch. When the processing of all the processing stages (301, 302 ...) Is completed, the processing target object (3
11, 312 ...) are moved to the next processing stage by the transfer facility 350. Then, each processing object is as shown in FIG. 9, and new processing is performed at each processing stage. By the way, a plurality of types of processing objects flow in this manufacturing line, and each processing stage has different parts to be mounted or a different processing method depending on the respective processing objects sent to it. This state is the 8th
This will be described with reference to FIGS.

In FIG. 8, the first processing stage 301 is the processing object 311.
Accordingly, the parts supply facility 340 automatically receives the corresponding parts. Parts A group storage 321-A and parts B group storage 321-B for the first processing stage 301
Than parts are supplied. By the way, the parts A1 (321-A1) and the parts A2 are stored in the parts A group storage 321-A.
(321-A2), component A3 (321-A3), and a plurality of types of components are stored. These three parts A
From the group, the PCs determine which component should be supplied to the processing object 311, and the component supply switching device 330 switches the component selection. When the switching operation is completed so that the component supply switching device 330 picks up the corresponding component, the component delivery device 331 operates and the required component is supplied to the first processing stage 301.

The 10th type of operation is a time chat method.
It is a figure. In this manufacturing line, an object to be machined is intermittently sent, and the object to be machined sent to each of the machining stages is brought into a stopped state to perform concentrated machining. The cycle from the conveyance of the object to be processed to the end of processing is cyclically operated. First, the transport operation 400 is performed in which the transport facility sends the workpiece to the next processing stage. Transport operation 40
When 0 ends, the processing for each processing stage starts all at once.
When these processes are examined for each stage, they are operated in a sequential manner in the order of shogi, the first process, the second process, and the third process. However, since there is no interlocking between the machining stages, the machining progresses independently and in parallel. Ie the first
It does not matter which of the operation end timing of the first step 401 of the processing stage processing and the end dimming of the first step 411 of the second processing stage processing ends earlier. That is, since the processing of the first processing stage and the processing of the second processing stage are completely independent from each other, there is no causal relationship with each other, and there is no problem.

However, in each processing stage, each processing step has an interlock for advancing a step, and the steps are carried out in a systematic and sequential manner. What is important here is that the machining progress for each machining stage proceeds in an orderly manner according to the program. Therefore, if the teaching of the progress of the process, that is, the input / output state transition of PCs, is performed in advance, the equipment will not fail. When it occurs, it is possible to automatically detect and diagnose at which process step the abnormality has occurred. However, in reality, various processes are progressing in parallel at each stage, so by simply operating the transition state of input / output of PCs on the actual process line and automatically analyzing and storing this, If the transition state is taught as a standard pattern for normal operation and the equipment is put into actual operation, if the pattern matching with the standard pattern for normal operation that was taught is tried to proceed with machining, even if there is a failure, Although it is not an abnormality, it is often misdiagnosed as an equipment abnormality and cannot be practically used. Similarly, when some kind of abnormality occurs, failure diagnosis cannot be performed by comparing and collating with a standard pattern prepared in advance for normal operation. This is because the processing between each processing stage is completely independent and has no causal relationship as described above, so from a microscopic point of view, minute movements of each part caused by mechanical lubricity The input / output transition conditions of the PCs are constantly fluctuating and are not settled due to variations in time or changes in each machining time due to secular changes in mechanical equipment during macro. Furthermore, although it has not been explained so far, when a plurality of types of processing objects flow in the actual manufacturing line, the processing method differs depending on the processing objects, and therefore PCs depends on which processing method is used. Since the input / output state transition of No. 1 changes each time, it is not possible to carry out the failure diagnosis by preparing the standard input / output pattern in advance.
That is, in such an example, it can be said that there is no means for automatically classifying and teaching what is the standard operation pattern and which is abnormal.

Next, the equipment abnormality diagnosis according to the present invention will be described. FIG. 11 shows an example of a sequence ladder program utilizing the present invention. When the processing of all the processing stages described in FIGS. 8, 9 and 10 is completed, the conveyor machine object simultaneous movement coil 510 is excited and each processing object is moved to the next processing stage. And the preparation conditions 52 for each processing stage
When the condition of 0 is satisfied, the process coils (512, 513, 514) and the process congestion check timer 515 for starting the processing of the first, second, and third processing stages are excited all at once. These machining process coils (latches are used here. Therefore, once the process coil is excited, the corresponding process reset coil is excited, and the process coil contact remains in the ON state until the process coil contact turns OFF. The process coil operation instruction 512 is executed every sequential cycle. When the operation command of the process coil 512 is executed, the hardware checks whether the contact of the process coil is ON or OFF, and if the contact of the process coil is ON, the corresponding subroutine 612 is jumped,
When the subroutine 612 that executes the program is completed, the next instruction process coil 513 of the main control program 500 is executed. Since this is also the contact ON, when the subroutine 613 is jumped to complete the process, the process coil 51, which is the next command of the main control program 500, is issued.
Execute 4.

From a macro point of view, when looking at the operation of this program, when the workpieces are simultaneously moved by the carrier machine, the process coils of the first, second and third machining stages are excited and Processing of the processing stage is executed. Here, in the case of a normal operation pattern, the processing time of the first processing stage is 23 seconds, the processing time of the second processing stage is 32 seconds, and the processing time of the third processing stage is 27 seconds.

Process coil 51 for the first, second, and third processing stages
2, 513 and 514 are excited and executed for each program sequence program scan of subroutines 612, 613 and 614 which are processing programs of the corresponding stage. At the same time, the process congestion check timer 515 is set and starts to operate.

This timer is set to 40 seconds, which is slightly longer than the normal processing cycle time of 32 seconds. When the processing time advances and 23 seconds elapse, the condition 602 for completing the processing of the first processing stage is set, After the process reset coil 512 of the first machining stage is excited, the machining program 612 of the first machining stage is not activated. When the machining elapsed time further reaches 27 seconds, the process reset coil 514 of the third machining stage is excited when the machining completion condition 604 of the third machining stage is completed, and the subroutine 61
Execution of 4 stops. Further, after 32 seconds, the processing on the second processing stage ends.

Here, consider the case where the limit switch of the third processing stage fails as shown in FIG. When the workpieces are moved to the next processing stage all at once by the carrier,
Processing of the third processing stage begins. After 23 seconds have passed from the start of processing, the processing of the first processing stage ends and the processing of the other stages ends. However, unlike the normal state, the process reset coil 514 of the third processing stage is not excited even after 27 seconds have elapsed. This is because the limit switch fails in the third processing stage, and the condition 604 for advancing the process is not satisfied. When 32 seconds have passed, the processing of the second processing stage ends. However, since the processing of the third processing stage is not completed, the transfer equipment cannot operate at the same time, and the time elapses. When 40 seconds have passed, the process congestion check timer 515 times up and makes the operator know that it is in an abnormal state. Therefore, the operator instructs the equipment failure diagnosis device to check which part of the production equipment is abnormal. The fault diagnosing device has a fault part searching device 220 shown in FIG. 7 which is turned on in the process coil contact area of the sequence command input / output buffer memory 140 in the process input / output controller 131 shown in FIG. Search. And the abnormal process number 2
28 is notified to the abnormal process search unit 222. Here, the fact that the process coil contact is still ON means that the process has been started but the process reset coil signal for ending the process has not been output for some reason. That is, it can be determined that there is a cause of failure here. By the way, the cause of the failure is not in the sequence circuit that activates the process, but in the process reset circuit that has the role of terminating this process and shifting to the next process, there is a key meaning, that is, the automatic diagnosis of the failure. Therefore, by investigating why the process cannot be completed, the cause can be identified.

〔The invention's effect〕

As described above, according to the present invention, the sequence program processing time is extremely fast. In the past, while it was known to be wasteful, the processing program part outside the relevant process was also processed as a whole.
In the present invention, only a very limited portion needs to be scanned, so that the processing speed can be increased. Generally, it is said that there are 60 to 120 processes in one plant, and if it is assumed that the processes that are moving at the same time are, for example, 3 processes at all times (in the scan step main program 10, (The required time is ignored.) Processing time of 1/20 to 1/40 will be sufficient. 1/10 even considering OS overbed and process time main program processing time
To 1/20 the processing time. This shortens the sequence cycle, and the processing such as positioning is conventionally performed on a PC.
Since it is not possible to process with s, PCs that have been realized with dedicated hardware equipped with a microprocessor or a dedicated counter etc. as an option function, PCs
It is a translation that can be processed by the main body.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining a second example of the sequence control method of the present invention, and FIG. 2 is a subdivided process from the start address table at the time of initialization in the sequence control method of the present invention shown in FIG. FIG. 3 is a diagram for explaining the state of the processing program memory area, FIG. 3 is a diagram for explaining a state in which a process processing program and a main program subdivided by the sequence control method shown in FIG. 1 are created and registered, and FIG. FIG. 5 is a schematic diagram showing a concrete configuration example of a sequence control device for carrying out the sequence control method shown in FIG. 1, according to the present invention, FIG. 5 is a block diagram showing a schematic configuration of a sequence control processor, and FIG. FIG. 7 is a diagram showing register contents of the process input / output controller, and FIG. 7 is another component of the sequence control device for implementing the sequence control method according to the present invention. Schematic, Figure 8 showing the example configuration,
FIG. 9 is a diagram showing a production line controlled by PCs,
FIG. 10 is the operation time chart of FIG. 8 and FIG.
1, 12, and 13 are sequence ladder programs, and FIG. 14 is a diagram showing a process input / output controller.
FIG. 15 is a diagram showing the abnormal state of FIG. 11, and FIG. 16 is a diagram for explaining a conventional general sequence control method.

Claims (1)

[Claims] 1. A process processing program group including a plurality of sequence process processing programs divided for each process step, and set and corresponded to each process processing program in the process processing program group. A program memory for storing a process step program that controls a sequence control including a plurality of process process execution determination commands for determining whether to execute the process process program, a program input / output signal, and the input / output signal It is turned on when the process processing program corresponding to the determination result of the process processing execution determination command to be executed should be executed, and is turned off when the execution of the process processing program executed based on the ON is completed. An input / output buffer memory that stores a step-up signal by linking each of the plurality of process processing programs, When the step program is started in a predetermined cycle, the process processing execution determination commands in the program are sequentially read and executed, and the process processing program corresponding to the determination result should be executed, the input / output buffer memory Sequence processing means for turning on the corresponding step signal for executing the corresponding step processing program, and executing processing for turning off the step signal when the execution of the step processing program is completed; A sequence control device provided with a sequence monitoring means for determining that the process according to the process processing program corresponding to the step signal is abnormal when at least one ON state of the signals exceeds a predetermined time. In, the method includes a plurality of independent processing stages in which the steps of the process are performed in parallel, each processing stage comprising at least one And a plurality of subprograms corresponding to the steps obtained by further subdividing the corresponding steps, and the subprograms of the plurality of subprograms. Whether or not it is determined based on the input / output signal, and an execution determination command that controls activation of the subprogram based on the determination result, wherein the sequence monitoring unit determines abnormality in each processing stage. Sequence control device characterized by.