JPH06250922A - Storage device - Google Patents

Abstract

PURPOSE:To provide a storage device which can store information much more than the number of memory cells. CONSTITUTION:In ROM 11, data is code-compressed and written. For reading data from PROM 10, an address is given to a logic circuit for code development 12 through an address signal line 15. The logic circuit for code development 12 judges whether a section including the address is developed on a buffer memory 13 or not. When it is developed, an output instruction is transmitted and data of one byte in the designated address is outputted to a data signal line 16 through a selection circuit 14. When the section including the designated address is not developed on the buffer memory 13, the logic circuit for code development 12 develops the section including the designated address on the buffer memory 13 from ROM 11, and the output instruction is similarly transmitted so as to output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device such as a ROM or a RAM used in electronic equipment such as a computer.

[0002]

2. Description of the Related Art Generally, a storage device such as a ROM or a RAM (hereinafter also referred to as a "memory") is formed by a repeating structure of a basic circuit called a memory cell. Normally, one bit of information is stored for each memory cell. Therefore, the capacity of the storage device is determined by the number of memory cells. In recent years, along with the multi-functionalization of devices, the tendency of increasing the amount of information and increasing the number of bits of data itself is remarkable, and a memory having a larger storage capacity is required.

[0003]

However, in order to increase the storage capacity, specifically, to increase the number of memory cells, the chip area must be increased as the number of memory cells increases as a semiconductor, or the memory cell circuit and There is no means other than miniaturization of the peripheral circuit, and any of these methods causes a problem of significant cost increase.

It is an object of the present invention to solve such a problem and to provide a memory device capable of storing a larger amount of information than the number of memory cells.

[0005]

To achieve the above object, a storage device of the present invention comprises a main storage device, a buffer storage device having a capacity of at least one partition of uncompressed data, and a buffer storage device in the buffer storage device. And a code expansion logic circuit for expanding the data in the main storage device into the buffer storage device.

[0006]

[Operation] In this way, information is compressed and written,
Since the data can be developed and read, only a small number of memory cells are needed compared to the original amount of information. Therefore, it is possible to store more information than the number of memory cells.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.
explain. Figure 1 shows 1M bits (8 bits x 128K)
2 shows a data map before and after compression when writing 2 Mbit data to the ROM of FIG. The same figure (a) is 2M before compression.
It is a data map of bits. This 2M-bit data is divided into 256 sections of 1K bytes each, and each is code-compressed by a method such as the Huffman method or the Lempel-Ziff method. The compressed data (b) is composed of a dictionary, an index, and compressed data of each section, and is data of 1 M bits or less. The dictionary is a code conversion table. The index indicates from which address each section after compression starts, and is necessary because the size of one section after compression varies. If this compressed data is written in the 1 Mbit ROM, it means that 2 Mbit information is actually written.

A method for reading the data compressed as shown in FIG. 1 will be described below. FIG. 2 shows the present invention as PR.
It is a block diagram at the time of adapting to OM (Programable-ROM). The PROM 10 is composed of a ROM 11 which is a main memory, a code expansion logic circuit 12, a buffer memory 13, a selection circuit 14, an address signal line 15 and a data signal line 16. ROM10 is 1M bit of 8 bits x 128K,
2M-bit data is compressed and written as shown in FIG. Further, the buffer memory 13 has RAMs 17, 18, 19 and 20 of 8 kilobits, and one RAM can store data of one section before compression. Address signal line
15 is 17 bits so that 1 M bits can be addressed, and the data signal line 16 is 8 bits.

When reading data from the PROM 10, first, an address is given to the code expanding logic circuit 12 via the address signal line 15. Code expansion logic circuit 12
Determines whether the partition including the address is expanded in any of the four RAMs of the buffer memory 13. For example, if it is expanded in the RAM 17, the output command is sent to the RAM 17 and the selection command is sent to the selection circuit 14. As a result, one byte in the RAM 17 is output to the data signal line 16 through the selection circuit 14 and the reading is completed. On the other hand, if the partition containing the specified address is not expanded in the buffer memory 13, the code expansion logic circuit 12 expands the partition containing the specified address from the ROM 11 in any of the four RAMs of the buffer memory 13. The output command and the selection command are sent to the RAM as described above, and the data is output.

Although the buffer memory shown in FIG. 2 is composed of four RAMs, the buffer memory may have a storage capacity larger than that of one partition before compression. When the present invention is applied to the ROM section of a one-chip microcomputer instead of the PROM as shown in FIG. 2, the code expansion program is executed by the CPU of the microcomputer instead of executing the code expansion by a dedicated logic circuit. Then, the chip size does not increase by the code expansion logic circuit. In this case, CPU is ROM
When the data corresponding to the address is not read from the buffer memory when reading from the memory, an interrupt is generated from the memory control unit. This interrupt causes the CPU
Restarts the execution of the original program after interrupting the processing, executing the code expansion program, retrying the read instruction that generated the interrupt after the expansion is completed.

Since FIG. 2 is a block diagram having only the code expansion logic circuit because the reading from the ROM has been described, it goes without saying that the code compression logic circuit is necessary when the main memory is a RAM. In that case,
When writing to the RAM, the data in the buffer memory may be compressed by the logic circuit for code compression and then written.

[0012]

As described above, according to the present invention,
Since the data can be compressed and stored, it is possible to store a number of bits larger than the number of memory cells. Therefore, the chip size can be made extremely smaller than that of a storage device having the same capacity, and a significant cost reduction can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a data map before and after compression.

FIG. 2 is a block diagram when the present invention is applied to a PROM.

[Explanation of symbols]

 10 PROM 11 ROM 12 Code expansion logic circuit 13 Buffer memory 14 Selection circuit 15 Address signal line 16 Data signal line 17, 18, 19, 20 RAM

Claims (1)

[Claims] 1. A main storage device, a buffer storage device having a capacity of at least one division of uncompressed data, a code compression logic circuit for compressing data in the buffer storage device into the main storage device, A storage device comprising a code expansion logic circuit for expanding data in a main storage device into the buffer storage device.