JPH06231034A - Method and device for generating address - Google Patents

Abstract

PURPOSE:To provide method and device for generating an address capable of performing memory access with arbitrary sequence and preventing the reduction of software quantity and the lowering of processing efficiency from occurring with simple constitution. CONSTITUTION:A counter 4 generates a numeric value in accordance with a sequence ID set by the MPU 5 of a computer, and furthermore, increments the numeric value at every clock cycle. Table memory 12 is constituted of (m) fields in accordance with the ports of the computer, and is comprised so as to store (n) words, respectively. An adder circuit 13 generates the address of data by adding (m) start addresses stored in a start address register 15 on the addresses inputted from the fields of corresponding table memory 12. A flag check circuit 14 reads out an address sequence control flag at every count of the counter 4, and outputs the value of the counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generating method and apparatus for accessing a memory or the like in a computer system.

[0002]

2. Description of the Related Art In a computer system used for numerical calculation, image processing, etc., when a processor (MPU) used performs matrix calculation or image processing calculation, it is actually one-dimensional. It becomes necessary to perform a two-dimensional access to the memory arranged and associated with the address. That is, as shown in FIG. 5A, it becomes necessary to access a set of data stored in a portion of the data that is grasped as a rectangular area 8 in the calculation process.

When accessing an area on such a memory, if the processing performed on the data stored in the memory at the accessed address is the same for each data, one instruction is executed to store the data in these plural memories. It becomes possible to perform processing on the obtained data. Such processing is called normal vector processing.

However, in general, the memory array of a computer system is not a two-dimensional array suitable for matrix operation or image processing operation, and as shown in FIG.
It is a dimensional array. When accessing a range such as the rectangular area 8 of the memory arranged one-dimensionally, some kind of address conversion is required. However, for example, if this address conversion processing is performed by software, the efficiency of vector processing will be greatly reduced.

Therefore, in order to efficiently perform vector processing on the data stored in the rectangular area 8, hardware that efficiently generates an address for the rectangular area 8 of this memory is used. Such hardware is called a two-dimensional address control circuit. FIG. 6 is a diagram showing the configuration of the two-dimensional address generation circuit 2. The two-dimensional address generation circuit 2 generates an address for performing a raster scan for an area that is regarded as a rectangular area 8 on the memory as shown in FIG. Here, FIG. 5 is a diagram illustrating an area that can be regarded as a rectangular area during image processing or the like.

In FIG. 6, the row counter 31 counts every clock cycle from the start of the address sequence. However, the row counter 31 is set to 2 during counting.
It is cleared when the address generation for all the one column components of the dimensional address generation circuit 2 is completed.

The NX register 32 stores the range of the rectangular area 8 in the x direction. Unless otherwise specified, the setting of each register of the two-dimensional address generation circuit 2 is performed by the computer MP.
Performed by U. The comparator 33 compares the count value of the row counter 31 with the numerical value stored in the NX register 32, and generates a row END signal when the numerical value of the row counter 31 is not smaller than the value stored in the NX register 32.

The column counter 34 counts the generation of the row END signal from the start of the address sequence. The NY register 35 stores the range of the rectangular area 8 in the y-axis direction.
The comparator 36 generates the END signal when the count value of the column counter 34 is not smaller than the numerical value stored in the comparator 36. The SAG 3 is composed of the above parts.

The DY register 41 stores the address step in the y-axis direction in the rectangular area 8. For example, DY
When the numerical value 1 is written in the 41-star 42, the two-dimensional address generation circuit 2 sequentially generates an address for every other column component of the rectangular area 8. The DX register 42 stores the address step in the x-axis direction in the rectangular area 8. For example, when the numerical value 2 is written in the DX register 42, the two-dimensional address generation circuit 2 sequentially generates an address with 2 bytes.

The SA register 43 stores the start address of the rectangular area 8 for each port. The adder 44 is DY
The numerical values stored in the register 41 and the DX register 42 and the numerical values stored in the address registers 45 and 46 are added. The numerical values stored in the adder 44 and the SA register 43 are added according to the setting to form an address for the rectangular area 8. The address registers 45 and 46 hold the output of the two-dimensional address generation circuit 2. The address calculator 4 is composed of the above parts.

Using the two-dimensional address generation circuit 2, FIG.
When accessing the address of the rectangular area 8 on the memory as shown in (A), the five parameters shown in FIG. 5 (A) are set in the two-dimensional address generation circuit 2 prior to the access.

That is, the start address of the rectangular area 8 is S
The register SA register 43 of AG3 is set, the range of the rectangular area 8 in the x-axis direction is set in the NX register 32, the range of the rectangular area 8 in the y-axis direction is set in the NY register 35,
The address step in the x-axis direction of access is set in the DX register 42, and the address step in the y-axis direction of access is set in the DY register 41.

After the above setting, the MPU activates the two-dimensional address generating circuit 2 by software, so that the two-dimensional address generating circuit 2 can be displayed in the rectangular area 8 on the memory of the computer every one clock cycle. Addresses are generated in the order shown by the arrow 5 (A). The two-dimensional address generation circuit 2 generates a signal END at the time when the access to the rectangular area 8 is completed, and the end of the access to the rectangular area 8 is generated by M.
Notify PU.

The two-dimensional address generation circuit 2 is usually provided for each port of the memory, and is used when the computer system has a data memory having a multiport structure or when it has an interface circuit with an external memory having a multiport structure. Requires the number of two-dimensional address generation circuits 2 corresponding to all of these ports.

[0015]

With the above-mentioned configuration of the two-dimensional address generation circuit, only memory access (raster scan) in the direction shown by the arrow in FIG. 5A can be realized. Therefore, for example, in the element processing for the image block of the image compression encoding method such as MPEG, the memory access (zigzag) in the direction shown by the arrow in FIG. 4 which is necessary when performing the run length encoding (run coding) is performed. There is a problem that it cannot be used for a series of access to discontinuous addresses to the data memory area, which is necessary when performing a scan) or a DCT operation.

When it is necessary to perform the above zigzag scan or access to discontinuous addresses,
Vector processing must be realized by repeating a plurality of instructions only for this address generation. Therefore, there is a problem that the program size increases.

Further, when the two-dimensional address generation circuit cannot execute one clock cycle of the instruction, it is necessary to realize the vector processing by repeating a plurality of instructions, so that the efficiency of the vector processing is lowered and the performance is lowered. There was a problem of inviting. Further, when the number of ports of the computer is large, a corresponding number of two-dimensional address generation circuits are required, which increases the number of instructions and the program size, and further increases the amount of hardware.

The present invention has been made in view of the above-mentioned problems of the prior art, and memory access in an arbitrary order is possible. Therefore, even when performing discontinuous memory access other than the raster scan. It is possible to prevent an increase in the size of software for arithmetic processing, and not reduce the efficiency of arithmetic processing, and to suppress an increase in the amount of hardware even when applied to a computer with a large number of ports. It is an object of the present invention to provide a possible address generation method and device thereof.

[0019]

In order to achieve the above object, an address generating method and apparatus of the present invention generate addresses for accessing the data in a different order from the order of data stored in a storage device. Which stores a counter for counting every clock cycle from the start of data reference, and a group of reference order data in which a data storage order and an access order are associated with each other, and the count value of the counter is accessed. When input as data, reference order data generating means for generating the reference order data corresponding thereto, and a storage address of data stored in the storage device by adding a start address of data to be referred to the reference order data And adding means for generating.

Further, the reference data generation means has a plurality of output terminals, and the reference order data is stored so that a plurality of reference order data related to one access are simultaneously output. A plurality of reference data corresponding to the count value are simultaneously generated corresponding to the ports, a plurality of adding means are provided for each output terminal, and the plurality of reference order data output at the same time are respectively stored in the storage device. The start address of the data to be stored is added to generate the storage address of the data.

The reference data generation means further stores an end identifier indicating whether each element data of the reference order data is the final data, and indicates that the end identifier is the final data. It is characterized by further comprising end identification means for identifying the end of the reference order data when the element data of the reference order data is read.

Further, the data is image data arranged two-dimensionally.

The reference order data is data for performing zigzag scanning on the data stored in the storage device.

Further, the storage device and a device for generating an address for accessing the data in a different order from the order of the data stored in the storage device, and counting every clock cycle from the start of the data reference. A group of reference order data in which a counter to be performed and a data storage order and an access order are associated with each other are stored, and when the count value of the counter is input as access data, the reference order data corresponding thereto is generated. An address generator having reference order data generation means and addition means for adding a start address of data to be referred to the reference order data to generate a storage address of data stored in the storage device; It has an arithmetic and control unit that processes the stored data in the access order.

A memory access method for accessing the data in an order different from the order of the data stored in the storage device, wherein a reference in which the storage order of the data recorded in the recording device corresponds to the access order. Sequential data is stored, and the reference data is used to generate the storage address of the corresponding data from the given access data.

The storage address of the data recorded in the recording device is generated every clock cycle.

The data recorded in the recording device is image data arranged two-dimensionally.

Further, the reference order data is data of an order of performing zigzag scanning on the data recorded in the recording device.

[0029]

The address generating method and apparatus according to the present invention has a table storing data of memory access order. The data in the memory access order stored in this table is read out for each clock cycle for each port, and the start address set for each port is added to generate the address in an arbitrary memory access order.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the address generating method and apparatus of the present invention will be described below. FIG. 1 is a diagram showing a configuration of an address generator 1 of the present invention. The address generator 1 sets the address used for memory access to 1 corresponding to each of m ports of the memory 6 of the computer.
It is a device that is automatically generated every clock cycle.

Here, as shown in the figure, the adders 13a to 13m are connected to the respective ports of the table memory 12 so that the addresses corresponding to the respective ports can be simultaneously generated. The maximum number of memories that can be accessed by a series of memory accesses (address sequence) by the address generator 1 is p. That is, the address generator 1 can generate at most p addresses in one address sequence.

In FIG. 1, the counter 4 is a computer M
A numerical value corresponding to the sequence ID set by PU5 is generated, and this numerical value is further incremented every clock cycle. The table memory 12 is composed of m fields 0 to m-1 provided corresponding to the ports 0 to m-1 of the computer, and each is capable of storing n words.

Therefore, the number of address sequences that can be stored in each field of the table memory 12 is [n / p]. Here, each word is [log ₂ p] + from the maximum access memory number p of one address sequence.
1 (however, [x] represents the maximum integer not exceeding x.)
It has a bit structure.

As shown in the drawing, each word of the table memory 12 is provided with, for example, 1-bit address sequence control flags E _{1 to} E _n-1, which address sequence control flags E _{1 to} E. _{When n-1} is 1, it indicates the end of each address sequence.

The adder circuits 13a to 13m add the m number of start addresses set by the MPU ₅ and stored in the start address registers 15 ₀ to 15 _m-1 and the address input from the corresponding field of the table memory 12. And output. The start address may be stored in any register other than the start address register 15, for example, a register used in the peripheral circuit of the MPU 5.

The flag check circuit 14 reads the address sequence control flag and outputs the value every time the counter 4 counts. Start address register 15
Stores the start address on the memory 6 corresponding to each address sequence.

The MPU 5 is the MPU of the computer in which the address generator 1 is used. The memory 6 has m ports and stores various data of a computer in which the address generator 1 is used. The DSP 7 performs calculations such as image calculations in the computer in which the address generator 1 is used.

The operation of the address generator 1 will be described below. When the MPU 5 executes the instruction to activate the generator 1, first, the address sequence ID is set in the counter 4. Here, the address sequence ID is an identifier for identifying the address sequence stored in the table memory 12. The address sequence ID may be set in the counter 4 directly by the DSP 7 as shown by the dotted line in FIG.

The counter 4 receives the address sequence I
Counting is started from the numerical value (offset) of the address of the table memory 12 corresponding to D, and the table memory 12
To enter. The table memory 12 adds the word of each field corresponding to the count value of the counter 4 to the adder circuit 13a.
Input to ~ 13m-1.

That is, for example, when the count value of the counter 4 is k (k is an integer, 0≤k≤n-1), the adder circuit 13a includes the data at the address A _{0, k} of the table memory 12 and the adder circuit 13b. The data of the address A _{1, k} of the table memory 12 is input to the adder circuit 13n-1, and the data of the address A _{n-1, k} of the table memory 12 is input to the adder circuit 13n-1.

The adder circuits 13a to 13m-1 add the start address registers 15 ₀ to 15 of the two-dimensional address generating circuit 2 to the input data of each address of the table memory 12.
The start address corresponding to each port stored in _m-1 is added to obtain the address used for accessing the memory 6 corresponding to each port. The memory 6 to which this address is input is
The data is output to the MPU 5 or the DSP 6 corresponding to the port. The MPU 5 and DSP 7 perform, for example, image processing based on this data.

By the addition in the adder circuits 13a to 13m-1, it is possible to generate the access address to the data memory by the relative address stored in the table memory 12. By configuring the address generator 1 in this way, each port can perform memory access in an arbitrary order simply by changing the numerical value stored in the table memory 12.

The address generator 1 sequentially generates addresses each time the counter 4 counts as described above.
Here, the value of the address sequence control flag is 0 in the middle of one address sequence and 1 at the end.

When the count of the counter 4 reaches a numerical value indicating the last address of the address sequence corresponding to the address sequence ID set in the counter 4, the output of the flag check circuit 14 becomes a logical value 1 (asserted). , MPU5, etc. are notified that the address sequence has ended. The address sequence generated by the address generator 1 and the two-dimensional address generator 2
The computer may be configured so that the address sequence generated in step 1 is also used.

The operation of the address generator 1 will be illustrated below by using specific numerical values. FIG. 2 shows an address generator 5 that generates an address sequence when performing zigzag scanning. The address generator 5 is a device that generates an address sequence for performing the zigzag scan as shown in FIG. 4 for the rectangular area shown in FIG.

In the address generator 5, only one address sequence is generated, and therefore the address sequence ID is not set in the counter 4. Therefore, when the address generator 5 is activated, the counter 4 always starts counting from 0.

The table memory 12 has 4 fields × 1.
It consists of 6 words. That is, according to the address sequence generated by the address generator 5, the four arithmetic units connected to the respective ports process the four data in parallel in one clock cycle. Also, the table memory 1
The numerical value written in 2 is the value of the relative address generated by the address sequence for performing the zigzag scan. Also, address sequence control flag, memory 6, DSP
7 and the like are omitted in FIG. Address generator 5
The respective parts of 1 correspond to the parts of the address generator 1 indicated by the same reference numerals.

The operation of the address generator 5 will be described below with reference to FIGS. 2, 3 and 4. Figure 3 shows 8x8
FIG. 4 is a diagram showing a rectangular area (data block) of, and the entered numerical values are memory addresses. FIG. 4 shows FIG.
FIG. 7 is a diagram showing the order of address sequences generated by the address generator 5 in the data block shown in FIG.

As can be seen with reference to FIGS. 3 and 4, the adder circuits 13a to 13d have numerical values (0, 1, 8, 1) corresponding to the address of FIG. 3 in the first clock cycle.
6) will be output. In the next clock cycle, the numerical values (9, 2, 3, 10) corresponding to the addresses of FIG. 3 are output to the adder circuits 13a to 13d. In this way, the relative addresses are sequentially output to the adder circuits 13a to 13d.

When the address generator 5 is activated, the counter 4 sequentially starts counting from 0 every clock cycle. When the count value of the counter 4 is 0, the numerical value (0, 1, 8, 16) of 0 word of the table memory 12 is output to each of the adding circuits 13a to 13d.

This value contains the start address register 15₁~
15_FourThe start address value stored in
Output. However, in the address generator 5
Is the start address register 15₁~ 15 _FourRemembered in
Since the data has the same value, a single start address register
The star 15 may be provided.

After that, in each clock cycle, the adder circuits 13a to 13d have (9, 2, 3, 10) in the second clock cycle, ... 47, 55, 62, 63) are output, and the start addresses stored in the start address registers 15 ₁ to 15 ₄ are added to produce an address output.

The numerical value of the last word is the table memory 12
, The output value of the flag check circuit 14 (not shown in FIG. 2) is asserted, and this address sequence ends. To realize an address sequence for accessing another 8 × 8 data block on the data memory in which the data block shown in FIG. 3 is stored, the start addresses set in the start address registers 15 ₁ to 15 ₄ can be changed. Good.

The table memory 12 can be created by a method of fixedly storing it in the ROM or setting it in the RAM of the computer when the computer is started up. In addition to the above-described embodiments, the address generating method and the apparatus therefor of the present invention can have various configurations such as those described as modifications. The embodiments described above are merely examples.

[0055]

As described above, according to the present invention, it is possible to generate an arbitrary address sequence such as a zigzag scan with a device having a simple structure. Further, an arbitrary address sequence can be generated for each clock without software-like calculation, which does not increase the amount of software and does not reduce the calculation speed. Also, since a single device can handle many ports, it is possible to suppress an increase in the hardware amount of the computer.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an address generator of the present invention.

FIG. 2 is an address generator that generates an address sequence when performing zigzag scanning.

FIG. 3 is a diagram showing an 8 × 8 data block.

4 is a diagram showing an order of an address sequence generated by an address generator in the data block shown in FIG.

FIG. 5 is a diagram illustrating a region that can be regarded as a rectangular region during image processing or the like.

FIG. 6 is a diagram showing a configuration of a two-dimensional address generation circuit.

[Explanation of symbols]

 1, 5 ... Address generator 4 ... Counter 5 ... MPU 6 ... Memory 7 ... DSP 12 ... Table memory 13 ... Addition circuit 14 ... Flag check circuit

Claims (10)

[Claims] 1. A device for generating addresses for accessing the data in an order different from the order of the data stored in the storage device, the counter performing counting every clock cycle from the start of data reference, and the data. A group of reference order data in which the storage order and the access order are associated with each other, and when the count value of the counter is input as the access data, the reference order data generation means for generating the corresponding reference order data. And an adding unit that adds a start address of data to be referred to the reference order data to generate a storage address of data stored in the storage device. 2. The reference data generating means has a plurality of output terminals, and the reference order data is stored such that a plurality of reference order data related to one access are simultaneously output. A plurality of reference data corresponding to the count value are simultaneously generated corresponding to the ports, a plurality of the adding means are provided for each output terminal, and the plurality of reference order data output at the same time are respectively stored in the storage device. The address generating device according to claim 1, wherein a storage address of the data is generated by adding a start address of the data to be stored. 3. The reference data generation means further stores an end identifier indicating whether each element data of the reference order data is the final data, and the end identifier indicates the final data. 3. The address generating device according to claim 1, further comprising an end identifying means for identifying the end of the reference order data when the element data of the reference order data is read. 4. The address generating device according to claim 1, wherein the data is image data arranged two-dimensionally. 5. The address generating device according to claim 1, wherein the reference order data is data for performing zigzag scanning on the data stored in the storage device. 6. A storage device, and a device for generating addresses for accessing the data in an order different from the order of data stored in the storage device, wherein a count is made every clock cycle from the start of data reference. A counter to be performed and a group of reference order data in which the storage order of data and the access order of data are stored, and when the count value of the counter is input as access data, the reference order data corresponding thereto is generated. An address generation device having a reference order data generation unit and an addition unit configured to add a start address of data to be referred to the reference order data to generate a storage address of data stored in the storage device; Signal processing device having arithmetic and control unit for processing stored data in the access order 7. A memory access method for accessing the data in an order different from the order of the data stored in the storage device, wherein a reference in which the storage order of the data stored in the storage device corresponds to the access order. An address generation method of storing sequence data and generating a storage address of corresponding data from access data given by using this reference sequence data. 8. The address generating method according to claim 7, wherein the storage address of the data stored in the storage device is generated every clock cycle. 9. The address generating method according to claim 7, wherein the data stored in the storage device is image data arranged two-dimensionally. 10. The address generating method according to claim 7, wherein the reference order data is data in an order of performing zigzag scanning on the data stored in the storage device.