JPH0621376A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To lessen the area of an internal step-down circuit and to make a stress be applied on the internal step-down circuit in a semiconductor storage device which has the internal step-down circuit incorporated and makes an internal supply voltage and an external supply voltage equal in a stress mode. CONSTITUTION:A P channel transistor 6 connecting an internal supply voltage line 1 with an external supply voltage line 2 at the normal mode is used also in a stress mode, and a level shifter circuit 3, a reference voltage generating circuit 4 and a differential amplifier circuit 5 are put in an active state in the stress mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an internal step-down circuit for generating an internal power supply voltage by dropping an external power supply voltage and supplying the internal power supply voltage to a semiconductor memory device, which is a special mode of the semiconductor memory device. The present invention relates to a semiconductor memory device that can realize a stress mode function.

[0002]

2. Description of the Related Art In a conventional semiconductor memory device, a power supply voltage input from the outside is used as it is as a power supply voltage for driving an internal storage circuit. However, with the recent increase in capacity of semiconductor memory devices, transistors have been miniaturized, and a method of stepping down an external power supply voltage has been widely proposed in order to improve its reliability and reduce current consumption. became.

By the way, generally, a semiconductor memory device contains a slight defect due to miniaturization, and at the time of manufacturing, even a non-defective product is included at a ratio of chips which are defective due to short-term use. Therefore, on the manufacturer side, it is usual to carry out continuous operation for several tens of hours to several days at high temperature / high voltage, and to screen by previously selecting the chips having the above defects.
This high temperature / high voltage continuous operation test is called a burn-in test.

However, the internal voltage down converter generates a constant voltage as shown in FIG. Therefore, in the semiconductor memory device having the internal voltage down converting circuit, the internal power supply voltage becomes constant even if the external power supply voltage is increased, and the burn-in test cannot be performed. Therefore, in the burn-in test, there is a method of connecting the internal power supply voltage line and the external power supply voltage line to make the internal power supply voltage and the external power supply voltage equal as shown in FIG. The test function by this method is called the stress mode function.

FIG. 15 is a schematic block diagram showing an example of a semiconductor memory device having such a stress mode function. Referring to FIG. 15, this semiconductor memory device 100
Is an external power supply voltage terminal 101 for inputting an external power supply voltage,
It includes an internal step-down circuit 102 for stepping down an external power supply voltage, a memory circuit 103 driven by an internal power supply voltage stepped down by internal step-down circuit 102, and a / SM terminal for inputting stress mode signal / SM.

In operation, the stress mode signal / SM
In response to this, the internal step-down circuit 102 operates the external power supply voltage line 1
And the internal power supply voltage line 2 are connected. As a result, the external power supply voltage is supplied to the memory circuit 103, and the burn-in test can be performed.

FIG. 16 is a circuit diagram showing a conventional internal voltage down converting circuit having a function of equalizing the internal power supply voltage and the external power supply voltage.

In FIG. 16, the internal voltage down converting circuit has an external power supply voltage line 1, an internal power supply voltage line 2, a level shifter circuit 3 for generating a voltage Vs obtained by shifting down the level of the internal power supply voltage, and a constant internal power supply voltage. A reference voltage generating circuit 4 for generating a reference voltage Vref for reducing the voltage Vs and a differential amplifier circuit 5 for amplifying a difference between the voltage Vs and the reference voltage Vref,
P that is connected between the external power supply voltage line 1 and the internal power supply voltage line 2 and turns on / off in response to the output of the differential amplifier circuit 5
Channel transistor 6 and P-channel transistor 6
And a P-channel transistor 19 connected in parallel with and turning on / off in response to the stress mode signal / SM. The stress mode signal / SM has a low level in the stress mode.

The external power supply voltage line 1 is connected to the external power supply terminal 101.
The internal power supply voltage line 2 is connected to the memory circuit (see FIG.
5) is connected.

The level shifter circuit 3 includes an internal power supply voltage line 1
And is activated in response to the stress mode signal / SM (high level) to lower the level of the internal power supply voltage by a constant voltage to generate the voltage Vs. This level shifter circuit 3
Responds to the stress mode signal / SM (low level),
It becomes inactive. The voltage Vs is supplied to the differential amplifier circuit 5.

The reference voltage generating circuit 4 is activated in response to the stress mode signal / SM (high level), and the reference voltage V
ref is generated and becomes inactive in response to the stress mode signal / SM (low level). The reference voltage Vref is supplied to the differential amplifier circuit 5.

Differential amplifier circuit 5 has two input terminals and one output terminal, one input terminal is connected to receive voltage Vs, and the other input terminal is reference voltage Vref.
The output terminal is connected to the gate electrode of the P-channel transistor 6. The differential amplifier circuit 5 compares the voltage Vs with the reference voltage Vref to obtain Vre
When f> Vs, a low level signal is output and Vre
When f <Vs, a high level signal is output.

In the P-channel transistor 6, the drain (or source) is connected to the external power supply voltage line 1, the source (or drain) is connected to the internal power supply voltage line 2,
The gate electrode is connected to the output of the differential amplifier circuit 5.

The P-channel transistor 19 has a drain (or source) connected to the external power supply voltage line 1 and a source (or drain) connected to the internal power supply voltage line 2,
The gate electrode is connected to receive the stress mode signal / SM.

The P-channel transistors 6 and 19
Since it is necessary to supply the power supply voltage to the memory circuit 103, the current driving capability thereof is increased, and the memory circuit 103 has a relatively large size.

Next, the operation of the voltage drop circuit shown in FIG. 16 will be described.

The internal power supply voltage is leveled down by the level shifter circuit 3 to become the voltage Vs. This voltage Vs
When the level of is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low level. In response to this low level output, P channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected.

On the contrary, when the internal power supply voltage becomes higher and the output voltage Vs of the level shifter circuit 3 becomes higher than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes high level, and this high level output is generated. In response to the signal, P channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are disconnected.

By controlling the P-channel transistor 6 to be turned on / off in this manner, the internal power supply voltage can be kept constant.

Next, in the stress mode, the stress mode signal / SM goes low and the P-channel transistor 19 is turned on. On the other hand, the level shifter circuit 3, the reference voltage generating circuit 4, and the differential amplifier circuit 5 are inactivated, and the output of the differential amplifier circuit 5 becomes high level. In response, P channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are connected to P channel transistor 1
Connected by 9.

As a result, the external power supply voltage can be applied to the internal memory circuit in the stress mode.

[0022]

As described above,
In the conventional internal voltage step-down circuit, in the stress mode (stress mode signal / SM is at a high level), the P-channel transistor 6 turns on / off between the external power supply voltage line 1 and the internal power supply voltage line 2 to keep the voltage constant. An internal power supply voltage is generated, and in the stress mode, the P-channel transistor 19 connects the external power supply voltage line to the internal power supply voltage line. Since the two relatively large transistors 6 and 19 are used as described above, there is a problem that the area of the internal voltage down converting circuit and hence the semiconductor memory device becomes large.

In the stress mode, the level shifter circuit 3, the reference voltage generating circuit 4 and the differential amplifier circuit 5 are deactivated so that the level shifter circuit 3, the reference voltage generating circuit 4 and the differential amplifier circuit 5 are deactivated. There is a problem that stress is not applied and a burn-in test cannot be performed on these circuits.

One object of the present invention is to reduce the area of an internal voltage down converting circuit in a semiconductor memory device having an internal voltage down converting circuit.

Another object of the present invention is to make it possible to perform a burn-in test on an internal voltage down converting circuit.

[0026]

According to another aspect of the present invention, there is provided an internal memory circuit and an internal step-down circuit for generating an internal power supply voltage by lowering an external power supply voltage and supplying the internal power supply voltage to the internal storage circuit. A semiconductor memory device comprising:
The internal step-down circuit has a stress mode test function of applying an external power supply voltage to the internal storage circuit, and is provided between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means for turning on / off the power supply, level drop means for lowering the level of the internal power supply voltage, reference voltage generation means for generating a reference voltage for keeping the level of the internal power supply voltage constant, and the reference voltage generation The switching means includes a control means for comparing the reference voltage generated by the means with the internal power supply voltage condensed by the level lowering means, and for controlling the switching means on / off based on the comparison result, wherein the switching means It is characterized in that it is always turned on in the mode.

A semiconductor memory device according to the invention of claim 2 is
It includes switching means and level dropping means similar to those of claim 1, and further includes first reference voltage generating means, pull-up means and control means.

The first reference voltage generating means generates a first reference voltage for keeping the internal power supply voltage constant.

The pull-up means pulls up the first reference voltage in the stress mode and generates a second reference voltage having a potential higher than the internal power supply voltage lowered by the level lowering means.

The control means compares the generated first or second reference voltage with the lowered internal power supply voltage,
When the first or second reference voltage is higher than the lowered internal power supply voltage, the switching means is turned on, and the first or second reference voltage is higher than the lowered internal power supply voltage. If is also low, the switching means is turned off.

A semiconductor memory device according to a third aspect of the present invention is
It includes switching means and reference voltage generating means similar to those of the first aspect, and further includes the following level drop means and control means.

The level lowering means converts the level of the internal power supply voltage into the lowered first voltage in the normal operation, and further lowers the first voltage to lower the reference voltage in the stress mode. Convert to a second voltage of potential.

The control means compares the generated reference voltage with the first or second voltage converted by the level lowering means, and if the reference voltage is higher than the first or second voltage. Turns on the switching means, and turns off the switching means when the reference voltage is lower than the first or second voltage.

According to another aspect of the semiconductor memory device of the present invention,
It includes switching means, level dropping means, and reference voltage generating means similar to those of the invention of claim 1, and further includes first control means and second control means.

The first control means compares the reference voltage generated by the reference voltage generation means with the internal power supply voltage lowered by the level lowering means, and controls the switching means on / off based on the comparison result.

The second control means always turns on the switching means in response to an externally generated stress mode signal. In the stress mode, at least one of the level lowering means, the reference voltage generating means, and the first control means is inactivated.

A semiconductor memory device according to a fifth aspect of the present invention is
A switching means, a level lowering means, a reference voltage generating means, a first control means and a second control means similar to those of the invention of claim 4 are included, and further, between the first control means and the second control means. And means for switching off in response to the stress mode signal.

[0038]

In the semiconductor memory device according to the first aspect of the present invention, there is one switching means for turning on / off between the external power supply voltage line and the internal power supply voltage line, and this switching means is turned on / off in the normal mode. The internal power supply voltage is kept constant by turning it off, and it is always turned on in the stress mode. By sharing the switching means requiring a relatively large size in the normal mode and the stress mode in this manner, the area of the internal voltage down converting circuit and hence the semiconductor memory device can be reduced.

In the semiconductor memory device according to the second aspect of the present invention, the pull-up means generates the second reference voltage higher than the internal power supply voltage lowered in the stress mode. In the mode, the switch means is always on. Thereby, the internal power supply voltage can be made equal to the external power supply voltage. Thus, even in the stress mode, the burn-in test can be performed with all means included in the internal voltage down converting circuit active. As a result, all the means included in the internal voltage down converter can be stressed.

In the semiconductor memory device according to the third aspect of the present invention, since the level lowering means generates the second voltage higher than the reference voltage in the stress mode, the control means turns on the switching means. . Therefore, in the invention of claim 3, as in the invention of claim 2, one switching means can be shared, and in the stress mode, all means included in the internal voltage down converting circuit are activated to reduce stress. You can call.

According to another aspect of the semiconductor memory device of the present invention, at least one of the level lowering means, the reference voltage generating means, and the first control means is inactivated by an externally generated stress mode signal. However, the second control means turns on the switching means in response to an externally generated test mode signal. As a result, the internal power supply voltage line and the external power supply voltage line are connected, and the burn-in test can be performed.

In the semiconductor memory device according to the fifth aspect of the present invention, since the first control means and the second control means are disconnected from each other in the stress mode, the level drop means, the reference voltage generation means, and the first control means. The burn-in test can be performed with all of the control means of (1) kept active. Thereby, stress can be applied to all the means included in the internal voltage down converter.

[0043]

1 is a circuit diagram showing an embodiment of an internal voltage down converting circuit incorporated in a semiconductor memory device. 1 includes an external power supply voltage 1, an internal power supply voltage 2, a level shifter circuit 3 which is always activated, a reference voltage generating circuit 4 which is always activated, and a differential amplifier which is always activated. It includes a circuit 5, a P-channel transistor 6, and a pull-up circuit 41 that pulls up the reference voltage Vref in response to the stress mode signal / SM.

External power supply voltage line 1, internal power supply voltage line 2 and P-channel transistor 6 have the same structure as the internal voltage down converting circuit shown in FIG. The level shifter circuit 3, the reference voltage generation circuit 4, and the differential amplifier circuit 5 perform the same operations as the normal operation of the level shifter circuit, the reference voltage generation circuit, and the differential amplifier circuit shown in FIG.

The pull-up circuit 41 includes an inverter 91 and a clocked CMOS 10. The inverter 91 is
Clocked CM by inverting stress mode signal / SM
It controls the OS 10. The clocked CMOS 10 has its input connected to the ground terminal and its output connected to the reference voltage line 7 that outputs the reference voltage. Pull-up circuit 4
1 raises the reference voltage line 7 to the power supply potential when the stress mode signal / SM is low level.

Next, the operation of the internal voltage down converting circuit shown in FIG. 1 will be described. First, in the normal mode, the level shifter circuit 3 levels down the internal power supply voltage and generates the voltage Vs. This voltage Vs is supplied to the differential amplifier circuit 5. The reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. When the voltage Vs from the level shifter circuit 3 is lower than the reference voltage Vref generated by the reference voltage generation circuit 4,
The output of the differential amplifier circuit 5 becomes low level. In response to this low level output, the P-channel transistor 6 turns on,
External power supply voltage line 1 and internal power supply voltage line 2 are connected.
When the internal power supply voltage becomes high, the level shifter circuit 3
As a result, the level of the voltage Vs which has been lowered is also increased. When this voltage Vs becomes higher than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes high level, the P-channel transistor 6 is turned off, and the external power supply voltage line 1 is disconnected from the internal power supply voltage line 2. The above operation is similar to the conventional example.

Next, the operation in the stress mode will be described. Since the reference voltage generation circuit 4 is always activated, it tries to generate the reference voltage Vref in the normal mode. However, the pull-up circuit 41 responds to the stress mode signal / SM (low level) to generate the reference voltage Vref. Raise the potential of the voltage line to the power supply potential. As a result, the level of the output Vs of the level shifter circuit 3 becomes lower than the level of the reference voltage line 7. Therefore, the output of the differential amplifier circuit 5 becomes low level, and the P-channel transistor 6 is always turned on in response to the low level output. Thereby, the external power supply voltage line 1 and the internal power supply voltage line 2 can be connected.

The internal step-down circuit shown in FIG. 1 can have a relatively large P-channel transistor connected between the external power supply voltage line 1 and the internal power supply voltage line 2, The area of the internal voltage down converter can be reduced. Further, since the level shifter circuit 3, the reference voltage generation circuit 4, and the differential amplifier circuit 5 are always activated, stress is applied even in the stress mode.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The difference between the internal step-down circuit shown in FIG. 2 and the internal step-down circuit shown in FIG.
The MOS transfer gate 11 is provided, and the inverter 92 connected to the gate electrode of the PMOS transistor forming the transfer gate is provided. The CMOS transfer gate 11 and the inverter 92 turn on / off in response to the stress mode signal / SM.

Next, the operation of the second embodiment will be described. In the normal mode, the stress mode signal / SM is at high level and the CMOS transfer gate 11 is turned on. Therefore, the reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. When the level of the voltage Vs obtained by leveling down the internal power supply voltage by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low level. In response to this low level output, the P channel transistor 6 is turned on. Thereby, the external power supply voltage line and the internal power supply voltage line are connected. Further, when the internal power supply voltage rises, the level of the output voltage Vs of the level shifter circuit 3 changes to the reference voltage Vs.
It becomes higher than ref, and the output of the differential amplifier circuit 5 becomes high level. In response to this high level output, P channel transistor 6 is turned off, and external power supply voltage line 1 and internal power supply voltage line 2 are disconnected.

Next, in the stress mode, the reference voltage Vref is set by the reference voltage generating circuit 4 which is always activated.
However, since the stress mode signal / SM is at a low level, the CMOS transfer gate 11 is off and the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, the clocked CMOS 10 turns on in response to the stress mode signal / SM (low level), so that the level of the reference voltage line 7 becomes high level (external power supply voltage level). Therefore, the level of the output voltage Vs of the level shifter circuit 3 is always lower than the potential of the reference voltage line 7. As a result, the output of the differential amplifier circuit 5 becomes low level, and in response, the P-channel transistor 6 is always turned on. In this way, the external power supply voltage line 1 and the internal power supply voltage line 2 can be connected.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The internal voltage down converter shown in FIG. 3 differs from the internal voltage down converter shown in FIG. 2 in that instead of the CMOS transfer gate 11 and the inverter 92, an N channel transfer gate 12 that turns on / off in response to a stress mode signal / SM is provided. It is provided. The other circuits are the same as those shown in FIG. 2, and the description thereof will be omitted as appropriate.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level and the N-channel transfer gate 12 is on, so the output of the reference voltage generation circuit 4 is sent to the differential amplifier circuit 5 via the reference voltage line 7. Supplied. Therefore, when the level of the voltage Vs lowered by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes low level. In response to this low level output, P channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected. Further, when the internal power supply voltage rises, the level of the voltage Vs lowered by the level shifter circuit 3 becomes higher than the reference voltage Vref, and the output of the differential amplifier circuit 5 becomes high level. In response to this high level output, the P-channel transistor 6 turns off, and the external power supply voltage line 1 and the internal power supply voltage line 2
And are separated.

Next, in the stress mode, the reference voltage Vref is output from the activated reference voltage generating circuit 4, but the N-channel transfer gate 12 is turned off because the stress mode signal / SM is at the low level. There is. Therefore, the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the clocked CMOS 10 is turned on, the reference voltage line 7 becomes high level (external power supply voltage level). The subsequent operation in the stress mode is the same as in the case of FIG. 2, and the description thereof will be omitted.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. The difference between the fourth embodiment and the first embodiment is only the pull-up circuit, and FIG. 4 shows only the pull-up circuit.

In FIG. 4, a P-channel transistor 13 is used as the pull-up circuit. P-channel transistor 13 has its source (or drain) connected to the power supply voltage, its drain (or source) connected to reference voltage line 7, and its gate electrode connected to receive stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level and the P-channel transistor 13 is off. Therefore, the reference voltage Vref generated by the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. The subsequent normal operation is the same as that shown in FIG. 1, and the description thereof is omitted.

Next, in the stress mode, the reference voltage Vref is activated by the reference voltage generating circuit 4 which is activated.
However, since the stress mode signal / SM is at a low level, the P-channel transistor 13 turns on,
The reference voltage line 7 is forced to a high level (external power supply voltage level). The subsequent operation is the same as that of the first embodiment shown in FIG. 1, and the description thereof is omitted.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention. The circuit shown in FIG. 5 differs from the circuit shown in FIG. 2 in that the pull-up circuit 41 is replaced by the P-channel transistor 13 shown in FIG. In FIG. 5, the differential amplifier circuit, the level shifter circuit, and the like are the same as those in FIG. 2, and the description thereof is omitted for simplification of the display.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, the P-channel transistor 13 is turned off, and the CM
Since the OS transfer gate 11 is turned on, the output Vref of the reference voltage generation circuit 4 is supplied to the differential amplifier circuit 5. The subsequent operation in the normal mode is the same as that shown in the first to fourth embodiments, and the description thereof will be omitted.

Next, in the stress mode, the reference voltage Vref is generated by the activated reference voltage generating circuit 4, but since the stress mode signal / SM is at the low level, the CMOS transfer gate 11 is off, The reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the P-channel transistor 13 is turned on in response to the stress mode signal / SM (low level), the potential of the reference voltage line 7 becomes high level (external power supply voltage level). The subsequent operation in the stress mode is the same as in the first to fourth embodiments, and the description thereof is omitted.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention. The circuit shown in FIG. 6 differs from the circuit shown in FIG. 7 in that instead of CMOS transfer gate 11 and inverter 92, N-channel transistor 12 shown in FIG. 3 is provided.

Next, the operation will be described. First, in the normal mode, since the stress mode signal / SM is at a high level, the P-channel transistor 13 is off and the N-channel transfer gate 12 is on. Therefore, the reference voltage Vref generated by the reference voltage generating circuit 4 is It is supplied to the differential amplifier circuit 5. The subsequent operation in the normal mode is the same as that shown in the first to fifth embodiments, and the description thereof is omitted.

Next, in the stress mode, the reference voltage Vref is generated by the reference voltage generating circuit 4 which is in an active state. However, since the stress mode signal / SM is at the low level, the N channel transfer gate 12 is turned off. Therefore, the reference voltage Vref is not transmitted to the differential amplifier circuit 5. On the other hand, since the P-channel transistor 13 turns on in response to the stress mode signal / SM (low level),
The potential of the reference voltage line 7 becomes high level (external power supply voltage level). Subsequent operations in the stress mode are the same as those in the first to fifth embodiments, and the description thereof will be omitted.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention. Also in FIG. 7, description of the external power supply voltage line 1, the internal power supply voltage line 2, the level shifter circuit 3, and the differential amplifier circuit 5 is omitted. The difference between the circuit shown in FIG. 7 and the circuit shown in FIG. 1 is that reference voltage generating circuit 4 is inactivated by stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level and the clocked CMOS 10 is off. Reference voltage generating circuit 4 is deactivated when stress mode signal / SM is at low level and activated when it is at high level. Therefore, reference voltage generating circuit 4 generates reference voltage Vref only in the normal mode. Therefore, the operation in the normal mode is similar to that of the first to sixth embodiments, and the description thereof will be omitted.

Next, in the stress mode, since the stress mode signal / SM is at the low level, the reference voltage generating circuit 4
Are deactivated. In addition, the clocked CMOS 10
Turns on, the reference voltage Vref becomes a high level (external power supply voltage level). Therefore, the level of the voltage Vs whose level is lowered by the level shifter circuit 3 is always lower than the reference voltage Vref, and the output of the differential amplifier circuit 5 is low level. P in response to this low level output
The channel transistor 6 is always turned on, and the external power supply voltage line 1 and the internal power supply voltage line 2 are connected.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

In FIG. 8, the external power supply voltage line 1,
Descriptions of the internal power supply voltage line 2, the level shifter circuit 3, and the differential amplifier circuit 5 are omitted. The difference between the circuit shown in FIG. 8 and the circuit shown in FIG. 4 is that the reference voltage generating circuit 4 is inactivated by the stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level and the P-channel transistor 13 is off.
Further, the reference voltage generating circuit 4 in the normal mode is inactivated when the stress mode signal / SM is at a low level and activated when it is at a high level. Therefore, the reference voltage Vref is generated in the normal mode. The generated reference voltage Vref is supplied to the differential amplifier circuit 5. The subsequent operation in the normal mode is similar to that of the first to seventh embodiments, and the description thereof will be omitted.

Next, in the stress mode, since the stress mode signal / SM is at the low level, the reference voltage generating circuit 4 is inactivated. On the other hand, the P-channel transistor 13 is turned on in response to the stress mode signal / SM, so that the potential of the reference voltage line 7 becomes high level (external power supply voltage level). The subsequent operation in the stress mode is the same as in the first to seventh embodiments, and the description thereof will be omitted.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention. The difference between the internal voltage down converter shown in FIG. 9 and the internal voltage down converter shown in FIG. 1 is that the pull-up circuit is omitted and instead of the level shifter circuit 3 that generates the voltage Vs,
That is, the level shifter circuit 31 capable of outputting the voltage Vs and the threshold voltage of the PMOS transistor is provided.

The level shifter circuit 31 has two electrodes and 1
It includes P-channel transistors 14 and 15 having one control electrode, and an inverter 93. P-channel transistor 14 has one electrode connected to internal power supply voltage line 2, the other electrode connected to one electrode of P-channel transistor 15, and the gate electrode connected to the output of inverter 93. The other electrode of the P-channel transistor 15 is connected to the ground potential, and its gate electrode is connected to the ground potential. The inverter 93 has its input terminal connected so as to receive the stress mode signal / SM,
Its output terminal is connected to the gate electrode of the P-channel transistor 14. The connection point between the P-channel transistors 14 and 15 is connected to the differential amplifier circuit 5.

Next, the operation will be described. First, in normal mode, stress mode signal / SM is at a high level and P-channel transistors 14 and 15 are both on, so that the resistance division divides the level of the internal power supply voltage. Thereby, the value of the voltage Vs is determined. Further, the reference voltage generating circuit 4 generates a reference voltage Vref having a certain constant value. Therefore, when the level of the voltage Vs whose level has been lowered by the level shifter circuit 3 is lower than the reference voltage Vref, the output of the differential amplifier circuit 5 becomes a low level. In response to this low level output, P channel transistor 6 is turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected. Also,
When the internal power supply voltage rises, the level of the voltage Vs lowered by the level shifter circuit 3 becomes the reference voltage Vr.
It is higher than ef. In this case, the output of the differential amplifier circuit 5 becomes high level, the P-channel transistor 6 is turned off, and the external power supply voltage line 1 and the internal power supply voltage line 2 are disconnected.

Next, in the stress mode, since the stress mode signal / SM is at the low level, the P-channel transistor 14 is off and the P-channel transistor 15 is on, so the output Vs of the level shifter circuit 3 is
It becomes the level of the threshold voltage of P-channel transistor 15. Further, although the reference voltage Vref having a constant value is generated by the reference voltage generation circuit 4, this reference voltage Vref
When the value of ref is set to a value larger than the value of the voltage Vs (threshold voltage Vtp), the output of the differential amplifier circuit 5 becomes low level and the P-channel transistor 6 is always turned on. As a result, the external power supply voltage line 1 and the internal power supply voltage line 2 are connected.

FIG. 10 is a circuit diagram showing a tenth embodiment of the present invention. The difference between the internal voltage down converter shown in FIG. 10 and the internal voltage down converter shown in FIG. 9 is that the voltage Vs or Vtp is different.
Voltage Vs or ground potential GN instead of the level shifter circuit for generating (threshold voltage of p-channel transistor)
That is, the level shifter circuit 32 that outputs D is provided. The level shifter circuit 32 has an N-channel transistor 17 and an inverter 94 added to the level shifter circuit shown in FIG. The N-channel transistor 17 has one electrode connected to the differential amplifier circuit 5, the other electrode connected to the ground potential, and the gate electrode connected to the inverter 94. Inverter 94
Are connected to receive the stress mode signal / SM.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, and the P-channel transistors 14 and 15 are
Both are on, and the N-channel transistor 17 is off. Therefore, the output voltage V of the level shifter circuit 32
In s, the level of the internal power supply voltage is lowered due to the resistance division of the P-channel transistors 14 and 15.
The value of Vs is determined. The subsequent operation in the normal mode is similar to that of the ninth embodiment, and the description thereof is omitted.

Next, in the stress mode, since the stress mode signal / SM is at the low level, the P channel transistors 14 and 15 are off and the N channel transistor 17 is on. Therefore, the output voltage Vs of the level shifter circuit 32 becomes a low level (ground level) and becomes smaller than the value of the reference voltage Vref, so that the output of the differential amplifier circuit 5 becomes a low level. In response to this low level output, the P-channel transistor 6 is always turned on,
External power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 11 is a circuit diagram showing an eleventh embodiment of the present invention. The difference between the internal voltage down converter shown in FIG. 11 and the internal voltage down converter shown in FIG. 1 is that instead of the differential amplifier which is always activated, the differential amplifier which is inactivated by the stress mode signal / SM. 5 is provided, and a circuit 51 for always turning on the P-channel transistor 6 in response to the stress mode signal / SM is provided. Circuit 51 includes N-channel transistor 18 and inverter 95. One electrode of the N-channel transistor 18 has the P-channel transistor 6
, The other electrode is connected to the ground terminal, and the gate electrode is connected to the output of the inverter 95. The inverter 95 uses the stress mode signal / SM
Connected to receive.

In the normal mode of operation, stress mode signal / SM is at a high level and N-channel transistor 18 is off. The differential amplifier circuit 5 is
The stress mode signal / SM is activated when it is at a high level and inactivated when it is at a low level. In the normal mode, stress mode signal / SM is at a high level and differential amplifier circuit 5 is in an active state. Therefore, the other operations in the normal mode are described in the first embodiment.
Since it is the same as that described in Nos. 10 to 10, its explanation is omitted.

Next, in the stress mode, the stress mode signal / SM is at a low level, and differential amplification is performed regardless of the values of the reference voltage Vref generated by the reference voltage generating circuit 4 and the voltage Vs output by the level shifter circuit 3. The circuit 5 becomes inactive. The N-channel transistor 18 turns on in response to the stress mode signal / SM,
It outputs a low level signal. In response to this low level signal, P channel transistor 6 is always turned on, and external power supply voltage line 1 and internal power supply voltage line 2 are connected.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the present invention. The difference between the internal voltage down converter shown in FIG. 12 and the internal voltage down converter shown in FIG.
A CMOS transfer gate 16 and an inverter 96 for turning on / off the channel transistor 6
Is provided and the differential amplifier circuit 5 is always activated.

Next, the operation will be described. First, in the normal mode, the stress mode signal / SM is at a high level, the N-channel transistor 18 is off,
The CMOS transfer gate 16 is on. Therefore, the subsequent operation in the normal mode is similar to that described in the first to eleventh embodiments.

Next, in the stress mode, the stress mode signal / SM is at a low level, the N-channel transistor 18 is on and the CMOS transfer gate 16 is off. Therefore, the P-channel transistor 6 is always turned on regardless of the values of the reference voltage Vref generated by the reference voltage generation circuit 4 and the output voltage Vs of the level shifter circuit 3. Thereby, the external power supply voltage line 1 and the internal power supply voltage line can be connected.

[0085]

As described above, according to the present invention, one switching means can turn on / off between the external power supply voltage line and the internal power supply voltage line in the normal mode, and in the stress mode. The external power supply voltage line and the internal power supply voltage line can always be connected. Therefore, the area of the internal voltage down converting circuit can be made smaller than that of the conventional one, and thus the area of the semiconductor memory device can be made smaller.

Even in the stress mode, all of the switching means, level dropping means, reference voltage generating means and control means can be activated, and stress can be applied to all these means. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of an internal step-down circuit of a semiconductor memory device.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a tenth embodiment of the present invention.

FIG. 11 is a circuit diagram showing an eleventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a twelfth embodiment of the present invention.

FIG. 13 is a graph showing characteristics of an internal voltage down converter.

FIG. 14 is a graph showing a relationship between an external power supply voltage and an internal power supply voltage during a burn-in test.

FIG. 15 is a schematic block diagram showing an example of a semiconductor memory device having a stress mode function.

FIG. 16 is a circuit diagram showing a conventional internal step-down circuit having a function of equalizing an internal power supply voltage and an external power supply voltage.

[Explanation of symbols]

 1 External power supply voltage line 2 Internal power supply voltage line 3 Level shifter circuit 4 Reference voltage generation circuit 5 Differential amplifier circuit 6 P-channel transistor 7 Reference voltage line 41 Pull-up circuit

Claims (5)

[Claims] 1. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that drops an external power supply voltage to generate an internal power supply voltage and supplies the internal power supply voltage to the internal storage circuit. It has a stress mode test function of applying an external power supply voltage to the internal memory circuit, and turns on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level dropping means for dropping the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, and a reference generated by the reference voltage generating means. A control for comparing the voltage with the internal power supply voltage dropped by the level dropping means, and controlling ON / OFF of the switching means based on the comparison result. Includes means, said switching means, to the stress mode, a semiconductor memory device characterized in that it is always on state. 2. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that drops an external power supply voltage to generate an internal power supply voltage and supplies the internal power supply voltage to the internal storage circuit. It has a stress mode test function of applying an external power supply voltage to the internal memory circuit, and turns on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level dropping means for lowering the level of the internal power supply voltage, reference voltage generating means for generating a first reference voltage for keeping the internal power supply voltage constant, and the first reference voltage in the stress mode. Pull-up means for pulling up to generate a second reference voltage having a potential higher than the internal power supply voltage dropped by the level dropping means; and The first or second reference voltage is compared with the lowered internal power supply voltage, and if the first or second reference voltage is higher than the lowered internal power supply voltage, the switching means is turned on. State,
A semiconductor memory device comprising: control means for turning off the switching means when the first or second reference voltage is lower than the lowered internal power supply voltage. 3. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that drops an external power supply voltage to generate an internal power supply voltage and supplies the internal power supply voltage to the internal storage circuit. It has a stress mode test function of applying an external power supply voltage to the internal memory circuit, and turns on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, reference voltage generating means for generating a reference voltage for keeping the internal power supply voltage constant, during normal operation, converting the level of the internal power supply voltage to a lowered first voltage, and in the stress mode, Level dropping means for further dropping the first voltage to convert it into a second voltage having a potential lower than the reference voltage, and the generated reference voltage and the level When the reference voltage is higher than the first or second voltage, the switching means is turned on, and the reference voltage is compared with the first or second voltage converted by the voltage lowering means. A semiconductor memory device comprising control means for turning off the switching means when the voltage is lower than the first or second voltage. 4. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that drops an external power supply voltage to generate an internal power supply voltage and supplies the internal power supply voltage to the internal storage circuit. It has a stress mode test function of applying an external power supply voltage to the internal memory circuit, and turns on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level dropping means for dropping the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, reference voltage generated by the reference voltage generating means Is compared with the internal power supply voltage lowered by the level lowering means, and the switching means is turned on / off based on the comparison result.
It includes a first control means for turning off, and a second control means for keeping the switching means always on in response to an externally generated stress mode signal. In the stress mode, the level lowering means and the reference are provided. A semiconductor memory device characterized in that either one of the voltage generating means and the first control means is inactivated. 5. A semiconductor memory device comprising: an internal storage circuit; and an internal step-down circuit that drops an external power supply voltage to generate an internal power supply voltage and supplies the internal power supply voltage to the internal storage circuit. It has a stress mode test function of applying an external power supply voltage to the internal memory circuit, and turns on / off between an external power supply voltage line supplying the external power supply voltage and an internal power supply voltage line supplying the internal power supply voltage. Switching means, level dropping means for dropping the level of the internal power supply voltage, reference voltage generating means for generating a reference voltage for keeping the level of the internal power supply voltage constant, reference voltage generated by the reference voltage generating means Is compared with the internal power supply voltage lowered by the level lowering means, and the switching means is turned on / off based on the comparison result.
First control means for controlling off, and second control means for always turning on the switching means in response to an externally generated stress mode signal, the first control means and the second control means A semiconductor memory device including a means connected to a control means for switching off in response to the stress mode signal.