JPH0621368A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a semiconductor device being easy to manufacture, by a method wherein a bottom-side part between a lowwithstand-voltage element and a high-withstand-voltage element is made a P-N junction isolation structure and a lateral-side part between them is made a dielectric isolation structure. CONSTITUTION:A high-withstand-voltage element 41 and a low-withstandvoltage element 42 are isolated from each other electrically in the vertical direction by P-N junction isolation using a P insulating layer 11, while they are isolated electrically in the lateral direction by dielectric isolation using a groove 23, and the groove 23 is filled up with an insulating film 1 and a buried layer 2, so as to be made firm also mechanically. The high-withstand-voltage element 41 can make a large current flow through a region in which the P insulating layer 11 is not provided, while the low-withstand-voltage element 42 is isolated electrically from the high-withstand-voltage element 42 by the P insulating layer 11 and the groove 23. Accordingly, it is possible to manufacture an integrated circuit in which the high-withstand-voltage element 41 and the low- withstand-voltage element 42 are isolated from each other electrically, and reduction of power consumption and a speed increase can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are integrally formed, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A power device structure in which a control circuit composed of a low withstand voltage element and a high withstand voltage element having a current path from the front surface to the back surface of a substrate are monolithically integrated has a large current control because the current capacity of the high withstand voltage element can be increased. Is attracting attention as a device for mobile phones. In this device, insulation between a low breakdown voltage element and a high breakdown voltage element is important, and conventionally, element isolation techniques such as pn junction isolation or dielectric isolation have been well known.
However, while the dielectric isolation structure enables reliable electrical isolation, it has the problem that it is difficult to fabricate a high breakdown voltage element having a current path from the substrate front surface to the back surface. The structure has been conventionally used for a high breakdown voltage device with a relatively small current flowing in the lateral direction of the substrate. On the other hand, when the pn junction isolation structure is used, it is possible to fabricate a high-current high-breakdown-voltage element structure in which a current flows vertically in the substrate. The structure of the monolithic high breakdown voltage circuit element using the pn junction isolation will be described below, and then this defect will be described.

High breakdown voltage circuit and C using pn junction isolation structure
FIG. 4 shows a conventional structure in which a MOS low breakdown voltage circuit is integrally formed. Such a structure is described in, for example, Japanese Patent Publication No. 3-65025. First, the high voltage circuit will be described. Four
3 is an N ⁺ drain low resistance region, 44 is an N ⁻ drain high resistance region, 48 is a P body, 49 is an N ⁺ source electrode, 47
Is a gate electrode.

Next, the MOS low breakdown voltage circuit will be described. Fifty
Is an N ⁻ region where a CMOS transistor is formed, 51 is a P well, and 53a and 53b are N ⁺ source and N of an N channel type MOSFET formed inside the P well.
⁺ Drain, 52 is a gate electrode of the N-channel FET. Also, 55a and 55b are P-channel MO
The P ⁺ source and P ⁺ drain of the SFET, 54 is the gate electrode of this P-channel FET. On the other hand, 45 and 46 are a P region and a P ⁺ region for electrically isolating the CMOS low voltage circuit and the MOSFET high voltage circuit by the pn junction isolation structure. By using the pn junction separation structure as described above, a high breakdown voltage circuit element through which a current flows from the front surface to the back surface of the substrate and a low breakdown voltage circuit element for performing this control can be integrated and formed on the same substrate.

[0005]

In the fabrication of the structure shown in FIG. 4, first, boron is diffused in the N ⁺ substrate 43 to diffuse the P region 45.
And then epitaxially grow silicon to form N ^−.
Forming regions 44 and 50, followed by 44 and 5
The P ⁺ region 46 connected to the P region 45 is formed by deeply diffusing boron in the direction 43 from the surface of 0. At this time, when the thickness of the N ⁻ regions 44 and 50 is about 10 μm, it is 5 at a high temperature of 1100 ° C.
A structure in which the P ⁺ region 46 and the P region 45 are connected to each other can be obtained by performing diffusion for about time. However, if the thickness of the N ⁻ regions 44 and 50 is 30 μm, a long diffusion time of 40 hours or more is required. There was a problem that was said.
Moreover, such deep diffusion presents a problem of P ⁺ region 46 extending laterally of the substrate within N ⁻ regions 44 and 50, in addition to the problem of the length of diffusion time. As a result, the areas of the N ⁻ regions 44 and 50 in which the high breakdown voltage element 41 and the low breakdown voltage element 42 are formed are reduced,
This hinders the improvement of the integration density of the semiconductor device. further,
There was also the problem that the thickness of 44 and 50 was reduced because the P region 45 diffused into the substrate of 44 and 50 due to the long diffusion time. Therefore, in order to finally obtain the desired depth of N ⁻ regions 44 and 50, the N before diffusion must be
^- it is kept considerably thicker produced the thickness of the region is required. This, in addition to significantly increasing the epitaxial growth time for making 44 and 50 substrates,
There has been a serious dilemma of increasing the diffusion time connecting 46 to 45.

[0006]

In order to solve the above problems of the prior art, the present invention provides a low breakdown voltage element in a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are simultaneously formed on a semiconductor substrate. A semiconductor device having a pn junction isolation structure on the bottom surface between the high voltage element and the dielectric breakdown structure on the side surface side is obtained.

As a method of manufacturing the structure of the present invention, an insulating layer region made of an impurity layer of a type different from that of the substrate is formed in a partial region of the semiconductor substrate, and then the same type of substrate as that of the substrate is formed on the substrate. After epitaxially growing a silicon layer containing impurities, by providing a groove obtained by etching the epitaxial silicon layer until it reaches the insulating layer,
A method of manufacturing on a conductive substrate, characterized in that a silicon region for forming a low breakdown voltage element and a silicon region for forming a high breakdown voltage element are separated, and an insulating layer made of an impurity layer of a type different from that of the substrate is provided. One semiconductor substrate and the other semiconductor substrate of the same type as the semiconductor substrate, in which an impurity layer region of a different type from the previous insulating layer is provided in at least a part of the island-shaped silicon region formed by the etching groove And (a) are bonded to each other, and then the impurities provided on the other semiconductor substrate are diffused until they penetrate the insulating layer.

In the structure of the semiconductor device of the present invention, the low breakdown voltage element and the high breakdown voltage element are electrically separated by two methods. That is, the pn junction isolation separates the low breakdown voltage element and the high breakdown voltage element in the vertical direction, and the dielectric isolation splits the low breakdown voltage element and the high breakdown voltage element in the horizontal direction. By providing pn junction isolation in the vertical direction and electrically isolating the element, it is possible to realize the formation of a high breakdown voltage element for a large current in which a current flows from the front surface of the substrate to the back surface. Further, the dielectric isolation provided for the electrical isolation in the lateral direction does not require the deep diffusion step required in the conventional example because it can be manufactured at a low temperature. As a result, the semiconductor device can be easily manufactured, and since the vertical and lateral diffusion of the P and P ⁺ regions is eliminated, the device can be highly densified.

[0009]

EXAMPLES The structure and manufacturing method of the present invention will be described below with reference to examples. FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, the components having the same numbers as the components in FIG. 4 represent the same components, and the description thereof will be omitted here.

The high breakdown voltage element 41 and the low breakdown voltage element 42 shown in the embodiment of FIG. 1 are electrically separated in the vertical direction by the pn junction separation using the P insulating layer 11. In addition, electrical isolation in the lateral direction is performed by dielectric isolation using the groove 23. Since the inside of the groove 23 is filled with an insulating film 1 such as an oxide film and a buried layer 2 such as polysilicon, it is mechanically strong. The high breakdown voltage element 41 can pass a large current through a region where the P insulating layer 11 is not provided. In addition, the low breakdown voltage element 4
2 is electrically isolated from the high breakdown voltage element 42 by the P insulating layer 11 (pn junction isolation) and the groove 23 (dielectric isolation).

FIG. 2 shows an embodiment of a method for manufacturing the embodiment of FIG. First, the mark 21 for alignment is provided on the back surface of the N ⁺ silicon substrate 43 which serves as the drain of the high breakdown voltage element. In the example of FIG. 2, this alignment mark 21 shows an example in which a V groove is formed on the silicon substrate 43 with an alkali etching solution. In addition to this, the alignment mark can be formed by diffusion of impurities or the like. Then, the P insulating layer 11 is formed on the surface opposite to the main surface on which the alignment marks 21 are formed while aligning the marks 21 (FIG. 2A). At this time, a P insulating layer is not provided in a region where a high breakdown voltage element will be formed in the future by covering this region with a protective film. A silicon film containing impurities of the same type as the silicon substrate 43 is epitaxially grown on the substrate thus manufactured. After the alignment mark 21 is aligned, the epitaxially grown silicon film 2
2 is deeply etched until the bottom surface of the groove 23 becomes a P insulating film (FIG. 2B). For this etching, KO
An anisotropic etching solution such as H, EDP or hydrazine can be used. In addition, reactive ion etching (RI
The groove 23 can be formed by an anisotropic dry etching device such as E).
Can be formed. An oxide film on the side surface of the groove 23,
After providing the insulating film 1 with a nitride film or the like, polysilicon is deposited to fill the groove. Finally, the polysilicon film is polished so that the surface of the epitaxial silicon film 22 is exposed (FIG. 2C). After that, the structure of FIG. 1 can be manufactured by using a normal MOS or bipolar process.

Another embodiment of manufacturing the structure of the present invention is shown in FIG. This manufacturing method uses two silicon substrates. First, the V-groove filled with the insulating film 1 and the polysilicon 2 is formed in the one silicon substrate 31 as described above (FIG. 3A). Then, the diffusion layer 32 is formed on the main surface provided with the V groove by ion implantation or diffusion (FIG. 3B). The diffusion layer 32 contains the same type of impurities as the silicon substrate 31. A diffusion layer 33 containing impurities different from 43 is formed on one main surface of the other silicon substrate 43. The silicon substrates 43 and 31 contain impurities of the same type. The two silicon substrates 43 and 31 are adhered so that the insulating layer 33 and the surface on which the V groove is formed face each other (FIG. 3C). A direct silicon bonding technique can be used for bonding the silicon substrate. The diffusion layer 32 is diffused into the insulating layer 33 by placing the silicon substrate thus bonded together in an electric furnace. This diffusion needs to be performed until the bottom surface of the diffusion layer 32 reaches the silicon substrate 43. As a result, the diffusion layer 32 becomes the drain penetration layer 34 as shown in FIG. 3D, and the electric current can flow between the two silicon substrates. After that, the silicon substrate 31 is polished so that the bottom surface of the V groove appears (FIG. 3D). In this way, it is possible to electrically separate the region 44 where the high breakdown voltage element is formed and the region where the low breakdown voltage element 50 is formed.

In the embodiment shown in FIG. 3, a high temperature treatment is required to diffuse the diffusion layer 32 into the insulating layer 33.
However, since the depth of this diffusion is much shallower than that of the conventional example, the required diffusion time is short.

On the other hand, compared with the invention of FIG. 2, the insulating layer 33
Is unnecessary, and the alignment mark on the back surface is not included, so that the manufacturing process is simplified.

In the above example of the present invention, the silicon substrate and the substrate on which the circuit is formed are described as N-type and the insulating layer is P-type. However, the present invention is not limited to this. That is, the present invention is effective even when the insulating layer is N type and the silicon substrate and the circuit forming substrate are P type. Also,
It is not necessary to embed the V-groove as shown in this embodiment, and a structure having a hollow inside is also included in the present invention.

[0016]

According to the present invention, it becomes possible to manufacture an integrated circuit in which a high breakdown voltage element and a low breakdown voltage element are electrically separated. Since the high breakdown voltage element allows a current to flow perpendicularly to the substrate, it is necessary to control a large current. Further, since the low breakdown voltage element and the high breakdown voltage element are separated in the lateral direction by the dielectric, the parasitic capacitance is smaller than that of the conventional pn junction separation, and excellent electrical characteristics are exhibited. As a result, reduction of power consumption and speeding up were realized. Further, unlike the conventional example, since a long diffusion process is not required, lateral diffusion of the separation layer can be suppressed, so that the element size can be reduced.

As a result, it has been possible to improve the density of the integrated circuit. On the other hand, in the manufacturing method of the present invention, the long-time high temperature process of the conventional example can be eliminated. This helped to significantly simplify the process. In particular, it is a great effect of the present invention that the device design is remarkably simple because the large fluctuation of the diffusion profile, which was a problem in the conventional example, can be suppressed to a low level.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of manufacturing the structure of the present invention.

FIG. 3 is a diagram showing another embodiment for manufacturing the structure of the present invention.

FIG. 4 is a diagram showing a structure of a conventional technique.

[Explanation of symbols]

1 Insulating Film 2 Buried Layer 11 P Insulating Layer 21 Alignment Mark 22 N ^- Silicon Circuit Region 23 Groove 31 N ^- Substrate 32 Diffusion Layer 33 Insulating Layer 34 Drain Through Layer 41 High Voltage Element 42 Low Voltage Element 43 N ⁺ Drain Low Resistance Region 44,50 N ^- Drain High Resistance Region 45 P Insulating Layer 46 P ⁺ Insulating Layer 47, 52, 54 Gate 48 P Body 49 N ⁺ Source Electrode 51 P Well 53a, 55a Source 53b, 55b Drain

Claims (3)

[Claims] 1. In a semiconductor device in which a high breakdown voltage element and a low breakdown voltage element are simultaneously formed on a semiconductor substrate, a bottom surface side between the low breakdown voltage element and the high breakdown voltage element has a pn junction isolation structure, and a side surface side is a dielectric. A semiconductor device having a body separation structure. 2. An insulating layer region made of an impurity layer of a type different from that of the substrate is formed in a partial region of the semiconductor substrate, and subsequently, a silicon layer containing impurities of the same type as the substrate is epitaxially grown on the substrate. A method of manufacturing a semiconductor device, wherein an etching groove reaching the insulating layer is provided in an epitaxial silicon layer to separate a silicon region for forming a low breakdown voltage element from a silicon region for forming a high breakdown voltage element. 3. One semiconductor substrate provided with an insulating layer made of an impurity layer of a type different from that of the substrate, and an impurity of a type different from that of the previous insulating layer in at least part of an island-shaped silicon region formed by an etching groove. The semiconductor substrate provided with the layer region and the other semiconductor substrate of the same type are bonded to each other, and then the impurities provided in the other semiconductor substrate are diffused to penetrate through the insulating layer. Manufacturing method of semiconductor device.