JPH06204257A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a self alignment GaAs MESFET, which has an easily reducible gate length and has a gate electrode having a sufficiently low gate resistance. CONSTITUTION:An operating layer of a MESFET is first formed by an ion implantation, a gate electrode 7 consisting of a silicon dioxide SiO2 film or two layers of a first high-melting point metal alloy film and a silicon dioxide SiO2 film is formed, an ion implantation is performed using this electrode 7 as a mask to form high-concentration regions 9 in a self alignment and an activation annealing of impurities is performed using a second high-melting point metal alloy film 10 as a protective film. The film 10 is removed and after a resist is applied, the resist 11 is etched until the head of the electrode 7 is exposed and the silicon dioxide SiO2 film is selectively removed with a hydrofluoric acid or the like. After that, a metal film having a low resistivity, such as a Ti/Au film, is deposited and is lifted off, whereby a gate electrode, which is constituted of the metal film having a low resistivity or the metal film having a low resistivity and the first high-melting point metal alloy film, is formed in a self alignment and a source electrode consisting of an AuGe/Ni alloy film and a drain electrode are formed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to compound semiconductors, especially Ga
The present invention relates to a method of manufacturing a Schottky gate field effect transistor (hereinafter referred to as MESFET) using As.

[0002]

2. Description of the Related Art Currently, a high frequency analog integrated circuit MMIC (Monolithic Microwave) using a GaAs MESFET.
IC) is being actively developed, but in order to realize an integrated circuit that operates at a higher frequency and consumes less power, the cutoff frequency ft and the maximum oscillation frequency fmax of the MESFET forming the integrated circuit are High is essential. Therefore, conventionally, the cutoff frequency ft and the maximum oscillation frequency fma
To increase x, the gate length Lg of the MESFET is shortened to reduce the gate-source capacitance Cgs, and
Mutual conductance g
A method of increasing m has been adopted. In order to reduce the noise figure NF, which is important as an analog integrated circuit,
Another important issue was how to reduce the gate resistance Rg and the source resistance Rs. On the other hand, conventionally GaAsME
Recess gate FET has been adopted as a manufacturing technology of SFET. However, since recess etching for determining the electrical characteristics of MESFET is performed by the wet etching method, there are major problems in precise control of etching amount, uniformity in wafer surface and reproducibility. there were. Therefore, recently, a self-aligned structure FET using a refractory metal alloy film, which has been conventionally developed for high-speed digital ICs and has good in-plane uniformity of electric characteristics as a gate electrode, is intended to be applied to a high-frequency analog integrated circuit. There are many attempts.

FIG. 5 is a self-aligned structure Ga using a conventional refractory metal alloy film as a gate electrode.
It is sectional drawing in each main process for demonstrating the manufacturing method of AsMESFET.

In the figure, first, the semi-insulating substrate 1 is
Strike 2 as a mask²⁹Si⁺ Acceleration voltage of 30 keV,
Dose amount 4 × 10¹²cm^-2Selective ion implantation under conditions of M
The n-type operating layer 3 of the ESFET is formed (Fig. 5a). next
The surface of the semi-insulating substrate 1 has a first high melting point such as WSi.
The metal alloy film 4 is formed to a thickness of about 400 nm by the sputtering method.
Deposition (Fig. 5b). Next, mass of aluminum (Al) 6
By reactive ion etching (RIE)
The refractory metal alloy film 4 of 1 is etched to form the gate electrode 7.
Formed (Fig. 5c). Next, the gate electrode 7 and the resist
8 as a mask ²⁸Si⁺ Acceleration voltage 80keV, dose
Amount 2 × 10¹³cm^-2Ion implantation under the conditions of
The n-type high concentration layer 9 is formed by self-alignment (FIG. 5).
d). Next, for example, Si on the surface of the semi-insulating substrate 1.₃N_FourEtc.
The insulating film 17 having a thickness of about 100 nm is formed by plasma CVD or the like.
It is applied with a thickness and N is used as a protective film.₂ 800 in the atmosphere
Heat treatment (activation annealing) for about 15 minutes at a temperature around ℃
Then, the implanted impurities are activated (FIG. 5e). Next
In addition, use a buffered hydrofluoric acid for the specified part of the insulating film 17.
Open more and lift AuGe / Ni alloy by lift-off method
Apply a heat treatment (sinter) with a thickness of about 200 nm.
To form the source electrode 15 and the drain electrode 16
A GaAs MESFET is manufactured (Fig. 5f).

[0005]

In a conventional method of manufacturing a GaAs MESFET used for a high frequency analog integrated circuit MMIC, a self-alignment (self-alignment) method which is advantageous in terms of controllability and uniformity of electric characteristics in place of the recess gate structure FET is used. The adoption of matching structure FETs has been considered.
However, the specific resistance of the refractory metal alloy film used for such a self-alignment structure is WS.
i is about 50 to 500 μΩ · cm, which is 20 to 200 times the specific resistance of conventional aluminum of 2.5 μΩ · cm,
As the gate length becomes shorter, the cross-sectional area of the gate electrode decreases, and the increase in the gate resistance Rg becomes non-negligible, which is a major factor limiting the high frequency characteristics of the FET.

For this reason, there are many attempts to reduce the gate resistance Rg by depositing a metal having a low specific resistance such as Au on the gate electrode after the heat treatment (annealing). It was difficult to deposit Au or the like on the gate electrode made of the high melting point metal alloy film.

The present invention is, in principle, a self-alignment structure using a refractory metal alloy or a metal film of low specific resistance capable of forming a gate electrode having a sufficiently low gate resistance Rg no matter how small the gate length is. GaAs MESF
It is an object to provide a method for manufacturing ET.

[0008]

In order to achieve the above-mentioned object, the present invention first forms an operating layer of a MESFET by ion implantation to form silicon dioxide SiO ₂ or a first refractory metal alloy and silicon dioxide SiO ₂ . A high-concentration region is formed by self-alignment (self-alignment) by forming a gate electrode composed of two layers and using it as a mask, and activating annealing of impurities using the second refractory metal alloy film as a protective film. After that, the second refractory metal alloy film is removed, the resist is applied and the resist is etched until the head of the gate electrode is exposed, and silicon dioxide SiO ₂ is selectively removed by hydrofluoric acid or the like. , Then Ti / A
A metal film having a low specific resistance by self-alignment (self-alignment) by depositing and lifting off a metal film having a low specific resistance such as u, or a gate composed of a metal film having a low specific resistance and a first refractory metal. Forming electrodes, MESFET
Is manufactured.

[0009]

In this way, the MESF is formed by ion implantation.
Forming an operating layer of ET, silicon dioxide SiO ₂ or first
Forming a high-concentration region by self-alignment by forming a gate electrode composed of two layers of the high-melting-point metal alloy and silicon dioxide SiO ₂ as a mask, and forming a second high-melting-point metal alloy. After the impurity activation annealing is performed using the film as a protective film, the second refractory metal alloy film is removed, the resist is applied and the resist is etched until the head of the gate electrode is exposed, and hydrofluoric acid or the like is used. Silicon dioxide SiO ₂ is selectively removed by
A metal film having a low specific resistance, such as i / Au, is deposited and lifted off to form a metal film having a low specific resistance by self-alignment (self-alignment) or a metal film having a low specific resistance and a first refractory metal. A MESFET having a gate electrode having a sufficiently low electric resistance and a high mutual conductance gm can be easily manufactured with good reproducibility. In addition, conventional protective films for activation annealing such as SiO ₂ , Si ₃ N ₄ , and SiO are used.
By using a refractory metal alloy film instead of a protective film such as _X N _Y, it is possible to effectively suppress outward diffusion of Ga atoms and As atoms from the GaAs substrate to the protective film at a high temperature. It is possible to reduce collapse of stoichiometry, fluctuation of activation rate of introduced impurities, and occurrence of crystal defects. As a result, the ME having excellent high-frequency characteristics with high cutoff frequency ft and maximum oscillation frequency fmax.
SFET can be manufactured and GaA using this MESFET
The sMMIC has excellent high frequency characteristics and can operate with lower power consumption.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view in each main step for explaining a method of manufacturing a GaAs MESFET, for explaining one embodiment of the first invention.

In the figure, first, the semi-insulating substrate 1 is
Strike 2 as a mask²⁹Si⁺ Acceleration voltage of 30 keV,
Dose amount 4 × 10¹²cm^-2Selective ion implantation under conditions of M
The n-type operating layer 3 of the ESFET is formed (FIG. 1a). next
The surface of the semi-insulating substrate 1 has a first high melting point such as WSi.
The metal alloy film 4 is formed to a thickness of about 100 nm by the sputtering method.
Deposited by plasma CVD followed by silicon dioxide Si
O₂ The film 5 is deposited to a thickness of about 500 nm (Fig. 1
b). Next, using aluminum (Al) 6 as a mask, reaction
Refractory metal alloy by reactive ion etching (RIE)
Membrane 4 and silicon dioxide SiO₂ The film 5 is etched and the
The electrode 7 is formed (FIG. 1c). Next, the gate electrode 7 and
And resist 8 as a mask²⁸Si⁺ Acceleration voltage 80 ke
V, dose amount 2 × 10¹³cm^-2Ion implantation under the conditions
Form n-type high concentration layer 9 by ruf alignment (self-alignment)
(Fig. 1d). Next, for example, W on the surface of the semi-insulating substrate 1.
The second refractory metal alloy film 10 such as Si is formed by the sputtering method.
Applied as a protective film with a thickness of about 100 nm.
N₂ Heat treatment for about 15 minutes at a temperature of around 800 ℃ in the atmosphere
(Activation anneal) to activate the implanted impurities.
Do (FIG. 1e). Next, the second refractory metal alloy film 10 is formed.
CF_Four+ O₂Gate by plasma etching using
The electrode 11 is selectively removed and the resist 11 is removed by 150
The resist is flattened by applying a thickness of about 0 nm.
At this time, the resist 11 having a low viscosity is more suitable for flattening,
It is also effective to perform a heat treatment (post bake) after coating.
(Fig. 1f). Then O₂ Reactive ion energy due to plasma
The head of the gate electrode 7 is exposed by etching (RIE).
The resist 11 is etched until it reaches the temperature. At this time
The final film thickness of GIST 11 is measured using an optical method.
It is also possible to monitor using a fixed device (Fig. 2
g). Next, silicon dioxide Si on the exposed upper part of the gate electrode 7
O ₂ The film 5 is removed by using hydrofluoric acid, and then the Ti film 1 is removed.
2 and Au film 13 of 50 nm and 400 nm, respectively.
Normal vapor deposition is performed to a thickness (FIG. 2h). Next, Ti film
12 and the Au film 13 are lifted off, and the first
Self-alignment on the refractory metal alloy film 4
In this case, a gate composed of a Ti film 12 and an Au film 13
Forming an electrode 14 (FIG. 2i). Then remove the resist
Due to the lift-off used, AuGe / Ni alloy was
Source with a thickness of about m and a heat treatment (sinter)
The electrode 15 and the drain electrode 16 are formed to form GaAsM
The ESFET is manufactured (Fig. 2j).

FIG. 3 is a sectional view for explaining an embodiment of the second invention and is a cross-sectional view in each main step for explaining a method of manufacturing a GaAs MESFET.

In the figure, first, ²⁹ Si ⁺ is applied to the semi-insulating substrate 1 using the resist 2 as a mask, and the acceleration voltage is 30 keV.
Selective ion implantation under the condition of a dose amount of 4 × 10 ¹² cm ^-2
The n-type operating layer 3 of the ESFET is formed (Fig. 3a). Then, a silicon dioxide SiO ₂ film 5 is deposited on the surface of the semi-insulating substrate 1 by plasma CVD to a thickness of about 600 nm (FIG. 3b). Next, silicon dioxide S is formed by reactive ion etching (RIE) using aluminum (Al) 6 as a mask.
The iO ₂ film 5 is etched to form a gate electrode 7 (FIG. 3c). Next, using the gate electrode 7 and the resist 8 as a mask, ²⁸ Si ^{+ is used} for the acceleration voltage of 80 keV and the dose amount of 2 × 10 ^13.
Ions are implanted under the condition of cm ⁻² to form the n-type high concentration layer 9 by self-alignment (FIG. 3d). Next, a second refractory metal alloy film 10 such as WSi is deposited on the surface of the semi-insulating substrate 1 to a thickness of about 100 nm by a sputtering method, and this is used as a protective film in an N ₂ atmosphere at about 800 ° C. Heat treatment (activation annealing) is performed at a temperature of about 15 minutes to activate the implanted impurities (FIG. 3e). Next, the second refractory metal alloy film 10 is selectively removed with respect to the gate electrode 7 by plasma etching or the like using CF ₄ + O ₂ , and a resist 11 is applied to a thickness of about 1500 nm to flatten the resist. To convert. At this time, the resist 11 having a low viscosity is more suitable for flattening, and it is also effective to perform a heat treatment (post-baking) after coating (FIG. 3f). Next, the resist 11 is etched by reactive ion etching (RIE) using O ₂ plasma until the head of the gate electrode 7 is exposed. At this time, the final film thickness of the resist 11 can be monitored by using a film thickness measuring device using an optical method (FIG. 4g). Next, the exposed silicon dioxide SiO ₂ film 5 of the gate electrode 7 is removed by using hydrofluoric acid, and then the Ti film 12 and the Au film 13 are each removed to 5
Normal deposition is performed to a thickness of 0 nm and 500 nm (FIG. 4h). Next, the Ti film 12 and the Au film 13 are lifted off, and Ti is self-aligned.
Gate electrode 14 composed of film 12 and Au film 13
Are formed (FIG. 4i). After that, AuGe / Ni alloy is vapor-deposited to a thickness of about 200 nm by lift-off using a resist, and heat treatment (sintering) is performed to form a source electrode 15 and a drain electrode 16 to form a GaAs MESFET.
Are produced (FIG. 4j).

This embodiment is merely an example,
It goes without saying that improvements and changes can be made without departing from the constitution of the present invention.

[0015]

As described above, according to the present invention, it is possible to easily form a gate electrode having a sufficiently low electric resistance even when the gate length Lg is extremely short, and also to form the n-type high concentration region. MESFE with high mutual conductance gm because it can be formed by cell alignment (self-alignment)
T can be manufactured uniformly with good reproducibility. In addition, conventional protective films for activation annealing such as SiO ₂ , Si ₃ N ₄ , S
By using a refractory metal alloy film instead of a protective film such as iO _x N _y , the G from the GaAs substrate to the protective film at high temperature can be reduced.
Outward diffusion of a atoms and As atoms can be effectively suppressed, and collapse of stoichiometry of the GaAs substrate, fluctuation of activation rate of introduced impurities, and occurrence of crystal defects can be reduced. As a result, the gate length Lg of the MESFET can be shortened, and at the same time, the FET can be increased in gm, and at the same time, a GaAs MESFET having an extremely small gate-source capacitance Cgs and a sufficiently low gate resistance Rg can be easily manufactured. Therefore, the GaAs MMIC using the MESFET according to the present invention has excellent high frequency characteristics and can operate with lower power consumption.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in each main process for explaining a method of manufacturing a GaAs MESFET for explaining an embodiment of the first invention.

FIG. 2 is a cross-sectional view in each main process for explaining the method of manufacturing the GaAs MESFET, for explaining one embodiment of the first invention.

FIG. 3 is a cross-sectional view in each main process for explaining a method of manufacturing a GaAs MESFET for explaining an embodiment of the second invention.

FIG. 4 is a cross-sectional view in each main step for explaining a method of manufacturing a GaAs MESFET, for explaining one embodiment of the second invention.

FIG. 5 is a diagram for explaining the prior art, GaAsM
Sectional drawing in each main process for demonstrating the manufacturing method of ESFET.

[Explanation of symbols]

1 semi-insulating substrate 2 resist 3 n-type operating layer 4 first refractory metal alloy film 5 SiO ₂ film 6 aluminum 7 gate electrode 8 resist 9 n-type high concentration layer 10 second refractory metal alloy film 11 resist 12 Ti film 13 Au film 14 Gate electrode 15 Source electrode 16 Drain electrode 17 Insulating film

Claims (4)

[Claims] 1. A surface of a semi-insulating substrate is n-implanted by ion implantation.
Forming a shaped operating layer, depositing a first refractory metal alloy film that maintains the Schottky junction even after heat treatment on the surface of the semi-insulating substrate by sputtering or the like, and said first refractory metal anisotropic a step, and said first refractory metal alloy film by reactive ion etching (RIE) of aluminum or the like as a mask the silicon dioxide SiO ₂ to deposit an insulating film on the alloy film made of silicon dioxide SiO ₂ Etching to form a gate electrode, a step of forming an n-type high concentration region by self-alignment by performing ion implantation using the gate electrode as a mask, and a second refractory metal as a protective film for annealing. A step of depositing an alloy film by sputtering or the like and performing a heat treatment to activate the implanted ions, a step of removing the second refractory metal alloy film, and a step of applying a resist to flatten the surface. And a step of etching the resist until the head of the gate electrode is exposed to selectively remove the silicon dioxide SiO ₂ using hydrofluoric acid or the like, and a specific resistance such as Ti / Au. Forming a metal film having a low specific resistance on the first refractory metal alloy film by self-alignment by vapor-depositing and lifting off a metal film having a low resistivity. Manufacturing method. 2. The first refractory metal alloy film and the second refractory metal alloy film are made of tungsten (W), molybdenum (Mo), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tungsten. 2. The method of manufacturing a field effect transistor according to claim 1, comprising at least one of a refractory metal film and a refractory metal alloy film such as nitride (WN) and tungsten aluminum (WAl). 3. A semi-insulating substrate surface is ion-implanted by n
Forming a shape operation layer, wherein an insulating film on a semi-insulating substrate surface made of silicon dioxide SiO ₂ and a step of depositing, the silicon dioxide SiO ₂ by reactive ion etching (RIE) of aluminum or the like as a mask A step of forming a temporary gate electrode by anisotropic etching, a step of forming an n-type high concentration region by self-alignment by performing ion implantation using the temporary gate electrode as a mask, and a step of forming a protective film for annealing. A step of activating the implanted ions by depositing a second refractory metal alloy film by sputtering or the like and performing a heat treatment; a step of removing the second refractory metal alloy film; And etching the resist until the head of the gate electrode is exposed, and then using the hydrofluoric acid or the like to remove the silicon dioxide S
a step of selectively removing iO ₂ and Al or Ti / Pt /
And a step of forming a gate electrode by self-alignment by vapor-depositing a metal film having a low specific resistance such as Au and lifting it off. 4. The second refractory metal alloy film comprises tungsten (W), molybdenum (Mo), tungsten silicide (WSi), tungsten silicon nitride (WS).
4. The method for manufacturing a field effect transistor according to claim 3, comprising at least one of a refractory metal film or a refractory metal alloy film such as iN), tungsten nitride (WN), and tungsten aluminum (WAl).