JPH06202894A - Shared memory control circuit - Google Patents

Abstract

PURPOSE:To speed up the processing on the shared memory circuit and to reduce the occupancy time of the shared memory circuit by providing plural control sections controlling device to be controlled according to the instructions of a high order device. CONSTITUTION:The circuit is provided with plural control sections 10 and 20 controlling device 2 to be controlled according to the instructions of a high order device 1. The control sections 10 and 20 include processor circuits 11 and 21, shared memory circuits 12 and 22, shared memory circuits 13 and 23. When it receives an asynchronous write instruction from the processor circuit 11, it instructs the data writing in the shared memory circuit 13 and instructs the data storage in the shared memory control circuit 22. When it receives a synchronous writing instruction from the processor 11, it instructs the data writing in the shared memory circuit 13 and instructs the shared memory control circuit 22 to write the data and the data already stored in the shared memory circuit 23. When the writing only in an own system shared memory circuit is completed by the asynchronous writing instruction, the next processing can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory circuit accessible by a plurality of processors, and more particularly to a shared memory control circuit.

[0002]

2. Description of the Related Art Conventionally, in an information processing system in which a controlled device is a magnetic disk device or the like, a plurality of control units may be provided for the same controlled device. That is, in this way, the processing capability of the information processing system is increased and the reliability of the entire information processing system including the controlled device is improved.

It is necessary for the plurality of control units to share control data in order to control the same controlled device, and the shared memory circuit provided in each control unit holds common control data. There is.

FIG. 4 is an explanatory diagram showing the operation when each control unit of the # 1 system and the # 2 system writes data in the respective shared memory circuits. In the figure, when the # 1 system control unit operates to generate an instruction to write data in the shared memory circuit (41), the # 1 system control unit transfers the data to the # 2 system control unit (42), Data writing is instructed to each shared memory circuit (43). And the # 1 system controller is # 1
Write data to the shared memory circuit of the system itself (4
4, 45), and waits for a write end notification from the # 2 system control unit (46).

When the # 2 system controller receives the data and the write instruction from the # 1 system controller (48, 49), it writes the data to the shared memory circuit of the # 2 system itself (50, 5).
1), a write end notification is sent to the # 1 system control unit.

After confirming the end of the write operation in the # 2 system control unit, the # 1 system control unit executes the next microinstruction (46, 47).

The shared memory control circuit provided in the control section of each system as described above controls the write address and write data of the shared memory circuit and controls the write operation. The address and the data are written by the processor circuit when writing from the own system, and the data transferred from the shared memory control circuit of the other system is written when writing from another system. That is, the conventional writing process is the synchronous writing process as described above.

[0008]

In the above-mentioned conventional shared memory control circuit, since writing is performed to both shared memory circuits when a write operation occurs, the write completion must be reported from the own system and other systems every time. The processor that has performed the write operation cannot start the next processing. Moreover, there is a drawback that the firmware processing becomes slower.

[0009]

A shared memory control circuit according to the present invention has a plurality of control units for controlling a controlled device according to an instruction from a host device, and the control units share a processor circuit and a shared memory control circuit. Each including a memory circuit,
When the asynchronous write instruction is received from the first processor circuit, the first shared memory circuit is instructed to write the data, and the second shared memory control circuit is instructed to store the data. When receiving the synchronous write instruction, instructing the first shared memory circuit to write the data, and writing the data and the already stored data to the second shared memory circuit, the second shared memory control It is configured to instruct the circuit.

In the shared memory control circuit of the present invention, the second shared memory control circuit for storing the data transferred by the first shared memory control circuit has a FIFO circuit, and the data is held in the FIFO circuit. It is configured to do.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the shared memory control circuit 12 according to the present invention is shown.
And 22 are included in the # 1 control unit 10 and the # 2 control unit 20, respectively.

The # 1 control unit 10 and the # 2 control unit 20 control the controlled device 2 according to an instruction from the host device 1. That is, when the controlled device 2 is a magnetic disk device, it controls the processing operation of writing and reading the information sent from the higher-level device 1 to the controlled device 2.

The # 1 control unit 10 includes a processor circuit 11 for controlling the above processing operation, a shared memory circuit 13 including a memory IC, a micro instruction from the processor circuit 11 or a shared memory control circuit of the # 2 control unit 20. The shared memory control circuit 12 controls the shared memory circuit 13 in accordance with an instruction from 22. Similarly, the # 2 control unit 20 includes a processor circuit 21, a shared memory circuit 23 including a memory IC, and a processor circuit 2.
The shared memory control circuit 22 controls the shared memory circuit 23 in response to a micro instruction from 1 or an instruction from the shared memory control circuit 12 of the # 1 control unit 10.

FIG. 2 is an explanatory diagram showing the configuration of the shared memory control circuit 12. In the figure, the shared memory control circuit 12
Of the sequence control circuit 12a and the address F
It has an IFO circuit 12b and a data FIFO circuit 12c.

The sequence control circuit 12a sends a shared memory circuit write signal when a synchronizing signal is input, and at the same time, sends a write address from the address FIFO circuit 12b and write data from the data FIFO circuit 12c to the shared memory circuit 13 to perform a write operation. To execute. In addition, # 2
The data transferred from the control unit 20 is written in the shared memory control circuit 12.

Further, the sequence control circuit 12a sends an end signal when the asynchronous signal is inputted, and the address FIF
The contents of the O circuit 12b and the data FIFO circuit 12c are retained as they are.

The shared memory control circuit 22 is also constructed in the same manner as above.

FIG. 3 is an explanatory diagram showing an asynchronous write operation in the shared memory control circuit. In the figure, when the micro instruction from the processor circuit 1 is decoded and the micro instruction is an asynchronous write instruction, the shared memory control circuit 12 instructs the shared memory circuit 13 of the # 1 system to write, and the shared memory control circuit 12 of the # 2 system. The write data is transferred to the shared memory control circuit 22 (31, 32, 33).

The shared memory control circuit 22 stores the write data in the internal register (FIFO circuit) (37).

Further, the shared memory control circuit 12 writes the data in the shared memory circuit 13, waits for the end thereof, and then performs the next processing (34, 35, 36). That is, the processor circuit 11 of the # 1 system can execute the following processing without writing to the shared memory circuit 23 of the # 2 system.

On the other hand, if the microinstruction from the processor circuit 11 is decoded and this microinstruction is synchronous writing, the # 1 system shared memory control circuit 12 writes this data to the shared memory circuit 13 and # 2. The system shared memory control circuit 22 is instructed to write this data, and at the same time, the data stored in the internal register of the shared memory control circuit 22 is instructed to be written to the shared memory circuit 23.

The shared memory control circuit 22 writes the main data and the stored data, and notifies the # 1 system shared memory control circuit 12 of the completion of the writing when the writing to the shared memory circuit 23 is completed. The shared memory control circuit 12 confirms the end of writing from the # 2 system and the end of writing in the # 1 system, and reports the end of writing to the processor circuit 11.

The shared memory control circuit 22 of the # 2 controller 20 operates in the same manner as above.

As described above, the micro-instruction from each processor circuit determines the synchronous / asynchronous write instruction, and if it is asynchronous write, the writing to the processor circuit ends when the data writing to the shared memory circuit of its own system ends. Since the report is made, the processor circuit can wait for the completion report and perform the next firmware process.

[0026]

As described above, according to the present invention, the following processing can be performed if the writing of only the own system shared memory circuit is completed by the asynchronous writing instruction. Therefore, there is an effect that the processing related to the shared memory circuit can be speeded up and the occupied time of the shared memory circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration of a shared memory control circuit.

FIG. 3 is an explanatory diagram showing an operation of asynchronous writing.

FIG. 4 is an explanatory diagram showing a synchronous writing operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper device 2 Controlled device 10,20 Control part 11,21 Processor circuit 12,22 Shared memory control circuit 12a Sequence control circuit 12b Address FIFO circuit 12c Data FIFO circuit 13,23 Shared memory circuit

Claims (2)

[Claims] 1. A plurality of control units for controlling a controlled device according to an instruction from a host device, wherein the control units include a processor circuit, a shared memory control circuit, and a shared memory circuit, respectively. When receiving the asynchronous write instruction, the first shared memory circuit is instructed to write the data, the second shared memory control circuit is instructed to store the data, and the synchronous write instruction is received from the first processor circuit. Occasionally, instructing the first shared memory circuit to write data and instructing the second shared memory control circuit to write the data and the already stored data in the second shared memory circuit. Characteristic shared memory control circuit. 2. The shared memory control circuit according to claim 1, wherein the second shared memory control circuit for storing the data transferred by the first shared memory control circuit comprises a FIFO circuit, and the data is transferred to the FIFO circuit. A shared memory control circuit, characterized in that