JPH0618851A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of DC bias in a liquid crystal driving circuit. CONSTITUTION:Parasitic capacity between a gate and a source of a TFT Talpha for driving liquid crystal at the time of OFF and ON state are respectively defined as CGSM1, CGSM2, parasitic capacity between a gate and a source of a TFT TC for compensating voltage shift generated at the time of OFF state of a gate pulse of Talpha is defined as CGSC1, fine variations of these parasitic capacity are respectively defined as DELTACGSM1, DELTACGSM2, DELTACGSC1, high level voltage and low level voltage of a gate pulse of Talpha are respectively defined as VGA1, VGA2, similarly, that of TC VGC1, VGC2, and gate voltage at an intermediate point when gate capacity is varied by gate voltage is defined as VTH, sizes of a pulse and parasitic capacity are set so that a equation CGSC1(VGC1-VGC2)+ CGSM1(VGA2-VTH)+CGSM2(VTH-VGA1) O, DELTACGSC1(VGC1-VGC2)+DELTACGSM1(VGA2-VTH)+DELTACCSM2(VTH-VGA1) O be applicable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving circuit,
More specifically, for example, the present invention relates to a liquid crystal drive circuit suitable for use in the field of active matrix liquid crystal display devices, and particularly to a liquid crystal drive circuit for driving liquid crystal by a thin film transistor (TFT). BACKGROUND OF THE INVENTION In recent years, for example, in a display device of an information terminal device such as a computer system, a small television, a projection type projection television and the like, a conventional CRT (Cathode) is used.
An active matrix liquid crystal display device using a thin film transistor has been attracting attention as a small and high-quality display device that replaces a Ray Tube.

This is to display a gradation by controlling the voltage applied to the liquid crystal by a thin film transistor. If the applied drive voltage is not accurate, the display quality is degraded. Therefore, in such an active matrix type liquid crystal display device, it is required to apply an accurate drive voltage by a thin film transistor.

[0003]

2. Description of the Related Art As a conventional liquid crystal drive circuit of this type,
For example, there is one as shown in FIG. In FIG.
Ta is a thin film transistor, C _LC is a liquid crystal, C _GS is a gate-source parasitic capacitance of the thin film transistor Ta, V
_G is a gate pulse voltage, V _S is a terminal voltage, V _D is a liquid crystal side terminal voltage, and V _R is a ground voltage.

In the liquid crystal drive circuit using the thin film transistor having the above structure, as shown in FIG. 7, when the gate pulse voltage V _G falls T ₁ , the parasitic capacitance G _GS between the gate and source of the thin film transistor Ta is caused. Liquid crystal C
Since the terminal voltage V _S at the connection point of the _LC and the thin film transistor Ta is shifted had deviates from a predetermined voltage value written.

In general, the liquid crystal C _LC deteriorates in characteristics when a DC bias is applied, and therefore AC driving is performed. However, the above-mentioned voltage shift causes a DC bias component, which causes a problem of deterioration in characteristics. Therefore, as shown in FIG. 1, a liquid crystal drive circuit has been proposed in which a thin film transistor Tc for compensating a voltage shift is provided in addition to a driving thin film transistor Ta.

In FIG. 1, Ta is a thin film transistor for addressing.
Transistor, Tc is a thin film transistor for voltage shift compensation
Ta, C_LCIs a liquid crystal, C_GSMIs a thin film transistor Ta
Gate-source parasitic capacitance, C_GSCIs a thin film transistor
Gate-source parasitic capacitance of the transistor Tc, V_GAIs address
Gate pulse voltage, V_GCIs the gate pulse voltage for compensation
Pressure, V_SIs the terminal voltage, V_DIs the liquid crystal terminal voltage, V_RHa
Land voltage. In addition, V_GA1Is the address gate
Lus high level voltage, V_GA2Is the address gate pal
Low level voltage, V_GC1Is the compensation gate pulse
Level voltage, V _GC2Is the low level of the compensation gate pulse
Voltage.

In the above configuration, the case of opposite side driving will be described with reference to FIG. First, since the driving is on the opposite side, the data voltage is applied as the liquid crystal side terminal voltage V _D. At the falling edge T ₁ of the address gate pulse voltage V _GA , the terminal voltage V _S at the connection point position between the thin film transistor Ta and the thin film transistor Tc shifts as described above, but the gate in the thin film transistor Tc for voltage shift compensation is shifted. - using the coupling due to the parasitic capacitance C _GSC between the source, by causing reverse voltage shift due to the opposite polarity compensating the gate pulse voltage V _GC of the rising time T ₂ of the compensation gate pulse voltage V _GC
Returns to the predetermined voltage value at the time of original writing.

[0008]

However, in such a conventional liquid crystal driving circuit, the coupling due to the parasitic capacitance C _GSC between the gate and the source in the thin film transistor Tc for voltage shift compensation is used to reverse the direction. Since the voltage shift is caused to compensate the voltage shift at the rising time T ₂ of the compensating gate pulse voltage V _GC , there is a problem as described below.

That is, the terminal voltage V_STime T₁Electricity at
The pressure shift is mainly due to the address gate pulse voltage V_GALarge of
The parasitic capacitance C of the thin film transistor Ta for address
_GSMAnd the time T₂Voltage shift at
Return is mainly due to the compensation gate pulse voltage V_GCThe size of
Parasitic capacitance C of thin film transistor Tc for voltage shift compensation
_GSCDetermined by.

Therefore, if the pulse magnitudes of the address gate pulse voltage V _GA and the compensation gate pulse voltage V _GC and the shapes of the thin film transistors Ta and Tc are the same and the pairing is good, the terminal voltage V
_S should return to the original value accurately, but in reality, due to variations in device parameters, the pairing property must be intentionally shifted.

The thin film transistor is an N channel type,
That is, it turns on when the gate voltage is "H",
It will be described that it is turned off in the case of "L". After the compensating gate pulse voltage V _GC rises for compensation (that is, after time T ₂ ), it is time to set the address of another pixel, and therefore it must be in the off state, and therefore FIG. The indicated voltage V _GC1 must be the off-state voltage, and since the voltage V _GC2 shown in FIG. 2 is lower than V ₁ , it is also in the off-state.

On the other hand, an address thin film transistor Ta
Since the normal ON / OFF operation is performed, the voltage V _GA1 shown in FIG. 2 is in the ON state and the voltage V _GA2 is in the OFF state. Since the thin film transistor has different parasitic capacitances between the ON state and the OFF state, in the configuration shown in FIG. 1, the terminal voltage V _S must be adjusted unless the shape of the thin film transistor and the magnitude of the applied pulse are different between the address side and the compensation side. The voltage shift of will not be restored.

This is not a problem when there is no variation in the device parameters of the thin film transistor (for example, pattern size, film thickness, etc.), but in reality, variation occurs depending on the arrangement location, so the pairing is intentionally shifted. ing. This will be described below using mathematical expressions. FIG. 3 shows FIG.
4 is a plan view of FIG. 4, and FIG. 4 is a cross-sectional view taken along the line AA ′ of FIG.

In FIG. 3, DL is the drain electrode width, G
S _M is the source electrode width of the thin film transistor Ta, GS _C is the source electrode width of the thin film transistor Tc, L is the channel length, W is the channel width, and in FIG. 4, d ₁ is the insulating film + a
-Si film thickness, d ₃ is the thickness of only an insulating film. In the above configuration, the capacity when the address side is off is

[0015]

[Equation 4]

Therefore, the capacity when the address side is on is

[0017]

[Equation 5]

The capacity on the compensation side when off is

[0019]

[Equation 6]

[0020] Note that ε ₀ is the dielectric constant of vacuum and ε ₁
Is the relative dielectric constant of the insulating film. In order to adjust the area ratio between the address side and the compensation side, the source electrode width GS has different values (GS _M and GS _C ) between the thin film transistors Ta and Tc. As described above, the parasitic capacitance of the thin film transistor is determined by the area of a-Si when turned on and the area of the source electrode when turned off.

Therefore, as shown in FIG. 2, the voltage V ₁ after the voltage shift is

[0022]

[Equation 7]

The compensated voltage V ₂ represented by

[0024]

[Equation 8]

It is represented by In addition, as shown in FIG.
_TH is the gate voltage at the midpoint when the parasitic capacitance of the thin film transistor changes with the gate voltage. Here, for example, if the source electrode widths GS _M and GS _C become narrower than the design value, as shown in [Equation 5], the on-side capacitance on the address side is determined by the area of a-Si. Although there is no change in the capacitance, as shown in [Equation 4] and [Equation 6], the off-time capacitance is determined by the area of the source electrode, so that the capacitance decreases.

Therefore, since the compensation side is determined only by the off-state capacitance, the compensation side has a larger change than the address side, and the conditions for canceling the voltage shift differ. That is, assuming that the source electrode width GS is narrower than the design value by x μm on one side, the condition that the voltage V ₂ = 0 is obtained from [Formula 4] to [Formula 8].

[0027]

[Equation 9]

Then, some device parameter (film thickness,
In the case of (dimension), what voltage each pulse should be set to is determined. Further, when a pulse satisfying [Equation 9] is substituted into [Equation 8] when the source electrode width GS is reduced by x μm on one side,

[0029]

[Equation 10]

Substituting x = 0 into [Equation 10] results in V ₂ = 0. That is, when there is no pattern thinning, the voltage shift is completely compensated by setting the pulse voltage by [Equation 9], but when the thinning occurs, [Equation 1]
[0], the value is determined by various parameters and does not become 0. In this case, the set voltage of the pulse may be changed according to [Numerical equation 9] according to the narrowed value, but this is known in advance how much the pattern and the film thickness are different for each row of the liquid crystal panel. In the above, a gate pulse having a slightly different magnitude is added to each column, which is practically impossible.

Therefore, even if the condition for canceling the magnitude of the pulse is set, V ₂ shown in FIG. 2 does not become 0 V, and in the circuit shown in FIG. 1, when variations in device parameter values are taken into consideration. Since the condition for canceling the voltage shift becomes very complicated, it is almost impossible to set V ₂ = 0V uniformly at any place, and therefore, the DC bias component is added to the liquid crystal depending on the place. Caused deterioration of characteristics.

[Object] Therefore, an object of the present invention is to provide a liquid crystal drive circuit for preventing the generation of a DC bias component.

[0033]

In order to achieve the above object, a liquid crystal driving circuit according to the present invention includes a first thin film transistor for driving a liquid crystal and a second thin film transistor for compensating a voltage shift generated when a gate pulse of the first thin film transistor is turned off. In a liquid crystal drive circuit having a thin film transistor, the gate-source parasitic capacitance when the first thin film transistor is off is C _GSM1 , the gate-source parasitic capacitance when the first thin film transistor is on is C _GSM2 , and the second When the thin film transistor is off, the gate-source parasitic capacitance is C _{GS C1} , and the minute capacitance changes of the respective parasitic capacitances C _GSM1 , C _GSM2 , C _GSC1 are ΔC _GSM1 , ΔC _GSM2 , Δ, respectively.
C _GSC1 , the high level voltage of the gate pulse of the first thin film transistor is V _GA1 , the low level voltage is V _GA2 , and the high level voltage of the gate pulse of the second thin film transistor is V _GA1 .
_GC1 , the low level voltage is V _GC2 , and the gate voltage at the intermediate point when the gate capacitance changes with the gate voltage is V
_{If TH}

[0034]

[Equation 11]

[0035]

[Equation 12]

The configuration is such that the magnitude of the pulse and the parasitic capacitance satisfying the above two expressions are set. In this case, each of the thin film transistor, covering the source and drain electrodes in a-Si film, respectively, further, the insulating film, which was covered sequentially with a gate, a source electrode width of the first TFT GS _M, The source electrode width of the second thin film transistor is GS _C , the drain electrode width of each thin film transistor is DL, the channel width is L, the total film thickness of the a-Si film and the insulating film is d ₁ , and the film thickness of the insulating film is d. ₃ , when the ratio GS _C / GS _M of the source electrode widths GS _M and GS _C is n,

[0037]

[Equation 13]

It is preferable to satisfy the following equation:
Further, the gate pulse voltage width (V _GC1 −V _GC2 ) of the second thin film transistor is equal to the gate pulse voltage width (V _TH −V _GA2 or V _GA1 −) of the first thin film transistor.
It is effective to make it an integral multiple of V _TH ).

[0039]

In the present invention, when the source electrode area ratio of the first thin film transistor and the second thin film transistor has a specific value, the voltage shift is compensated regardless of the film thickness and the pattern shift. That is, the voltage shift is uniformly suppressed, and D
Generation of the C bias component is prevented.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Since the structure of the liquid crystal drive circuit according to the present invention is the same as that of the conventional example shown in FIGS. 1 to 4, the description thereof will be omitted. Rearranging the above [Equation 9] to form “n =”,

[0041]

[Equation 14]

Here, the source electrode width ratio n is expressed by
When the value is set as shown in, V ₂ = 0. This is to cancel all parameters at voltage V ₂ regardless of their absolute value. Therefore, the dimensional ratio n is
4], the voltage shift becomes 0V regardless of the deviation of the absolute value of each parameter.

Further, if each pulse satisfies, for example, V _TH -V _GA2 = V _GA1 -V _TH = V _GC1 -V _GC2 in [Equation 14], the condition of the size ratio n is further simplified, and n
Is

[0044]

[Equation 15]

It is represented by In this case, V _TH −V _GA2 , V
_GA1 -V _TH, the values of V _GC1 -V _GC2 are not equal, if an integral ratio, simplifies to Equation 15]. Hereinafter, description will be given based on specific numerical values. now,
Assuming that a thin film transistor having V _TH of 0 V is used, V _GA1 = 10 V and V _GA2 = −10 in FIG.
If V, V _GA1 = −10 V, and V _GA2 = −20 V, then these satisfy V _TH −V _GA2 = V _GA1 −V _TH = V _GC1 −V _GC2 .

Next, as an example of the device parameter, d
₁ = 0.325 μm, d ₃ = 0.3 μm, GS _M = 10
If μm, DL = 10 μm, and L = 5 μm, then [Equation 1
5]

[0047]

[Equation 16]

Therefore, if the source electrode width GS _C of the voltage shift compensating thin film transistor Tc is set to 2.354 times the source electrode width GS _M of the address thin film transistor Ta, the voltage shift can be suppressed regardless of variations. As described above, in this embodiment, the source electrode width ratio between the address side and the compensation side is set to a predetermined value determined by the device parameter, so that the gate pulse of the address side is not affected even if the parameter varies depending on the location. The voltage shift that occurs at the fall can be suppressed uniformly,
It is possible to prevent deterioration of characteristics due to generation of DC component.

[0049]

According to the present invention, when the source electrode area ratio of the first thin film transistor and the second thin film transistor has a specific value, the voltage shift can be compensated regardless of the film thickness and the pattern shift. Therefore, the voltage shift can be suppressed uniformly, and the generation of the DC bias component can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal drive circuit according to an embodiment and a conventional example.

FIG. 2 is a timing chart for explaining the operation of FIG.

FIG. 3 is a plan view of FIG.

4 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 5 is a diagram showing a gate voltage at an intermediate point when the parasitic capacitance changes according to the gate voltage.

FIG. 6 is a circuit showing a configuration of a main part of a conventional example.

7 is a timing chart for explaining the operation of FIG.

[Explanation of Codes] Ta thin film transistor (for address) Tc thin film transistor (for voltage shift compensation) C _LC liquid crystal C _GS Thin film transistor Ta gate-source parasitic capacitance C _GSM Thin film transistor Ta gate-source parasitic capacitance C _GSC thin film transistor Tc Gate-source parasitic capacitance of V _G Gate pulse voltage V _GA Address gate pulse voltage V _GA1 Address gate pulse high level voltage V _GA2 Address gate pulse low level voltage V _GC compensation gate pulse voltage V _GC1 compensation low-level voltage V _S terminal voltage V _D on the liquid crystal side terminal voltage V _R the ground voltage of the use gate pulse high voltage V _GC2 compensation gate pulse

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Fumiyo Takeuchi 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (3)

[Claims] 1. A first thin film transistor for driving a liquid crystal, and
This occurs when the gate pulse of the first thin film transistor is turned off.
A second thin film transistor that compensates the voltage shift due to
In the liquid crystal driving circuit according to claim 1,
The parasitic capacitance between _GSM1, Of the first thin film transistor
The parasitic capacitance between the gate and the source when turned on is C_GSM2,
The gate-source when the second thin film transistor is off.
The parasitic capacitance between_GSC1, The parasitic capacitance C_GSM1, C
_GSM2, C_GSC1ΔC_GSM1, Δ
C_GSM2, ΔC_GSC1, The gate pattern of the first thin film transistor
The high level voltage of the lus is V_GA1, Low level voltage V
_GA2, The gate pulse high voltage of the second thin film transistor
Bell voltage is V_GC1, Low level voltage V_GC2, The gate Yong
The amount at the midpoint when the amount varies with the gate voltage.
Voltage to V_THIf, then,[Equation 2]Set the magnitude of the pulse and parasitic capacitance that satisfy the two equations
A liquid crystal drive circuit characterized by the above. 2. Each of the thin film transistors has a source electrode and a drain electrode covered with an a-Si film, and
The source electrode width of the first thin film transistor is GS _M , the source electrode width of the second thin film transistor is GS _C , the drain electrode width of each thin film transistor is DL, and the channel width is L. , The total film thickness of the a-Si film and the insulating film is d ₁ , the film thickness of the insulating film is d ₃ , the ratio GS of the source electrode widths GS _M and GS _{C.
If C} / GS _M is n, then 2. The liquid crystal drive circuit according to claim 1, wherein the formula is satisfied. 3. The gate pulse voltage width (V _GC1 -V _GC2 ) of the second thin film transistor is equal to the gate pulse voltage width (V _TH -V _GA2 or V _TH of the first thin film transistor).
3. The liquid crystal drive circuit according to claim 1, wherein the liquid crystal drive circuit is an integral multiple of ( _GA1− V _TH ).