JPH06187466A - Semiconductor and microcomputer system - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory which can ensure the universal applicability of a controller and to facilitate the construction of its compact structure together with high reliability and the high speed driving performance. CONSTITUTION:A semiconductor memory 3 consists of a controller 3a which includes an address generating circuit, a data generating circuit and a semiconductor memory control signal generating circuit, and the semiconductor memory 3b1-3bn which undergo the driving control through the controller 3a. The device 3b1-3bn contain the identification information storage circuits which store the identification information for mutual discrimination and the discrimination information discriminating circuits which identify the identification information on the identification information storage circuits respectively. Then a microcomputer system consists of a CPU 1, a main memory and an input/output device and uses the memory 3 as the main memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a simplified and compact circuit structure, and a microcomputer system using this semiconductor memory device.

[0002]

As is well known, a semiconductor memory device or a semiconductor memory device is widely put to practical use as a main memory of a microcomputer system or a memory of various cards such as a memory card. For example, in a microcomputer system including a central processing unit, a main memory, and an input / output device, a plurality of semiconductor memory devices form a main memory in order to increase the storage capacity. That is, as shown in the schematic configuration of FIG. 3 as a block diagram, a controller including an address generation circuit, a data generation circuit, a semiconductor memory element control signal generation circuit, and a semiconductor memory element selection signal generation circuit for the central processing unit 1. 2
a and a semiconductor memory device ₂ including a plurality of semiconductor memory devices 2b ₁ , 2b ₂ , ... 2b _n whose drive is controlled by the controller 2a, is attached as a main memory (external storage device). ing. Here, the controller 2a drives the corresponding generation circuits by the address bus, the data bus, the write signal, the read signal, and the address enable signal from the central processing unit 1. Address input, data input / output, read (output) enable input, and write enable input are sequentially applied to the semiconductor memory devices 2b ₁ , 2b ₂ , ... 2b _n in response to the driving of the generation circuit of the controller 2a. On the other hand, one of these semiconductor memory elements 2b ₁ , 2b ₂ , ..., 2b _n is selected by a chip select signal, and required data is written / read out. That is, in the case of the semiconductor memory device 2, the address bus, the data bus, the write signal, and the read signal are common to the respective semiconductor memory elements 2b ₁ , 2b ₂ , ... 2b _n ,
The chip select signal driven by the address enable signal and the address bus signal is supplied to the semiconductor memory devices 2b ₁ and 2
Each of b ₂ , ... 2b _n is branched and connected to the controller 2a.

[0003]

The above-mentioned semiconductor memory device 2 has an advantage that it can be made compact and can be driven at high speed, as compared with a memory device mainly including a so-called floppy disk, but the following problems are still encountered. There is.
In other words, while achieving the compactness and high speed driving,
In order to increase (increase) the memory capacity further, when adding / attaching semiconductor memory elements, it is necessary to separately replace with a controller 2a having a corresponding chip select signal terminal, and a chip included in the controller 2a. The select signal generation circuit (which is configured using a latch and a decoder) also becomes complicated. Then, the lack of versatility of the controller 2a inevitably leads to the production of a variety of controllers 2a, while the complexity of the chip select signal generation circuit leads to a reduction in size, reliability, or high-speed driveability. However, it is difficult to say that it has a function (performance) that is satisfactory for practical use. In particular, having the chip select signal wiring for each of the semiconductor memory devices 2b ₁ , 2b ₂ , ..., 2b _n causes adverse effects such as downsizing of the semiconductor memory device 2 and signal delay.

The present invention has been made in consideration of the above circumstances, and not only can the controller have general versatility,
It is an object of the present invention to provide a semiconductor memory device which is easy to achieve compactness and has excellent reliability and high-speed driveability, and a microcomputer system which uses the semiconductor memory device as a main memory.

[0005]

A semiconductor memory device according to the present invention includes a controller having an address generation circuit, a data generation circuit, and a semiconductor memory device control signal generation circuit, and a plurality of drives whose driving is controlled by the controller. And a semiconductor memory device, wherein each semiconductor memory device identifies an identification information storage circuit that stores identification information for distinguishing each other and identification information of the identification information storage circuit. The microcomputer system according to the present invention further comprises a central processing unit, a main memory, and an input / output device, wherein the main memory includes an identification information identification circuit. The semiconductor memory device having the above structure is used. That is, a controller including an address generation circuit, a data generation circuit, and a semiconductor memory device control signal generation circuit,
A semiconductor memory device comprising a plurality of semiconductor memory elements whose driving is controlled by the controller, wherein each of the semiconductor memory elements stores an identification information storage circuit for storing identification information for distinguishing each other. A semiconductor memory device having an identification information identification circuit for identifying the identification information of the identification information storage circuit is provided as a main memory.

[0006]

According to the semiconductor memory device of the present invention, the plurality of semiconductor memory devices forming the main memory store the identification information storage circuit for storing identification information for distinguishing each other and the identification information storage circuit. When a so-called access is made, one of the semiconductor memory devices is selected and set in the active state by the first address signal transfer when the so-called access is made. The semiconductor memory device selected / set in the active state selectively receives the second address signal transfer, and data is exchanged in accordance with the instructed address signal. That is, the identification information number which is previously written in the identification information storage circuit of each semiconductor memory element is previously selected and designated for each semiconductor memory element via the identification information (ID) write signal pin. Thereafter, based on this selection / designation, the predetermined semiconductor memory device is automatically set to the active state, and the required access proceeds.

[0007]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration example of a main part of a semiconductor memory device according to the present invention. 3 is an address generation circuit,
Controller 3a including data generation circuit and semiconductor memory device control signal generation circuit, and the controller
Multiple semiconductor memory devices whose drive is controlled by 3a
It is a semiconductor memory device comprising 3b ₁ , 3b ₂ , ... 3b _n . The semiconductor memory devices 3b ₁ , 3b ₂ , ... 3b _n forming the main part of the semiconductor memory device 3 are respectively written via the write signal pin 4 and are identification information for distinguishing each other, that is, Semiconductor memory device 3
An identification information (ID) storage circuit that stores a different identification information number for each b ₁ , 3b ₂ , ... 3b _n , and this identification information (I
D) It is characterized by having a configuration including an identification information (ID) identification circuit for identifying the identification information of the memory circuit.

Next, the operation or use of the semiconductor memory device 3 having this structure will be described. First, the semiconductor memory device 3b _1, 3b _2, ... per 3b _n, prior to connection to a controller 3a, the semiconductor memory device _{3b 1, 3b 2, ... 3b} n
Each time, with the write signal pin 4 activated, the different identification information (ID) is written to the built-in identification information (ID) storage circuit using the address bus or the data bus. Remember.
Identification information (ID) containing the identification information (ID)
Each semiconductor memory element 3b written / stored in the memory circuit
₁ , 3b ₂ , ... 3b _n as main memory (external storage device)
The semiconductor memory device 3 is connected to the controller 3a, and if necessary, the semiconductor memory device 3 is connected to the central processing unit 1 or the like to form, for example, a microcomputer system.

In this configuration, when the central processing unit 1 drives or accesses the semiconductor memory device 3, a required address signal is transferred twice using the address bus.
At this time, the first address signal is applied to each semiconductor memory device.
3b ₁ , 3b ₂ , ... 3b _n are mutually distinguished (divided),
Different identification information numbers are transferred to the respective semiconductor memory elements 3b ₁ , 3b ₂ , ... 3b _n . The transfer of the identification information number, each semiconductor memory device 3b _1, 3b ₂ are connected to a common address bus, ... 3b _n receives the respective semiconductor memory elements 3b _1, 3b _2, ... for each 3b _n The identification information number stored in the memory circuit is compared and compared with the identification circuit also built in, and only one semiconductor memory element having the same identification information number (written) is selected in the active state. Is set. In this way, one semiconductor memory device selected and set in the active state is
Upon receiving the address signal for the second time, required data is exchanged with the instructed address signal.

FIG. 2 is a block diagram showing the main part of another configuration example of the semiconductor memory device according to the present invention. Instead of the address generation circuit of the controller 3a in the above configuration example,
Controller with a built-in logical address generation circuit
a 'and the semiconductor memory device 3b _1, 3b _2, ... a common address bus and 3b _n and a logical address writing signal, and configured to transfer an address signal and the identification information ID in the data bus of the multiplexer.

In the operation or use of the semiconductor memory device 3 having this structure, first, the respective semiconductor memory elements 3b ₁ and 3b are
₂ , ... 3b _n , prior to connection with the controller 3a ′, for each semiconductor memory device 3b ₁ , 3b ₂ , ... 3b _n , with the write signal pin 4 activated respectively, and the multiplexer of the data bus. The identification information (ID) different from each other is stored by using the identification information (I
D) Write / store in the memory circuit. Each of the semiconductor memory devices 3b ₁ , 3b ₂ , ... Written and stored in an identification information (ID) storage circuit containing the identification information (ID).
Controller with 3b _n as main memory (external storage)
The semiconductor memory device 3'is connected to 3a ', and if necessary, the semiconductor memory device 3'is connected to the central processing unit 1 or the like to form, for example, a microcomputer system.

When writing or reading required data to or from the semiconductor memory device 3 ', first,
An identification number for activating a logical address write signal and then selecting a semiconductor memory device to be accessed,
And, the address signal for transmitting and receiving data is instructed by dividing into several bytes using the data bus. Based on this instruction, the semiconductor memory device having the designated identification information number (written) is selectively activated, and the required data is transmitted / received to / from the designated address signal. Will be seen.

[0014]

As can be seen from the above description, in the semiconductor memory device according to the present invention, the so-called controller is general-purpose, and the storage capacity is increased (increased). It becomes possible to attach (connect). That is, since a required semiconductor memory element can be selectively accessed without requiring a selection signal circuit or the like for a plurality of semiconductor memory elements provided side by side, not only is a dedicated controller unnecessary, but also the semiconductor memory element is not required. The simplification of the circuit configuration and the improvement of reliability can be easily achieved due to the elimination of the selection signal circuit. Therefore, it can be said that this semiconductor memory device brings many practical advantages as a storage device of various cards or computer systems.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a main part of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing an example of the main part configuration of a semiconductor memory device according to the present invention.

FIG. 3 is a block diagram showing a main configuration of a conventional semiconductor memory device.

[Explanation of symbols]

1 ... Central processing unit 2, 3, 3 '... Semiconductor memory device
2a, 3a, 3a '... Controllers 2b ₁ , 2b ₂ , 3
b ₁ , 3b ₂ ... semiconductor memory device 4 ... write signal pin

Claims (2)

[Claims] 1. A semiconductor memory device comprising: a controller having an address generation circuit, a data generation circuit, and a semiconductor memory device control signal generation circuit; and a plurality of semiconductor memory devices whose drive is controlled by the controller. Wherein each of the semiconductor memory elements includes an identification information storage circuit that stores identification information for distinguishing each other and an identification information identification circuit that identifies the identification information of the identification information storage circuit. Semiconductor memory device. 2. A microcomputer system comprising a central processing unit, a main memory, and an input / output device, wherein the main memory is an address generation circuit, a data generation circuit,
A semiconductor memory device comprising: a controller having a semiconductor memory device control signal generation circuit; and a plurality of semiconductor memory devices whose driving is controlled by the controller, wherein the semiconductor memory devices are distinguished from each other. A microcomputer system having a built-in identification information storage circuit for storing identification information for performing identification and an identification information identification circuit for identifying identification information of the identification information storage circuit.