JPH06187064A - Method and device for controlling clock - Google Patents

Abstract

PURPOSE:To make continuous operations possible by preventing the abnormal operation or fault of the device while suppressing the temperature increase of the device, and preventing the processing of a CPU from being interrupted by the temperature increase of the device. CONSTITUTION:A CPU controller for controlling a CPU 116 is provided with temperature sensors 101-10N for detecting the temperature of a circuit 117 to be controlled by the CPU 116, basic clock and down clock preparation parts 112 and 113 for generating clock signals in different cycles, and control part 111 for outputting a clock switching signal 131 by comparing the outputs of the temperature sensors 101-10N with a set value. Further, a clock selector part 115 is provided to selectively output either a basic clock signal 132 or a low-speed clock signal 133 corresponding to the clock switching signal 131, and the cycle of a clock signal 135 is switched corresponding to temperature state signals 121-12N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control method and a clock control device in a CPU control device.

[0002]

2. Description of the Related Art Generally, a central processing unit (hereinafter referred to as CPU) is controlled by a CPU control unit. Then, this CPU control device supplies a clock signal of a constant cycle to the CPU and performs processing in synchronization with this clock signal. Then, in order to prevent abnormal operation or failure due to the temperature rise of the CPU, conventionally, a process of stopping the CPU by detecting the temperature rise of the CPU is performed.

A conventional clock control method and its control device will be described below. FIG. 9 is a block diagram of a conventional clock controller, and FIG. 10 is a flowchart of the conventional clock controller. In FIG. 9, 201 is a temperature sensor, 202 is a control unit, 203 is a basic clock generation unit, 204 is a CPU, 205 is a controlled circuit, 211 is a temperature state signal, 212 is a stop signal, and 213 is a basic clock signal.

The temperature state signal 211 output from the temperature sensor 201 is input to the control unit 202, and the control unit 202
The stop signal 212, which is the output of, is input to the CPU 204. The temperature sensor 201 is attached to an arbitrary part of the device in which the clock control device is installed and measures the temperature of that part. Then, the control unit 202 inputs the temperature state signal 211 which is the output of the temperature sensor 201 and compares the temperature state signal 211 with a preset set value. By this comparison, it is possible to detect the temperature rise in the device.

When the temperature rise exceeds the set value, the control unit 202 outputs a stop signal 212 to the CPU 204 to stop the operation of the control unit 202. In addition, the basic clock signal 2 output from the basic clock generation unit 203
13 is input to the CPU 204 and other controlled circuits 205. The clock control device shown in the block diagram of FIG. 9 is used by being incorporated in an arbitrary device.

A conventional clock control device will be described below with reference to the flowchart of FIG. Step S20: Generally, in a normal operating state,
The CPU 204 executes processing in synchronization with the basic clock signal 213. Step S21: It is determined whether or not the temperature inside the device in which the clock control device is installed exceeds the set temperature. This determination is performed by comparing the temperature state signal 211 of the temperature sensor 201 installed in the device in which the clock control device is installed with the preset value T1.

The set value T1 is determined by the temperature sensor 20.
1 is determined in accordance with the set temperature at the position where 1 is attached. That is, when the temperature inside the device in which the clock control device is installed rises during the operation of the CPU 204, the temperature sensor 201 detects this rise in temperature and inputs the temperature state signal 211 to the control block 202.

The control unit 202 compares the set temperature signal 211 set with a preset value signal corresponding to a preset temperature T1 arbitrarily set, and the detected temperature T is equal to or higher than the preset temperature T1 (T> T1). ), The stop signal 212 is output to the CPU 204, and the process proceeds to step S22. On the other hand, in the comparison between the set temperature T1 and the detected temperature T in the control block 202, the detected temperature T is the set temperature T1.
In the following case (T <T1), the processing is continued in synchronization with the basic clock signal 213.

Step S22: The CPU 204 immediately stops its processing when the stop signal 212 is input. Then, the stopped state is continued until the temperature of the device drops. The determination of the temperature drop of the device is performed in step S21. When the detected temperature is determined to be equal to or lower than the set temperature, the process returns to step S20 and the operation based on the reference clock signal is performed again.

By the above operation, abnormal operation and failure due to the temperature rise of the device are prevented.

[0011]

However, the conventional clock control device cannot be used in a system that requires continuous processing because the operation of the CPU is stopped due to the temperature rise and the processing is intermittent. There is a problem. The present invention solves the above-mentioned problems of the conventional clock control device, suppresses the temperature rise of the device at the time of temperature rise, prevents abnormal operation and failure of the device, and improves the processing of the CPU due to the temperature rise of the device. An object of the present invention is to provide a clock control method and a control device capable of preventing interruption and capable of continuous operation.

[0012]

In order to achieve the above object, the present invention provides a CPU control method for controlling a CPU after detecting the temperatures of the CPU and a device controlled by the CPU to obtain a detected temperature. The detected temperature is compared with the set temperature to switch the clock signal for synchronizing the operation of the CPU. When the temperature rises, the clock signal is switched to the slow clock cycle, and conversely, when the temperature drops, the fast clock cycle is switched. It switches to a signal.

Further, in a CPU control device for controlling the CPU, a temperature sensor for detecting the temperature of the CPU and the device controlled by the CPU, a clock generation unit for generating clock signals having different cycles, and an output of the temperature sensor are set. A clock selector that outputs a clock switching signal in comparison with a value and a clock selector that selects and outputs the clock signal according to the clock switching signal, and switches the clock cycle according to the detected temperature. The selection of the clock signal in the unit can be performed by the timing signal obtained from the clock switching signal. Further, at the time of switching, the control unit controls to switch to a clock signal with a slow clock cycle when the temperature rises and to switch to a clock signal with a fast clock cycle when the temperature falls.

[0014]

According to the clock control method and the control device of the present invention, when the temperature sensor detects the temperature rise and exceeds the set temperature when the temperature rises, a switching signal and a switching timing signal are issued. It is possible to switch from the basic clock signal to a low-speed clock signal with a slow clock cycle, and when the temperature of the device drops, the switching signal and the switching timing signal are issued again to send a low-speed clock signal with a slow clock cycle. The signal can be switched to the basic clock signal.

As a result, the temperature rise of the device is suppressed to prevent abnormal operation and failure of the device, and C
It is possible to prevent interruption of processing of the PU and enable continuous operation.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of the clock control device of the present invention, and FIG. 2 is a flowchart of the clock control device of the present invention. In FIG. 1, 101 to 1
0N is a temperature sensor, 111 is a control unit, 112 is a basic clock generation unit, 113 is a down clock generation unit, 114 is a timing generation unit, 115 is a clock selector unit, 11
6 is a CPU, 117 is a controlled circuit, 121 to 12N are temperature state signals, 131 is a clock switching signal, 132 is a basic clock signal, 133 is a low speed clock signal, 134 is a timing signal, and 135 is a clock signal.

The temperature sensors 101 to 10N are the CPU 11
6 and controlled circuit 11 controlled by CPU 116
It is installed in a device such as 7 and detects the temperature of the device. The installation positions of the temperature sensors 101 to 10N can be installed at a plurality of places of the apparatus, and the temperature condition of the installation position is transmitted to the control unit 111 as temperature condition signals 121 to 12N.

The control unit 111 includes temperature sensors 101-10.
The temperature condition signals 121 to 12N transmitted from N are compared with a preset temperature T1.
For example, it is created by a comparator (not shown) or the like. According to the comparison result, the control unit 111 transmits the clock switching signal 131 to the timing creation unit 114. The clock switching signal 131 switches between the basic clock signal and the low speed clock signal.

The timing generation unit 114 receives the clock switching signal 131 and transmits a timing signal 134 for determining the timing for switching the clock signal 135 to the clock selector unit 115. Further, in the clock selector 115, in addition to the timing signal from the timing generator 114, the basic clock signal 132 from the basic clock generator 112 and the down clock generator 11 are provided.
3 is input, and either the basic clock signal 132 or the low speed clock signal 133 is selected according to the timing signal to select the clock signal 13
Output as 5.

The down clock generating section 113 is composed of a counter or the like and divides the basic clock signal 132 to generate a low speed clock signal 133 having a cycle slower than that of the basic clock signal 132. The clock switching signal 131 is composed of a flip-flop or the like and generates a clock switching timing signal 134.

Then, the clock signal 135 output from the clock selector unit 115 is input to the CPU 116 or the controlled circuit 117, and this clock signal 135 is input.
Will be synchronized by. Hereinafter, description will be made according to the flowcharts of the clock control device of the present invention shown in FIGS.

Step S1: In a normal operation state, the CPU 116 and the controlled circuit 117 carry out the processing in synchronization with the basic clock signal 132. Step S2: The control unit 111 controls the temperature sensors 101 to 1
If the detected temperature T of the temperature sensors 101 to 10N exceeds the set temperature T1 (T> T1), the temperature state signals 121 to 12N transmitted from 0N are compared with a preset set temperature T1. In S3, the clock switching signal 131 is output. On the other hand, the temperature sensors 101 to 1
When the detected temperature T of 0 N does not exceed the set temperature T1 (T <T1), the process returns to step S1 and the CPU 116
The controlled circuit 117 is driven in synchronization with the basic clock signal 132.

The set temperature T1 is determined by the temperature sensors 101 to 10
It is also possible to set one set temperature for the temperature state signals 121 to 12N transmitted from N.
It can also be set individually for 10N. When the set temperatures T1 are individually set corresponding to the temperature sensors 101 to 10N, for example, a low set temperature is set at a position where the temperature tolerance is small, and a high set temperature is set at a position where the temperature tolerance is large. The set temperature T1 can be determined according to the importance of the position of the device with respect to the temperature.

The set temperature T1 is a set temperature when the clock signal 135 is switched from the basic clock signal 132 to the low speed clock signal 133, and when the clock signal 135 is switched from the low speed clock signal 133 to the basic clock signal 132. The set temperature is set to a set temperature T2 lower than the set temperature T1. Hereinafter, the two set temperatures of the set temperature T1 and the set temperature T2 will be described with reference to FIG.
The temperature hysteresis diagram of the clock signal and the switching diagram according to the temperature of the clock signal of FIG.

In comparison of the temperatures in the control unit 111 of FIG. 1, the set temperature is given a temperature hysteresis as shown in FIG. This temperature hysteresis is for preventing chattering of the clock switching signal 131. In FIG. 3, the temperature of the apparatus is from low temperature to set temperature T2
Is the clock frequency of the basic clock signal shown by in the figure, and the set temperature T2 to the set temperature T1 is the clock frequency of the basic clock signal shown by in the figure. When the set temperature T1 is exceeded, as shown by Move to the clock frequency of the clock signal. The direction of this movement is irreversible and is the direction of the arrow indicated by in the figure.

When the temperature further rises and is equal to or higher than the set temperature T1, the clock frequency of the low-speed clock signal is as shown in the figure. The temperature falls and the set temperature T1 to the set temperature T2 is the clock frequency of the basic clock signal shown by in the figure. Further, when the temperature drops below the set temperature T1, it moves to the clock frequency of the basic clock signal as shown in the figure. The directions of movement of the figures and of figures are irreversible and are the directions of the arrows indicated by and of the figures.

Next, the switching state of the clock signal depending on the temperature due to the temperature hysteresis will be described with reference to FIG. In addition, (a) of FIG. 4 corresponds to (a) of FIG. First, when the temperature of the device is lower than the set temperature T2, synchronization is achieved by the basic clock signal as shown in FIG. From this state, when the temperature rises and the temperature is between T2 and T1, the clock frequency is the basic clock signal as shown in FIG. 3, so there is no change in the clock frequency, and as shown by I in FIG. 4B. Synchronization is achieved by the basic clock signal.

Next, when the temperature exceeds the set temperature T1, FIG.
The clock frequency is switched from the basic clock signal to the low-speed clock signal as shown in, and II of FIG.
As described above, the low-speed clock signal is used for synchronization. Figure 3
As shown in, the clock frequency is a low-speed clock signal when the temperature is equal to or higher than the set temperature T1, and the temperature drops from this state until the temperature reaches the set temperature T2 as shown in FIG. Becomes a low-speed clock signal,
After all, in FIGS. 4A to 4C, synchronization is achieved by the low-speed clock signal as indicated by II in FIG. 4B.

Further, when the temperature drops to the temperature T2, the clock frequency shifts from the low speed clock signal to the basic clock signal as shown in FIG. As a result, synchronization is achieved with the basic clock signal as shown by III in FIG. This can prevent chattering in switching between the low speed clock signal and the basic clock signal.

Step S3: In the step S2, when the detected temperature T of the temperature sensors 101 to 10N exceeds the set temperature T1, the control section 111 generates the clock switching signal 131. This clock switching signal 131 is
It is for switching the clock signal from the basic clock signal 132 to the low-speed clock signal 133, and is sent to the timing generation unit 114.

Step S4: The timing signal 134 generated by the timing generation unit 114 is actually the basic clock signal 13 based on the clock switching signal 131.
2 and the low-speed clock signal 113 is switched, and the switching timing is monitored in this step. This is to prevent abnormalities in the clock waveform during switching.

At the time of switching between the basic clock signal 132 and the low-speed clock signal 133, the time when there is no difference in the intervals of the clock signals is measured, and the processing of step S5 is performed at that time. Step S5: In this step, the timing generation unit 114 transmits the timing signal 134 to the clock selector unit 115 to select the basic clock signal 132 and the low speed clock signal 133.

Here, the function of the timing signal will be described. FIG. 5 is a clock signal diagram selected by the clock switching signal, and FIG. 6 is a clock signal diagram selected by the timing signal. First, a state in which the clock signal is selected by the clock switching signal will be described with reference to FIG. In FIG. 5, (a) is the basic clock signal 132, (b) is the low-speed clock signal 133,
(C), (e), (g) and (i) are clock switching signals 1
Reference numerals 31, (d), (f), (h), and (j) indicate the clock signal 135. Then, the clock signal 135
(D), (f), (h), and (j) are selected by the clock switching signals 131 (c), (e), (g), and (i), respectively, and are (A) and (A), respectively. B),
It shall be represented by (C) and (D).

Here, the low-speed clock signal 133 shown in (b) is the basic clock signal 132 shown in (a).
Is divided into 1/3 and, for example, t in FIG.
It is assumed that a signal is output at 0 and t3. In the case of (A): As shown in (c), when the clock switching signal 131 is generated at time t10 immediately before the time t0 of the basic clock signal 132, the clock signal 135 in (d) is the low-speed clock from the time t0. Signal 13
3 is output.

In this case, as shown in (d),
Basic clock signal 1 before and after switching the clock signal 135
The time interval between 32 and the low-speed clock signal 133 is t. For (B): As shown in (e),
When the clock switching signal 131 is generated at the time t11 between the time t0 and the time t1 of the clock signal 132 of (a), the clock signal 135 shown in (f) is changed to the time t3.
Outputs the low-speed clock signal 133.

In this case, the time interval between the basic clock signal 132 and the low-speed clock signal 133 before and after the switching of the clock signal is 3t. In the case of (C): As shown in (g),
Time t1 and time t2 of the basic clock signal 132 in (a)
When the clock switching signal 131 is generated at time t12 during the period, the clock signal 135 shown in (h) outputs the low-speed clock signal 133 from time t3.

In this case, the basic clock signal 132 and the low-speed clock signal 1 before and after the switching of the clock signal 135.
The time interval of 33 is 2t. In case of (D): As shown in (i),
Time t2 and time t3 of the basic clock signal 132 in (a)
When the clock switching signal 131 is generated at time t13 during the period, the clock signal 135 shown in (j) outputs the low-speed clock signal 133 from time t3.

In this case, the time interval between the basic clock signal 132 and the low-speed clock signal 133 before and after the clock signal switching is 1t. Therefore, depending on the time of generation of the clock switching signal 131, the clock signal 13
The difference between the time intervals of the basic clock signal 132 and the low-speed clock signal 133 before and after the switching of No. 5 will occur.

Next, the state when the clock signal is selected by the timing signal will be described with reference to FIG. Figure 6
, (A) is the basic clock signal 132, (b) is the low-speed clock signal 133, (c), (f), (i),
(L) is the clock switching signal 131, (d), (g),
(J) and (m) are timing signals 134, (e),
(H), (k) and (n) show the clock signal 135. The clock signals 135 (e), (h),
(K) and (n) are timing signals 134, respectively.
It is selected by (d), (g), (j), and (m), and is represented by (A), (B), (C), and (D), respectively.

Here, the low-speed clock signal 133 shown in (b) is the basic clock signal 132 shown in (a).
Is divided into 1/3, for example, t in (a)
It is assumed that a signal is output at 0 and t3. The timing signal 134 shown in FIG. 6 is the clock signal 135.
It is assumed that the time interval between the basic clock signal 132 and the low-speed clock signal 133 before and after the switching is set to 3t. For this reason, the timing of generation of the timing signal 134 is, for example, the point in time 2t after the first basic clock signal 132 after the generation of the clock switching signal 131.

The timing of generation of the timing signal 134 is not limited to this example, and it is possible to use another timing. In the case of (A): As shown in (c), when the clock switching signal 131 is generated at time t10 immediately before time t0 of the clock signal 132, the timing signal 134 of (d) is generated at time t2. (E)
The clock signal 135 of 1 outputs the low-speed clock signal 133 from time t3 according to the timing signal 134.

In this case, the time interval between the basic clock signal 132 and the low-speed clock signal 133 before and after the switching of the clock signal is 3t. In the case of (B): As shown in (f), when the clock switching signal 131 is generated at the time t11 between the time t0 and the time t1 of the basic clock signal 132, the timing signal (g) is generated. 134 is generated at time t3, which is a time interval 2t after time t1. (H)
The clock signal 135 of 1 outputs the low-speed clock signal 133 from time t3 according to the timing signal 134.

In this case, the basic clock signal 132 and the low-speed clock signal 1 before and after the switching of the clock signal 135.
The time interval of 33 is 3t. Case (C): As shown in (i), when the clock switching signal 131 is generated at time t12 between the time t1 and the time t2 of the basic clock signal 132, the timing signal 134 of (j) is changed to the time. It is generated at time t4 after time interval 2t from t2. The clock signal 135 of (k) outputs the low-speed clock signal 133 from time t6 according to the timing signal 134.

In this case, the basic clock signal 132 and the low-speed clock signal 1 before and after the switching of the clock signal 135.
The time interval of 33 is 3t. In the case of (D): As shown in (l), when the clock switching signal 131 is generated at the time t13 between the time t2 and the time t3 of the basic clock signal 132, the timing signal 134 of (m) is changed to the time. It is generated at time t5 after time interval 2t from t3. The clock signal 135 of (n) outputs the low-speed clock signal 133 from time t6 according to the timing signal 134.

In this case, the basic clock signal 132 and the low-speed clock signal 1 before and after the switching of the clock signal 135.
The time interval of 33 is 3t. Therefore, by using the timing signal 134, the clock signal 1 is generated regardless of the time when the clock switching signal 131 is generated.
The time interval between the basic clock signal 132 and the low-speed clock signal 133 before and after the switching of 35 can be held constant.

Step S6: The clock signal is generated by generating the timing signal 134 in the step S5.
5 to switch the basic clock signal 132 to the low-speed clock signal 133. The CPU 116 and the controlled circuit 117 are synchronized by the low speed clock signal 133.

Step S7: By synchronizing with the low speed clock signal 133, the CPU 116 and the controlled circuit 117 operate with the low speed clock signal 135.
As a result, although the processing of the CPU 116 is temporarily operated at a low speed, the continuity of the processing is maintained and the power consumption is reduced due to the low-speed processing, so that the heat generation amount is reduced and the temperature is lowered.

Therefore, in step S7, the detected temperature T and the set temperature T of the temperature state signals 121 to 12N of the temperature sensors 101 to 10N are set in the same manner as in step S2.
2 is compared to determine whether or not the temperature has become equal to or lower than the set temperature T2. The set temperature in this step is lower than the set temperature T1 in step S2.
The reason why the value is set to 2 is to prevent malfunction such as chattering at the time of switching between the basic clock signal 132 and the low speed clock signal 133 due to the hysteresis characteristic described in step S2.

When the detected temperature T drops below the set temperature T2, the process proceeds to step S8, and the clock switching signal 131 is generated as in step S3. On the other hand, when the detected temperature T is equal to or higher than the set temperature T2 and the temperature drop is insufficient, the synchronization with the low-speed clock signal 133 is continued. It should be noted that the temperature sensor 101-
A plurality of 10N can be installed at any position of the apparatus.

The set temperature T2 is the set temperature T1.
Similarly, the temperature state signals 121 to 12N transmitted from the temperature sensors 101 to 10N can be set to one set temperature, or can be individually set corresponding to the temperature sensors 101 to 10N. Set temperature T2 to temperature sensor 1
In the case of individually setting in correspondence with 01 to 10 N, for example, a low setting temperature is set at a position where the temperature tolerance is low, and a high setting temperature is set at a position where the temperature tolerance is high. The set temperature T2 can be determined according to the degree of importance of the position at the temperature.

Here, the clock control of the present invention will be described with reference to the first configuration diagram of the comparator of the clock control device of the present invention of FIG. 7 and the second configuration diagram of the comparator of the clock control device of the present invention of FIG. The configuration of the comparator of the device will be described. FIG. 7 shows a plurality of temperature sensors 101 to 101 with one set temperature T1.
The plurality of detected temperatures T of the 10N temperature state signals 121 to 12N are compared with one set temperature T1.

For example, the control unit 111 is composed of one comparator C and one memory M. The memory M stores the set temperature T1. The comparator C inputs the temperature state signals 121 to 12N of the plurality of temperature sensors 101 to 10N and the signal corresponding to the set temperature T1 from the memory M, and compares the plurality of detected temperatures T with one set temperature T1. Then, the output, the clock switching signal 131, is transmitted to the timing generation unit 114.

In FIG. 8, the set temperatures T1 are plural,
Temperature state signals 121 of the plurality of temperature sensors 101 to 10N
It is intended to compare a plurality of detected temperatures T of up to 12N with a plurality of set temperatures T1 respectively corresponding thereto. In the figure, for example, the control unit 111 is composed of a plurality of comparators C1 to CN and a plurality of memories M1 to MN. Memory M1
A set temperature T1 is set and stored in each of the to MN. It should be noted that all of these set temperatures may be different, or some or all of them may be the same set temperature.

The comparators C1 to CN include a plurality of temperature sensors 1
01-10N temperature state signals 121-12N and memory M
A signal corresponding to the set temperature T1 from 1 to MN is input, a plurality of detected temperatures T and a plurality of set temperatures T1 are compared, and a clock switching signal 131 which is an output thereof is transmitted to the timing generation unit 114. To do. Usually, the plurality of detected temperatures T and the plurality of set temperatures T1 are compared to generate the clock switching signal 131. In order to ensure stable operation of the device, one of them exceeds the set temperature T1. However, if the number of temperature sensors that exceed the set temperature exceeds the preset number, the temperature sensor that has been set according to the importance is given priority. It is also possible to set it as.

Step S8: In this step, the same processing as in step S3 is performed, and the temperature sensor 10
When the detected temperature T of 1 to 10 N becomes equal to or lower than the set temperature T2, the control unit 111 generates the clock switching signal 131. The clock switching signal 131 is the clock signal 13
5 from the low speed clock signal 133 to the basic clock signal 13
It is for switching to 2, and the timing creation unit 1
14 is sent.

Step S9: This step performs the same processing as step S4, and the timing signal 134 generated by the timing generation unit 114 is actually the basic clock signal 132 based on the clock switching signal 131. The timing of switching the low-speed clock signal 133 is taken, and the timing of this switching is monitored in this step, and the basic clock signal 13
2 and the low-speed clock signal 133 are switched, the time when there is no difference in the intervals of the clock signals is measured, and the process of step S10 is performed at that time.

Step S10: In this step, the same processing as in step S4 is performed, and the timing generation section 114 transmits the timing signal 134 to the clock selector section 115, and the basic clock signal 132 and the low-speed clock signal 133 are transmitted. Make a choice. Step S11: The timing signal 134 is generated and input to the clock selector 115 by the step S10, and the low-speed clock signal 133 to the basic clock signal 13 are generated.
Switch to 2.

As a result, the CPU 116 and the controlled circuit 117 are again synchronized by the basic clock signal 132, and the processing at the normal operating speed is performed. After that, the process returns to step S2 again, the detected temperature T is compared with the set temperature T1, the clock signal is selected, and the temperature control is performed. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0059]

As described above in detail, according to the present invention, the CPU control device is provided with a temperature sensor for monitoring the temperature inside the device and a means for switching the clock cycle according to the temperature inside the device. When the temperature rises, the clock signal is switched to a clock signal with a slow cycle to keep the processing speed low to prevent the equipment temperature from rising, and when the temperature drops, a clock signal with a fast clock cycle again. Since the processing is switched to and the processing is continued, continuous operation is guaranteed even if the temperature of the apparatus rises.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock control device of the present invention.

FIG. 2 is a flowchart of the clock control device of the present invention.

FIG. 3 is a temperature hysteresis diagram of a clock signal of the clock control device of the present invention.

FIG. 4 is a switching diagram according to temperature of a clock signal of the clock control device of the present invention.

FIG. 5 is a clock signal diagram selected by a clock switching signal of the clock control device of the present invention.

FIG. 6 is a clock signal diagram selected by a timing signal of the clock control device of the present invention.

FIG. 7 is a first configuration diagram of a comparator of the clock control device of the present invention.

FIG. 8 is a second configuration diagram of a comparator of the clock control device of the present invention.

FIG. 9 is a block diagram of a conventional clock control device.

FIG. 10 is a flowchart of a conventional clock control device.

[Explanation of symbols]

 101-10N Temperature sensor 111 Control part 112 Basic clock creation part 113 Down clock creation part 114 Timing creation part 115 Clock selector part 116 CPU 117 Controlled circuit 121-12N Temperature condition signal 131 Clock switching signal 132 Basic clock signal 133 Low speed clock signal 134 Timing signal 135 Clock signal

Claims (7)

[Claims] 1. A CPU control method for controlling a CPU, comprising: (a) detecting a temperature of a CPU and a device controlled by the CPU to obtain a detected temperature; and (b) comparing the detected temperature with a set temperature. (C) A clock control method for switching a clock signal for synchronizing the operation of the CPU based on the comparison. 2. The clock control method according to claim 1, wherein, when the clock signal is switched, the clock signal is switched to a clock signal having a slow clock cycle when the temperature rises. 3. The clock control method according to claim 1, wherein when the temperature of the clock signal is switched, the clock signal is switched to a clock signal having a faster clock cycle. 4. A CPU control device for controlling a CPU, comprising: (a) a temperature sensor that detects the temperature of the CPU and the device controlled by the CPU; and (b) a clock generation unit that generates clock signals with different cycles. (C) a control unit that compares the output of the temperature sensor with a set value and outputs a clock switching signal; and (d) a clock selector unit that selects and outputs the clock signal according to the clock switching signal. e) A clock control device characterized in that the cycle of the clock is switched according to the detected temperature. 5. The clock control device according to claim 4, wherein the clock signal is selected in the clock selector unit by a timing signal obtained from the clock switching signal. 6. The clock control device according to claim 4, wherein in the selection of the clock signal, when the temperature rises, the clock signal is switched to a clock signal having a slow clock cycle. 7. The clock control device according to claim 4, wherein in the selection of the clock signal, the clock signal is switched to a clock signal having a fast clock cycle when the temperature drops.