JPH06180599A - Computer system - Google Patents

Abstract

PURPOSE:To attain a computer game device accompanying with a voice output device and a picture display device whose image output and a voice output correspond correctly each other by synchronizing the operation of an adaptive differential pulse code converting (ADPCM) decoder with an image output. CONSTITUTION:A horizontal synchronizing signal (32.47kHz) with a constant cycle ratio to a vertical synchronizing signal synchronizing with an image output is used for the operation control clock of an ADPCM decoder. For a data transfer to the ADPCM decoder, the confirmation of the data transfer and a reproducing operation state becomes easy by being allowed to synchronize with the horizontal synchronizing signal. Since the size of a necessary ADPCM data is fixed, the data reproduction of the ADPCM can be easily recognized by a CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device having an image display function and a sound generation function.

[0002]

2. Description of the Related Art Currently, a digital system is predominant as a sound source. In the digital method, all audio signals are obtained as numerical values, and waveforms can be easily prepared by adding, subtracting, multiplying, and dividing. Computers are used because high-speed data processing capability is required to perform waveform synthesis by calculation.

To obtain a sound source, there is a method of generating a waveform by programming to generate a sound, but in order to obtain a sound source with high sound quality, an intended analog sound is often converted into a digital signal.

To digitize a voice signal, a pulse code modulation method (PC
M) is used. PCM is a method for obtaining digital data by sampling an analog signal at regular time intervals, quantizing a measured value, and converting the obtained numerical value into a binary number.

Differential PCM (DPCM) improved from PCM
Is a method in which the amount of data is reduced by taking the difference between the values of adjacent samples and performing quantization. Adaptive difference PCM (ADP
CM) further compresses the data by reducing the sampling pitch when the difference is large and increasing the pitch when the difference is small, thereby minimizing sound quality damage and using a smaller amount of data. It reproduces the sound.

[0006] PCM data is interconverted with ADPCM data having a small data amount by compression / expansion performed by converting scale level vs scale value and converting ADPCM data vs change amount vs level increase / decrease value.

The computer device did not handle voice at the beginning, but with the development of technology, a small-sized programmable sound generator (P
SG) has come to be used. The PSG generates a voice waveform created by performing amplitude change and frequency modulation by calculation from waveform data of a certain period given by control of a central processing unit (CPU). In some cases, noise is created by directly generating a simple waveform. PSG audio output is easy to control, but it is difficult to obtain a free sound.

As a sound source for obtaining a free sound, the ADPCM system which can obtain a high quality sound is adopted.
Based on the amount of data that can be handled by a general computer device, the sampling frequency of the ADPCM decoder of the computer device is around 16 kHz.

Audio data previously written in the form of ADPCM data in the external storage device is read by the CPU, and the ADPCM decoder expands the data by referring to the scale value from the scale level to reproduce the sound.
The ADPCM decoder in the audio generation mechanism has a built-in sync signal generation circuit that produces a transfer rate. Timing of generating a musical sound or a sound effect is controlled by reproducing PCM data and outputting it as a sound in accordance with a transfer rate set by a synchronizing signal generated by a crystal oscillator.

For computer equipment, PSG, ADPCM
In addition to a sound source whose output is controlled by a CPU or the like, an external sound device is connected to obtain a high-quality sound output. For example,
Compact disc (CD) as a storage medium for game software
In the device introduced with, the CD player is directly used as the PCM sound source to obtain high-quality sound.

[0011]

A computer device having a voice generation function and an image display function is intended to provide various information by voice and image. It is required that the user operates at high speed and the information is accurate as long as the users compete for advanced operation technology based on the composite information obtained from the voice and the image. Since the voice and the image are integrated to form complex information, it is desirable that the generation of the voice and the output of the image are exactly the same.

In a conventional computer device equipped with a sound generating device and an image display device, the ADPCM decoder of the sound source output section operates by incorporating an independent synchronizing signal generating circuit. On the other hand, the image display is controlled by the vertical synchronizing signal. When it is desired to match the output of the image and the sound, the CPU receives the signal output from the sound generation device, etc.
Make sure to match the video and audio by checking the operating state of the decoder, for example, the end of the previous data playback or the start of the current data playback, and matching the image output and audio output for each series of data that is continuously played back. ing.

However, even if the operation of image output is started to coincide with the audio output from the ADPCM decoder, there is a small time difference between the audio output and the image output as it progresses to the latter half of the series of data sets that are continuously reproduced. It grows gradually. SUMMARY OF THE INVENTION It is an object of the present invention to obtain a computer device having an audio output device and an image display device in which the operation of the ADPCM decoder is synchronized with the image output, and the image output and the audio output are exactly the same.

[0014]

In order to solve the above problems, according to the present invention, an ADPCM signal which is synchronized with image output and whose timing can be easily confirmed by the CPU of the computer is used. It is used for the sync signal of the decoder. The frequency of the sync signal that determines the transfer cycle of the ADPCM decoder must be an integral multiple of the sampling frequency of the ADPCM decoder.

The sampling frequency of the ADPCM decoder that has been conventionally used in computer devices is 16 kHz.
Considering that it is around z, it is appropriate to use a synchronization signal having a frequency near an integral multiple of 16 kHz from the viewpoint of compatibility. Therefore, the horizontal synchronizing signal of the image display device, which is extremely close to 32 kHz, is used as the synchronizing signal of the ADPCM decoder.

FIG. 16 is an explanatory diagram showing the relationship between the horizontal synchronizing signal and the vertical synchronizing signal. Odd field (ODD) 26
A horizontal synchronization signal (HSYNC) of 31.47 kHz controls scanning of 525 raster lines composed of three lines and 262 even fields (EVEN). The vertical sync signal (VSYNC) controls the field. OD / -EV
Indicates whether the currently displayed field is EVEN or O
It is a signal for identifying whether it is DD.

The image output is normally synchronized with the vertical synchronizing signal (about 59.94 kHz) of the image display device, but naturally the vertical synchronizing signal and the horizontal synchronizing signal of the image display device have a constant cycle ratio and are synchronized. ing. By creating the transfer rate of the ADPCM decoder using the horizontal synchronizing signal of the image display device, the image output and the audio output can easily and accurately match.

[0018]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a block diagram of a computer device according to an embodiment of the present invention. Game software recording medium such as CD-ROM, 32
It is composed of a bit CPU, a control unit mainly for image / audio data transfer control and an interface of each device, an image data expansion / conversion unit, an image data output unit, and an audio data output unit. K for each device
-Has memory such as RAM, M-RAM, R-RAM, V-RAM.

FIG. 2 is a block diagram of an audio data output unit constituting the computer device of the embodiment of the present invention. This audio data output unit incorporates a 6-channel programmable sound generator (PSG), left and right 2-channel ADPCM decoders # 1 and # 2, and an audio data output unit from a compact disc sound source as an external audio device.

The audio data transferred to the ADPCM decoder by the output control unit is stored in the memory (K-RAM in FIG. 1) in the format as shown in FIG. Figure 3
FIG. 3 is an explanatory diagram showing a storage format of ADPCM data in a memory in the embodiment of the present invention. The data are stored in the memory in the order of, read, and transferred. Voice data is 4
It is a bit (of which the sign is 1 bit), and is stored in a 16-bit boundary closed form as shown in the figure.

In the computer device of this embodiment, a horizontal synchronizing signal (15.735 kHz) and a dot clock (5 MHz) for obtaining a display cycle of 1 dot on the screen are used.
Is used to transfer and reproduce ADPCM data. Sampling frequency of ADPCM decoder 31.4
To realize 7 kHz, the dot clock is counted and the midpoint of one cycle of the horizontal synchronizing signal is obtained. A sampling frequency of 31.47 kHz is obtained by alternately using the dot timing of the intermediate point of 341.25 dots corresponding to one cycle of the horizontal synchronizing signal and the timing of the horizontal synchronizing signal. The basic sampling frequency of the ADPCM decoder is 31.47 kHz, and 15.73 kHz, 7.87 kHz, 3.
It is also possible to select a sampling frequency of 93 kHz.

Linear interpolation required when a sampling frequency other than 31.47 kHz is selected will be described with reference to the drawings. FIG. 4 is an explanatory diagram of the relationship between the sampling frequency and the amount of addition at the time of data transfer and linear interpolation, and FIG.
It is explanatory drawing of the linear interpolation performed at the time of selecting the sampling frequency of 87 kHz.

Reference numerals (0), (1), (2), (3) and (4) indicate the order of data transfer, and the box in the figure indicates 1 in every 4 horizontal periods (H).
Indicates that bytes are being transferred. As shown in FIG. 5, when the sampling frequency is 7.87 kHz, the addition amount is 1/4 of the difference between the current data and the previous data to be reproduced next time.

The previous data (0) is reproduced at the fall of HSYNC immediately after the data (1) and (2) are transferred. While (0) is being played, one step (1 /
Addition amount (d (n) − to the previous data (0) every two horizontal periods)
The data obtained by adding d (n-1) / 4 is reproduced during the data reproduction of (0) and (1).

ADPCM of the computer system of this embodiment
ADPCM data expansion performed by the decoder will be described with reference to the drawings. FIG. 6 is a flowchart for compressing PCM data into ADPCM data. FIG. 7 is a flowchart for decompressing ADPCM compressed data into PCM data. AD obtained by compressing PCM data according to the procedure shown in FIG.
The PCM data is decompressed according to the procedure of FIG. 7 while the device is starting up.

At the time of compression and decompression, ADPCM data vs.
The values are converted by referring to the change amount vs level increase / decrease value correspondence table and the scale level vs scale value conversion table.
FIG. 8 shows the ADPCM data vs change amount vs level increase / decrease value correspondence table. FIG. 9 shows a scale level vs. scale value table. In this apparatus, the initial value of the scale value is 16 which is the minimum value, the maximum value is 48, the maximum of the decompressed data is 4095.875, and the minimum is 0.

In the computer device of the embodiment of the present invention,
Among the operations of the ADPCM decoder, the audio volume, sampling frequency, and soft reset are performed by the CPU
It is set by writing to the register in the CM decoder.

The registers inside the ADPCM decoder will be described below. FIG. 10 is an explanatory diagram of a register that specifies an ADPCM decoder operation. DIV1, DI
The sampling frequency is set by 2 bits of V0. Similar to the setting of the ADPCM decoder operation control register in the output control unit, 31.47 kHz when DIV = 0 (hexadecimal), 15.73 kHz when DIV = 1
When z and DIV = 2, the frequency is 7.87 kHz, and when DIV = 3, the frequency is 3.93 kHz.

Interpolation # 1 and interpolation # 2 are ADPC, respectively.
M registers # 1 and # 2 specify execution of linear interpolation required when reproduction is performed at a sampling frequency other than 31.47 kHz. Performs linear interpolation when the bit is set. RSTADPCM # 1 and RSTADPCM #
2 sets the bit when the ADPCM decoder performs a soft reset independent of the output control unit.

FIG. 11 is an explanatory diagram of a register for setting the volume of the sound reproduced by the ADPCM decoder. A
There is a left / right volume control on one channel of the DPCM decoder, and the maximum is 3F (hexadecimal) and 1B to 00 are silent.

The timing of writing data from the CPU when setting the registers shown in FIGS. 10 and 11 will be described. FIG. 12 is an explanatory diagram of the input voltage of each terminal of the audio data output unit that receives a signal from the CPU.
-CS and A0 to A4 are the chip select signal and the write address signal from the CPU, -WR is the write signal, and D7 to D0 are the data input signals through the bus between the CPU and the audio data output unit.

Data is written to the register designated by the chip select signal and the address signal from the CPU through D7 to D0 when the write signal -WR is in the low level write mode. Data is latched every time the write signal -WR recovers from writing and rises to the high-level recovery mode (the timing of the dotted line in the figure), and the data held at this time becomes valid at the trailing edge of -HSYNC. . That is, when data is written twice or more in one horizontal synchronization period, the data written immediately before the fall of -HSYNC is valid.

In this embodiment, the CPU outputs the audio data on the CD-ROM to the SCSI in the output control unit.
Read out to the memory (K-RAM) via the interface. The CPU sets the register for controlling the ADPCM decoder in the output control unit, so that the output control unit controls the transfer of the audio data stored in the K-RAM.

FIG. 13 shows A in the output control unit.
An explanatory view of a register for controlling the DPCM decoder is shown. The ADPCM decoder reproduction mode register of FIG. 13 (1) specifies the sampling frequency and the data transfer start. DIV1 and DIV0 specify the sampling frequency by 2 bits, and when DIV = 0 (hexadecimal), 31.
47 kHz, 15.73 kHz when DIV = 1, D
When IV = 2, it becomes 7.87 kHz, and when DIV = 3, it becomes 3.93 kHz. READEN # 1 and # 2 are registers for designating the reproduction enable of the ADPCM decoders # 1 and # 2, respectively, and start audio data transfer by setting a bit.

The ADPCM data buffer control register of FIG. 13B sets the state of the memory in which the audio data to be transferred to the ADPCM decoders # 1 and # 2 is read. RINGBUF # 1 and # 2 indicate the usage mode of the memory. When the bit is set, the memory becomes a ring buffer, and the read pointer (in the output control unit) starts reading after reading the end address. It becomes an endless memory that continuously reads out addresses, and continuous data transfer is maintained. When the bit is not set, it becomes a normal sequential buffer and is reset when the read pointer reaches the end address.

BUFEND # 1 and BUFEND # 2, when the bit is set, generate an interrupt when the read pointer reaches the end address of the memory. BUFHALF # 1, #
When bit 2 is set, an interrupt occurs when the read pointer reaches the half address of the memory.

The ADPCM start address register of FIG. 13C specifies the start address of memory reading. ADPCM decoder playback enable (RE
When ADEN # 1 and # 2) are set and the operation start of the ADPCM decoder is designated, the address set in this register is loaded into the read pointer, and reading and transfer of audio data are started.

When the memory is set to the ring buffer, the read pointer performs data transfer of the end address, and then the start address of this register is reset, so that the memory functions as the ring buffer.

The ADPCM end address register of FIG. 13 (4) designates the end address of memory reading. When the memory is set to the sequential buffer, the data transfer is stopped after the read pointer transfers the data of the address set here, and ADPC
Reset the ADPCM playback enable (READEN # 1, # 2) bits of the M data buffer control register.

The ADPCM half address register of FIG. 13 (5) generates an interrupt after the data transfer of the address in which the read pointer is set in this register.
This interrupt is for continuously reproducing ADPCM data by monitoring the timing of writing the continuous data after the interrupt.

The ADPCM status register of FIG. 13 (6) indicates the state of ADPCM, and is SOUNDEN.
Bits are set in D # 1 and SOUNDEND # 2 when the read pointer performs data transfer of the end address of the memory, and SOUNDHALF # 1 and SOUNDHALF are set.
The bit of # 2 is set when the read pointer transfers the data of the half address of the memory. This register is used when ADPCM playback enable is set,
When this register is read and the state of ADPCM is confirmed, resetting is performed.

The timing of writing data from the output control unit when setting the register shown in FIG. 13 will be described. FIG. 14 is an explanatory diagram of the input voltage of each terminal of the audio data output unit that receives a signal from the output control unit. -CS0 to -CS1 are
A chip select signal, RH / -L is a select signal for upper / lower bytes of write data, -WRR is a write signal, and SD0 to SD7 are data input signals. -CS
0 / -CS1 input voltage level
The DPCM decoder # 1 / # 2 is switched. RH /
By switching -L, the audio data is transferred in the order of high order and low order. When the data transfer destination designation and the upper / lower designation are completed, the -WRR write signal falls and SD0 to SD0
Data is input to SD7.

In this embodiment, the horizontal sync signal is received by the output control unit (SOUNDCCTRL in FIG. 1) and the ADPCM decoder to synchronize the audio data transfer rate and the reproduction rate with the horizontal sync signal. Figure 1
5 is an explanatory diagram of a horizontal synchronizing signal and a cycle of data transfer and reproduction, and shows an example in which a sampling frequency of 31.47 kHz is selected. The output control unit receives the horizontal synchronizing signal HSYNC1 and sends the write signal -WRR to the ADPCM decoder. At this time, the already transferred data n-1 is being reproduced.

Within one horizontal blanking period, the data n is transferred in the order of the upper 1 byte and the lower 1 byte, and the data is latched until the blanking period ends. Following the next HSYNC2, ADPCM
Reproduces the data n and outputs the sound, and while the data n is being reproduced, the next data n + 1 is transferred upon receiving the HSYNC3. Thus, in the computer device of the present invention,
The audio data reproduction of the ADPCM decoder is accurately synchronized with the horizontal synchronizing signal, so that the image output and the audio output are accurately matched.

[0045]

As described above, according to the computer control device including the sound generating unit and the image display unit of the present invention, the horizontal synchronization in which the cycle ratio is constant with respect to the vertical synchronization signal controlling the image output. By controlling the audio output using the signal, it is possible to accurately match the video and audio.

It is possible to accurately express complex information including video and audio. In the present invention, the horizontal synchronizing signal of the image display unit, which determines the data transfer rate of the ADPCM decoder, can be easily checked by the CPU for the operation status, so whether the audio output is normally performed or not. Can be monitored by the CPU.

Since the reproduction rate of the ADPCM decoder is controlled by using the horizontal synchronizing signal, the size of the audio data used is fixed. Therefore, there is an effect that the size of the necessary audio data can be grasped appropriately and the CPU can easily determine which data is being reproduced by the ADPCM decoder during the operation of the apparatus.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an audio data output unit that constitutes the computer device of the embodiment of the present invention.

FIG. 3 is an ADPCM in a memory according to an embodiment of the present invention.
It is explanatory drawing which shows the storage format of data.

FIG. 4 is an explanatory diagram of a relationship between a sampling frequency and an addition amount at the time of data transfer and linear interpolation.

FIG. 5 is an explanatory diagram of linear interpolation performed when a sampling frequency of 7.87 kHz is selected.

FIG. 6 is a flowchart of compressing PCM data into ADPCM data.

FIG. 7 is a flowchart of decompressing ADPCM data into PCM data.

FIG. 8 is a table corresponding to ADPCM data vs change amount vs level increase / decrease value.

FIG. 9 is a scale level vs. scale value table.

FIG. 10 is an explanatory diagram of a register that specifies an ADPCM decoder operation.

FIG. 11 is an explanatory diagram of a register that sets a volume of audio reproduced by the ADPCM decoder.

FIG. 12 is an explanatory diagram of the input voltage of each terminal of the audio data output unit that receives a signal from the CPU.

FIG. 13 is an explanatory diagram of a register for controlling an ADPCM decoder in the output control unit.

FIG. 14 is an explanatory diagram of an input voltage of each terminal of the audio data output unit that receives a signal from the output control unit.

FIG. 15 is an explanatory diagram of a horizontal sync signal and a cycle of data transfer and reproduction.

FIG. 16 is an explanatory diagram showing a relationship between a horizontal synchronizing signal and a vertical synchronizing signal.

[Procedure amendment]

[Submission date] November 20, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Within one horizontal blanking period, the lower 1 byte and the upper 1 byte
The data n is transferred in the order of the right side and the data is latched until the end of the blanking period. Following the next HSYNC2, ADPCM
Reproduces the data n and outputs the sound, and while the data n is being reproduced, the next data n + 1 is transferred upon receiving the HSYNC3. Thus, in the computer device of the present invention,
The audio data reproduction of the ADPCM decoder is accurately synchronized with the horizontal synchronizing signal, so that the image output and the audio output are accurately matched.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

[Fig. 13]

Claims (1)

[Claims] 1. In a computer device having an image display function and a voice generation function, a data transfer operation performed by a data output control unit to an ADPCM decoder with a built-in voice generation unit and a voice data reproduction operation of the ADPCM decoder. A computer device controlled by a horizontal synchronizing signal for controlling an image display function generated by a clock unit of the computer.