JPH06175924A - Computer device - Google Patents

Abstract

PURPOSE:To improve the processing performance of a processor by increasing the speed of transfer of data between a processor and a memory. CONSTITUTION:In a computer device in which a memory control circuit 2 is connected with a central processor 3, cache memory 4, main memory 5, and peripheral controller 6, an address check circuit 1 is provided. At the time of transferring the data from the peripheral controller 6 to the main memory 5, the invalidation of the cache memory 4 and the rewriting of the content of the cache memory 4 are not operated by the address check circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system for controlling a hierarchical memory, that is, a cache memory.

[0002]

2. Description of the Related Art As the field of use of computer systems has expanded in recent years, there has been a demand for higher performance of computer devices. One of the important technologies to meet this demand is to improve the performance of a central processing unit (hereinafter referred to as a processor) and the performance of a storage device. The storage device generally has the following three hierarchical structures in relation to the cost.

1. It is a small-capacity (several kilobytes to several tens of kilobytes), ultra-high-speed, high-priced memory, and is used as a cache memory. 2. Large capacity (several megabytes to hundreds of megabytes), high speed,
It is a medium priced memory and is used as the main memory.

3. It is an extremely large capacity (several hundred megabytes to several terabytes), medium speed, low price memory, such as a magnetic storage device. Here, the relationship between the cache memory and the main memory will be described with reference to FIG.

FIG. 2 is a diagram showing the relationship between the cache memory and the main memory. A program is stored in a part of the main memory 5 (for example, addresses 0 to 499),
Data is stored in the other part (for example, addresses 500 to 1499). On the other hand, the cache memory 4 is more expensive than the main memory 5 and smaller than the storage capacity of the main memory 5.

Therefore, in the cache memory 4, only part of the content of the main memory (for example, addresses 100 to 999) is copied (copied) to the data section 41 of the cache memory 4. Further, the cache memory 4 stores the value of the address of the main memory corresponding to this content (for example, 100, 1
01, ..., 999) for storing the cache memory, and a cache memory data valid display portion 43 for indicating whether or not the contents of the cache memory 4 are valid corresponding to each address. is doing.

FIG. 7 is a block diagram of a conventional device. Data transfer between the processor 3b, the cache memory 4, and the main memory 5 will be described with reference to FIG.
The state performed via b will be described.

It is assumed that the processor 3b specifies an address (address) to the memory control circuit 2b and requests a processor instruction in the program area or data in the data area. The memory control circuit 2b checks the address part 42 of the cache memory 4, and if there is a designated address and the data valid display part 43 corresponding to the address is valid (0), the memory The control circuit 2b accesses the corresponding contents (data) of the data section 41,
Transfer to the processor 3b.

If the data valid display portion 43 corresponding to the address indicates invalid (if 1),
The memory control circuit 2b accesses the main memory 5 and transfers it to the processor 3b. In anticipation that this data will be used again in the future, the memory control circuit 2b also transfers it to the cache memory 4 and turns off the data valid display section 43 (valid). To

If there is no target information (program or data) in the cache memory 4 (for example, 100
The memory control circuit 2b accesses the main memory 5, transfers it to the processor 3b, and transfers it to the cache memory 4 in anticipation that this data will be used again in the future.

In the case where the data valid display section 43 of the cache memory 4 indicates that it is invalid (if 1), and when the cache memory 4 does not have the target information (program or data). When transferring from the main memory 5 to the cache memory 4, the memory control circuit 2b generally transfers a plurality of data (equal to the maximum cache memory storage capacity) over several consecutive addresses from the transfer address of the main memory 5. ,
The data section 41 and the address section 42 of the cache memory 4 are updated, and the data valid display section 43 is turned off (valid).

When the processor 3b rewrites the contents by designating an address (for example, address 101) to the memory control circuit 2b, at the same time, the corresponding address of the main memory (address 101) is rewritten (store through).
And later, the entire contents of the cache memory (addresses 100 to 99)
There is a system (copyback) in which the address 9) is stored in the main memory 5.

Here, when the peripheral controller 6 makes a memory access via the memory control circuit 2b, the memory control circuit 2b reads from the main memory 5 for reading,
In the case of writing, when the data of the same address exists in the cache memory 4 at the same time as writing in the main memory 5, the corresponding portion of the data valid display section 43 is turned on (1) and individual invalidation is performed ( Invalidation).

As a result, data consistency between the contents of the cache memory 4 and the contents of the main memory 5 can be ensured. In this way, the contents of the cache memory 4 and the contents of the main memory 5 are always consistent with each other.

[0015]

FIG. 6 is a diagram showing access to the same area by the processor and the peripheral control unit.
In the conventional technique, as shown in FIG.
When a reads data from the cache memory 4 and the peripheral control device 6 writes data to the same address area of the main memory 5 (for example, a buffer area for the peripheral device), data from the main memory 5 to the cache memory 4 is read. However, there is a problem that the performance of the processor 3 is deteriorated due to frequent copy invalidation processing and individual invalidation processing (invalidation) of the cache memory 4.

In view of the above point, the present invention has an object to provide a means for improving the performance of a processor when a memory access conflict occurs between the processor and another device.

[0017]

The above-mentioned problems can be solved by an address check circuit configured as follows.

FIG. 1 is a block diagram showing the principle of the present invention. ． In the computer device in which the memory control circuit 2 is connected to the central processing unit 3, the cache memory 4, the main memory 5, and the peripheral control device 6, the address check circuit 1 is provided, and the address check circuit 1 accesses It is composed of an access permission register 10 indicating whether or not, an address comparison circuit 11, a first address register 12, and a second address register 13.

When the peripheral controller 6 starts accessing the main memory 5, the central processing unit 3 turns on the access permission register 10 and sets the start address of the access area in the first address register 12, Is set in the second address register 13, the central processing unit 3 turns off the access permission register 10 at the end of access, and the peripheral control unit 6 sets the first address register when the access permission register 10 is on. Main memory 5 indicated by 12 and the second address register 13
When it is detected by the address comparison circuit 11 that the access area is accessed, the cache memory 4 of the address corresponding to the access is not invalidated.

[0020]. In the above, the start address of the access area is set in the first address register 12, and the end address of the access area is set in the second address register 13.

[0021]. In the above, the start address of the access area is set in the first address register (12),
The don't care address (mask data) of the access area is set in the second address register (13).

[0022]

That is, according to the present invention, while the peripheral controller 6 is accessing a certain address area of the main memory 5, data transfer from the main memory 5 to the cache memory 4 and individual invalidation processing of the cache memory 4 ( By not performing the validation, the processor 3
To improve the performance of.

In response to a read request from the certain address area from the processor 3, the memory control circuit reads data from the main memory 5, transfers the data to the processor 3, and does not transfer data to the cache memory 4. By doing so, the performance of the processor 3 is improved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a diagram showing the state setting of an address check circuit.

As shown in FIG. 3, this embodiment has a bus structure and the buses have a hierarchical structure.
The first-level bus 20 (I-BUS) has a main memory 5a, an address comparison circuit 11a, a first address register 12a, a second address register 13a, a first bus transceiver 22a, and a second bus transceiver 22b.
Are connected.

A second level bus 21a (K-BUS) is connected to the first bus transceiver 22a.
A processor 3a and a cache memory 4a are connected to this K-BUS. Further, another second level bus 21b (C-BUS) is connected to the second bus transceiver 22b. A file control device 6a is connected to the C-BUS, and the file control device 6a controls the reading / writing (R / W) of the device 7.

The memory control circuit 2a includes a processor 3a, a cache memory 4a, an access permission register 1
0a, the address comparison circuit 11a, the first bus transceiver 22a, and the second bus transceiver 22b. The memory control circuit 2a controls the bus transceiver 22a and the bus transceiver 22b so that at most one bus of the second level bus K-BUS or C-BUS can be simultaneously operated at the first level bus 20 (I-bus). BU
It does not conduct with S).

In the device having such a configuration, when the file control device 6a reads data from the device 7 and writes the data in the buffer area of the main memory 5a, when the address check circuit of the present invention is added. Enables high-speed processing as described below.

In other cases, the conventional technique is used. For example, when the file control device 6a reads data from the buffer area of the main memory 5a and writes the data in the device 7, the conventional technique is used.

Prior to the operation of reading data from the device 7 and writing the data into the main memory 5a, the processor 3a sets the bus transceiver 22a in the conductive state and the bus transceiver 22b in the non-conductive state via the memory control circuit 2a for access. While turning on the permission register 10a,
The start address S of the read buffer area and the length L of the area of the device 7 of the main memory 5a are stored in the first address register 12a and the second address register 13a via K-BUS and I-BUS, respectively. , Preset. (See FIG. 4) When the read operation by the file control device 6a is completed, the file control device 6a causes an interrupt to the processor 3a, and the processor 3a causes the memory control circuit 2 to operate.
The access permission register 10a is turned off via a.

Before the data is read from the device 7 by the file controller 6a and the write operation to the main memory 5a is started, the cache memory 4a is instructed by the processor 3a at a position corresponding to the read buffer area, that is,
The data in the area between S and S + L is purged (collective invalidation).

After that, when the file controller 6a writes to the read buffer area designated by the first address register 12a and the second address register 13a, the bus transceiver 2 is passed through the memory control circuit 2a.
2b is turned on, the bus transceiver 22a is turned off, and data transfer (writing) from the device 7 to the main memory 5a is performed. At this time, the write address value of the main memory 5a is taken into the address comparison circuit 11a as a variable V, and this variable is stored in the first address register 12a (start address S of the read buffer area).
, And the value of the second address register 13a (the length L of the read buffer area), that is, if S + L ≧ V ≧ S, the address comparison circuit 11a.
Takes AND (logical product) with the ON data of the access permission register 10a, and sends the result (logical value "1") to the memory control circuit 2a. In response to this result, the memory control circuit 2a prevents the cache memory from performing the invalidation (individual invalidation) operation.

Further, the processor 3a has a memory control circuit 2a.
When the memory is read via the memory, the required data is not in the cache memory 4a (cache miss hit) or the data valid display portion 43 of the cache memory 4a is on (invalid display), and the address is If the value is within the read buffer area, the memory control circuit 2a reads the I-BUS and K from the main memory 5a.
The data is supplied to the processor 3a via the bus so that the data is not copied to the cache memory 4a.

At this time, whether or not the access address value of the processor 3a is within the read buffer area is checked by the address comparison circuit 11a as described above. The check result is sent to the memory control circuit 2c. If the variable V is outside the read buffer area, that is, if V <S or V> S + L, then the memory control circuit 2a operates in the same manner as in the conventional case. Upon receiving the result of 11a (logical value "0"), the cache memory is invalidated (invalidated).

Next, as another case, a case where data is read from the device 7 and written in the main memory 5a will be described. Prior to the write operation, the processor 3a turns on the bus transceiver 22a, turns off the bus transceiver 22b, and turns on the access permission register 10a via the memory control circuit 2a.
The start address of the read buffer area and the end address of the area for the device 7 of the main memory 5a are stored in the first address register 12a and the second address register 13a via K-BUS and I-BUS, respectively.
Set in advance.

Thereafter, the same processing as when the length of the buffer area is set in the second address register 13a is performed. That is, if E ≧ V ≧ S, the memory control circuit 2a validates the cache memory (individual invalidation).
Do not perform any operation and change the main memory 5a to IB
The data is supplied to the processor 3a via the US and K-BUS, and the data is not copied to the cache memory 4a. (Claim 2) Next, a case of don't care will be described as still another case.

FIG. 5 shows effective values in the case of don't care. In FIG. 3, a third address register (not shown) is added, and like the first address register 12a and the second address register 13a, mask data is set via I-BUS.

Then, the output of the third address register and the variable V are subjected to a logical product operation (“AND” operation), and the result is a new variable in the address comparison circuit 11.
The data is input to a and the same processing as above is performed.

Prior to the operation of reading data from the device 7 and writing it to the main memory 5a, the processor 3a makes the bus transceiver 22a conductive and the bus transceiver 22b nonconductive by way of the memory control circuit 2a. The permission register 10a is turned on.

Further, the processor 3a sets the start address of the read buffer area for the device 7 of the main memory 5a to the first address register 12a and the final address of the area via the K-BUS and I-BUS. In the second address register 13a and mask data in a third address register (not shown). Further, the mask data in which only the effective portion is turned on is passed through the K-BUS and I-BUS to the mask register 1
Set to 4.

When data is transferred from the device 7 to the main memory 5a, the write address value of the main memory 5a is fetched as a variable V, and this variable V and the mask data of the mask register or bit data as shown in FIG. Correspondingly, an AND (logical product) operation is performed, and the result is input to the address comparison circuit. In the case of FIG. 5,
Since 28 to 31 bits of the mask register are "1", "1" of 0 to 27 bits of the variable is ignored and 28
Only the value indicated by ~ 31 bits is adopted.

Between the value of the first address register 12a (start address of the read buffer area) and the value of the second address register 13a (final address of the read buffer area), the bit corresponding AND operation is performed. If the output result is included, the address comparison circuit 11a again ANDs (logical product) the ON data of the access permission register 10a.
And the result (logical value “1”) is stored in the memory control circuit 2
Send to a. The memory control circuit 2a receives this result and validates (invalidates) the cache memory.
Disable the action. (Claim 3) On the other hand, if the data read address value from the memory of the processor 3a is outside the read buffer area,
As in the conventional case, the memory control circuit 2a supplies the data from the main memory 5a to the processor 3a via the I-BUS and the K-BUS, and copies the data to the cache memory 4a. Further, when the write address value to the memory of the processor 3a is outside the read buffer area, the memory control circuit 2a writes the data to the cache memory 4a and simultaneously writes the data to the main memory 5a as in the conventional case. (Store-through) or later in a batch with main memory 5a
To write (swap) to.

Although not generally present, when the file controller 6a is writing to the buffer area of the main memory 5a (access permission register 10a is on),
When the processor 3c is also written in the buffer area,
In the case of store-through, the I-BUS is in a competitive state, that is, the C-BUS is in the conductive state with the I-BUS, and the K-BUS is in the non-conductive state by the memory control circuit 2c. Data transfer from the cache memory 4a to the main memory 5a is put on hold.

By the above operation, the cache memory 4a
And the data in the main memory 5a are kept consistent, the invalidation operation is not performed, and the wasteful data transfer from the main memory 5a to the cache memory 4a is not performed.
By supplying the data from the main memory 5a to the processor 3c, it is possible to reduce the deterioration in performance when the operation of the processor 3c is performed only in the cache memory.

[0045]

As is apparent from the above description, according to the present invention, there is an industrial effect of improving the performance of the computer system by reducing the invalidation operation that causes the deterioration of the performance of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention.

[Fig. 2] Relationship between cache memory and main memory

FIG. 3 is a configuration diagram of an embodiment of the present invention.

FIG. 4 State setting of address check circuit

[Figure 5] Effective value for don't care

FIG. 6 Access to the same area of the processor and the peripheral device

FIG. 7 is a conventional device configuration diagram.

[Explanation of symbols]

1 Address check circuit 2, 2a, 2b
Memory control circuit 3, 3a, 3b Processor 4, 4a Cache memory 5, 5a Main memory 6 Peripheral control device 6a File control device 7 Device 10, 10a Access permission register 11, 11a Address comparison circuit 12, 12a First address register 13 , 13a Second address register 14 Third address register 41 Data section of cache memory 42 Address section of cache memory 43 Data valid display section of cache memory

Claims (3)

[Claims] 1. A computer system in which a memory control circuit (2) is connected to a central processing unit (3), a cache memory (4), a main memory (5) and a peripheral control unit (6), respectively. An address check circuit (1) is provided, and the address check circuit (1) includes an access permission register (10) indicating whether access is possible, an address comparison circuit (11), a first address register (12), and When the peripheral control unit (6) starts accessing the main memory (5), the central processing unit (3) turns on the access permission register (10) to access the main memory (5). The start address of the area is set in the first address register (12) and the length of the access area is set in the second address register (13). The central processing unit (3) turns off the access permission register (10), and when the access permission register (10) is on, the peripheral control unit (6) causes the first address register (12) and the second address register ( When it is detected by the address comparison circuit (11) that the access area of the main memory (5) indicated by 13) is accessed, the cache memory (4) of the address corresponding to the access is not individually invalidated. Characteristic computer device. 2. The start address of the access area is set in the first address register (12) according to claim 1,
A computer device characterized by setting a final address of an access area in a second address register (13). 3. The start address of the access area is set in the first address register (12) according to claim 1,
A computer device characterized in that a don't care address of an access area is set in a second address register (13).