JPH06165212A - Integrated circuit for video signal processing - Google Patents
Integrated circuit for video signal processingInfo
- Publication number
- JPH06165212A JPH06165212A JP31674392A JP31674392A JPH06165212A JP H06165212 A JPH06165212 A JP H06165212A JP 31674392 A JP31674392 A JP 31674392A JP 31674392 A JP31674392 A JP 31674392A JP H06165212 A JPH06165212 A JP H06165212A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- digital
- conversion circuit
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Of Color Television Signals (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＮＴＳＣ方式またはＰ
ＡＬ方式あるいはこれらに準拠したテレビジョンに使用
される集積回路に関し、特に、コンポジットビデオ信号
を輝度信号と色信号に分離する集積回路に関する。The present invention relates to the NTSC system or P
The present invention relates to an integrated circuit used in an AL system or a television compliant with these, and more particularly to an integrated circuit for separating a composite video signal into a luminance signal and a chrominance signal.
【０００２】[0002]
【従来の技術】近年、カラーテレビ受像機の各種性能
が、目覚ましい技術革新により大幅に改善されてきてい
る。特に、高画質化のなかでの最大のポイントは、高解
像度化であり、この高解像度化に大きく貢献しているの
がデジタル信号処理技術である。例えば、クリアビジョ
ン（ＩＤＴＶ）と呼ばれるテレビジョンでは、Ｙ／Ｃ分
離、ＹＣ処理、色復調、走査線補間、動き検出などが、
デジタル信号処理によって行われ、これらの集積回路化
が進んでいる。2. Description of the Related Art In recent years, various performances of color television receivers have been greatly improved due to remarkable technological innovation. In particular, the highest point in improving image quality is high resolution, and digital signal processing technology is a major contributor to this high resolution. For example, in a television called clear vision (IDTV), Y / C separation, YC processing, color demodulation, scanning line interpolation, motion detection, etc.
This is performed by digital signal processing, and these integrated circuits are being developed.
【０００３】図２は、従来のＩＤＴＶに用いられる動き
適応型三次元Ｙ／Ｃ分離回路のブロック図である。アナ
ログのコンポジットビデオ信号ＶSは、Ａ／Ｄ変換回路
１において、カラーバースト信号に同期したクロック信
号によって８ビットのデジタル信号に変換される。変換
されたデジタルビデオ信号は、ラインメモリ２及び３を
使用したライン間Ｙ／Ｃ分離回路４によって、デジタル
Ｙ信号とデジタルＣ信号に分離される。更に、変換され
たデジタルビデオ信号は、フレームメモリ５を使用した
フレーム間Ｙ／Ｃ分離回路６によってデジタルＹ信号と
デジタルＣ信号に分離される。ライン間Ｙ／Ｃ分離回路
４の出力とフレーム間Ｙ／Ｃ分離回路６の出力は、切り
換え回路７によって選択され、デジタルＹ信号はＹ信号
用Ｄ／Ａ変換回路８に出力され、デジタルＣ信号はＣ信
号用Ｄ／Ａ変換回路９に出力される。切り換え回路７を
制御する動き検出回路１０は、動画と静止画にそれぞれ
適したライン間Ｙ／Ｃ分離回路４とフレーム間Ｙ／Ｃ分
離回路６を選択するための回路であり、画素毎に動きを
検出しそれに応じたデジタルＹ信号とデジタルＣ信号を
選択する。検出の方法は、基本的には、輝度信号の低域
成分の１フレーム間差信号と色信号の２フレーム間差信
号をもとに動きを検出して、更にその動きの信号のノイ
ズ成分を除去したり、画像のエッジ付近でのジッタ成分
による動きを抑圧することによって最適な動き信号を作
り出す。FIG. 2 is a block diagram of a motion adaptive type three-dimensional Y / C separation circuit used in a conventional IDTV. The analog composite video signal V S is converted into an 8-bit digital signal in the A / D conversion circuit 1 by a clock signal synchronized with the color burst signal. The converted digital video signal is separated into a digital Y signal and a digital C signal by the inter-line Y / C separation circuit 4 using the line memories 2 and 3. Further, the converted digital video signal is separated into a digital Y signal and a digital C signal by the inter-frame Y / C separation circuit 6 using the frame memory 5. The output of the inter-line Y / C separation circuit 4 and the output of the inter-frame Y / C separation circuit 6 are selected by the switching circuit 7, the digital Y signal is output to the Y signal D / A conversion circuit 8, and the digital C signal is output. Is output to the C signal D / A conversion circuit 9. The motion detection circuit 10 that controls the switching circuit 7 is a circuit for selecting the line-to-line Y / C separation circuit 4 and the frame-to-frame Y / C separation circuit 6 that are suitable for a moving image and a still image, respectively. Is detected and a digital Y signal and a digital C signal corresponding thereto are selected. Basically, the detection method is to detect the motion based on the one-frame difference signal of the low frequency component of the luminance signal and the two-frame difference signal of the chrominance signal, and further to detect the noise component of the motion signal. An optimal motion signal is created by removing or suppressing motion due to a jitter component near the edge of the image.
【０００４】このような動き適応型三次元Ｙ／Ｃ分離回
路を採用することによって、ドット妨害（色信号が輝度
信号に混入し、上下の色の境界に点状の妨害が発生する
現象）やクロスカラー（縞状の色がつく現象）を防止す
ることができる。従来は、ライン間Ｙ／Ｃ分離回路４、
フレーム間Ｙ／Ｃ分離回路６、切り換え回路７が１つの
集積回路、動き検出回路１０が１つの集積回路に集積さ
れ、ラインメモリ２及び３、フレームメモリ６、Ａ／Ｄ
変換回路１、及び、Ｄ／Ａ変換回路８及び９が外部接続
された構成であった。最近では、集積回路の微細化プロ
セスの進展により、集積度が向上し、動き適応型三次元
Ｙ／Ｃ分離回路のビデオ信号処理をする集積回路内にＡ
／Ｄ変換回路１やＤ／Ａ変換回路８及び９を内蔵するこ
とが可能になった。By adopting such a motion-adaptive three-dimensional Y / C separation circuit, dot interference (a phenomenon in which a color signal is mixed in a luminance signal and dot-like interference occurs at the boundary between upper and lower colors) and It is possible to prevent cross color (a phenomenon in which a striped color is formed). Conventionally, the line-to-line Y / C separation circuit 4,
The inter-frame Y / C separation circuit 6, the switching circuit 7 are integrated in one integrated circuit, and the motion detection circuit 10 is integrated in one integrated circuit. The line memories 2 and 3, the frame memory 6, A / D
The configuration is such that the conversion circuit 1 and the D / A conversion circuits 8 and 9 are externally connected. Recently, due to the progress of miniaturization process of integrated circuits, the degree of integration has been improved, and the integrated circuit for video signal processing of the motion adaptive type three-dimensional Y / C separation circuit has been developed.
It has become possible to incorporate the / D conversion circuit 1 and the D / A conversion circuits 8 and 9.
【０００５】[0005]
【発明が解決しようとする課題】しかし、同一のビデオ
信号処理用集積回路内に複数のＤ／Ａ変換回路を内蔵し
た場合、互いの信号間の干渉が問題となった。特に、分
離されたＹ信号とＣ信号をＤ／Ａ変換した場合、Ｃ信号
は特定周波数の色搬送波上で変調された信号であるた
め、これがＹ信号に干渉すると、水平同期信号などの様
々な成分と結合してビートを発生し、これがテレビ画面
上に周期的な縞模様状の妨害として現れた。このような
干渉によるビート妨害を抑えるためには、集積回路のパ
ターン設計において細心の注意と経験を要する。また、
設計段階で干渉を防ぐ合理的な手法が確率されていない
ため、集積回路が完成した後、その特性評価の結果によ
ってパターン・レイアウトの調整を要するので、非常に
繁雑であった。However, when a plurality of D / A conversion circuits are built in the same integrated circuit for video signal processing, interference between signals becomes a problem. Particularly, when the separated Y signal and C signal are D / A converted, since the C signal is a signal modulated on a color carrier of a specific frequency, if the C signal interferes with the Y signal, various signals such as a horizontal synchronizing signal are generated. It combined with the components to produce beats, which appeared as periodic striped disturbances on the television screen. In order to suppress the beat interference due to such interference, careful attention and experience are required in the pattern design of the integrated circuit. Also,
Since no rational method for preventing interference has been established in the design stage, the pattern layout needs to be adjusted according to the result of the characterization of the integrated circuit, which is very complicated.
【０００６】[0006]
【課題を解決するための手段】本発明は、上述した点に
鑑みて創作されたものであり、Ｙ信号用Ｄ／Ａ変換回路
とＣ信号用Ｄ／Ａ変換回路を各々デジタルデータに対応
して重み付けされた電流源を備えた電流加算型Ｄ／Ａ変
換回路で構成し、Ｃ信号用Ｄ／Ａ変換回路の最小デジタ
ルビットに対応する電流源の電流値がＹ信号用Ｄ／Ａ変
換回路の最小デジタルビットに対応する電流源の電流値
より小さく設定されることを特徴とする。The present invention was created in view of the above-mentioned points, and the Y signal D / A conversion circuit and the C signal D / A conversion circuit respectively correspond to digital data. Current adding type D / A conversion circuit having a current source weighted by a variable current source, and the current value of the current source corresponding to the minimum digital bit of the C signal D / A conversion circuit is the Y signal D / A conversion circuit. Is set to be smaller than the current value of the current source corresponding to the minimum digital bit of.
【０００７】[0007]
【作用】Ｃ信号用Ｄ／Ａ変換回路の最小デジタルビット
に対応する電流源の電流値がＹ信号用Ｄ／Ａ変換回路の
最小デジタルビットに対応する電流源の電流値より小さ
くなるために、Ｃ信号の電流全体が圧縮される。従っ
て、Ｃ信号用Ｄ／Ａ変換回路に流れる電流がＹ信号用Ｄ
／Ａ変換回路に漏れる総量を少なくすることができるの
で、ビート妨害が減少する。Since the current value of the current source corresponding to the minimum digital bit of the C signal D / A conversion circuit is smaller than the current value of the current source corresponding to the minimum digital bit of the Y signal D / A conversion circuit, The entire current of the C signal is compressed. Therefore, the current flowing through the D / A conversion circuit for C signals is D for Y signals.
Since the total amount leaked to the A / A conversion circuit can be reduced, beat interference is reduced.
【０００８】[0008]
【実施例】図１は、本発明の実施例を示すブロック図で
あり、動き適応型三次元Ｙ／Ｃ分離回路である。図にお
いて、集積回路１１には、アナログのコンポジットビデ
オ信号ＶSを８ビットのデジタル信号に変換するＡ／Ｄ
変換回路１２と、変換された８ビットのデジタル信号を
処理し、分離されたデジタルＹ信号とデジタルＣ信号を
出力するデジタル信号処理回路１３と、デジタルＹ信号
をアナログのＹ信号に変換するＹ信号用Ｄ／Ａ変換回路
１４と、デジタルＣ信号をアナログのＣ信号に変換する
Ｃ信号用Ｄ／Ａ変換回路１５が集積化される。ここで、
デジタル信号処理回路１３は、図２に示されたライン間
Ｙ／Ｃ分離回路４とフレーム間Ｙ／Ｃ分離回路６と切り
換え回路７を少なくとも含むものであり、場合によって
は動き検出回路１０をも含む。このデジタル信号処理回
路１３にはラインメモリ１６及び１７とフレームメモリ
１８が外部接続される。FIG. 1 is a block diagram showing an embodiment of the present invention, which is a motion adaptive type three-dimensional Y / C separation circuit. In the figure, an integrated circuit 11 has an A / D for converting an analog composite video signal V S into an 8-bit digital signal.
A conversion circuit 12, a digital signal processing circuit 13 that processes the converted 8-bit digital signal and outputs a separated digital Y signal and digital C signal, and a Y signal that converts the digital Y signal into an analog Y signal. The D / A conversion circuit 14 for C and the D / A conversion circuit 15 for C signal for converting a digital C signal into an analog C signal are integrated. here,
The digital signal processing circuit 13 includes at least the inter-line Y / C separation circuit 4, the inter-frame Y / C separation circuit 6 and the switching circuit 7 shown in FIG. 2, and may also include the motion detection circuit 10 in some cases. Including. Line memories 16 and 17 and a frame memory 18 are externally connected to the digital signal processing circuit 13.
【０００９】Ｙ信号用Ｄ／Ａ変換回路１４は、８ビット
のデジタル信号に応じて重み付けされた電流源ＳY1〜Ｓ
Y8と、スイッチＳＷY1〜ＳＷY8と、印加されたデジタル
Ｙ信号に基づいてスイッチＳＷY1〜ＳＷY8のオン及びオ
フを制御する制御回路１４−１とから構成され、スイッ
チＳＷY1〜ＳＷY8の一端が共通に接続され、アナログＹ
信号出力となる。The Y signal D / A conversion circuit 14 includes current sources S Y1 to S Y weighted according to an 8-bit digital signal.
And Y8, the switch SW Y1 to SW Y8, and a control circuit 14-1 which controls on and off of the switch SW Y1 to SW Y8 based on the applied digital Y signal, the switch SW Y1 to SW Y8 One end is connected in common, analog Y
Signal output.
【００１０】一方、Ｃ信号用Ｄ／Ａ変換回路１５もＹ信
号用Ｄ／Ａ変換回路１４と同様の構成であり、８ビット
のデジタル信号に応じて重み付けされた電流源ＳC1〜Ｓ
C8と、スイッチＳＷC1〜ＳＷC8と、印加されたデジタル
Ｃ信号に基づいてスイッチＳＷC1〜ＳＷC8のオン及びオ
フを制御する制御回路１５−１から構成され、スイッチ
ＳＷC1〜ＳＷC8の一端が共通に接続され、アナログＣ信
号出力となる。On the other hand, the C signal D / A conversion circuit 15 has the same configuration as the Y signal D / A conversion circuit 14, and the current sources S C1 to S C are weighted according to the 8-bit digital signal.
And C8, and switches SW C1 to SW C8, and a control circuit 15-1 to control the on and off switch SW C1 to SW C8 based on the applied digital C signal, one end of the switch SW C1 to SW C8 Are commonly connected to provide an analog C signal output.
【００１１】ここで、Ｃ信号用Ｄ／Ａ変換回路１５の最
小ビットに対応する電流源ＳC1の電流値ＩC1は、Ｙ信号
用Ｄ／Ａ変換回路１４の最小ビットに対応する電流源Ｓ
Y1の電流値ＩY1より小さく設定される。例えば、ＩC1の
電流をＩY1の電流の１／２に設定すると、全体的にＣ信
号用Ｄ／Ａ変換回路１５に流れる電流は、Ｙ信号用Ｄ／
Ａ変換回路１４に流れる電流の１／２になる。従って、
Ｃ信号用Ｄ／Ａ変換回路１５に流れる電流がＹ信号用Ｄ
／Ａ変換回路１４に漏れる量を少なくすることができ
る。Here, the current value I C1 of the current source S C1 corresponding to the minimum bit of the C signal D / A conversion circuit 15 is the current value S C1 corresponding to the minimum bit of the Y signal D / A conversion circuit 14.
Y1 smaller than the current value I Y1 of the set. For example, when the current of I C1 is set to 1/2 of the current of I Y1 , the current flowing through the C signal D / A conversion circuit 15 as a whole is Y signal D / A.
It becomes half of the current flowing through the A conversion circuit 14. Therefore,
The current flowing through the D / A conversion circuit 15 for C signals is D for Y signals.
The amount leaked to the / A conversion circuit 14 can be reduced.
【００１２】また、Ｃ信号は、Ｙ信号に比べて最高周波
数帯域が低いため、Ｄ／Ａ変換の最小単位電流を減少さ
せてもＣ信号用Ｄ／Ａ変換回路１５の動作帯域上の影響
は少ない。一方、Ｙ信号は帯域が広いため、Ｃ信号用Ｄ
／Ａ変換回路１５への妨害は目立たない。さらに、集積
回路上においてＹ信号用Ｄ／Ａ変換回路１４とＣ信号用
Ｄ／Ａ変換回路１５の配置を離間し、パター設計上の対
策も施すことにより、本発明の効果を有効に生かすこと
ができる。Further, since the C signal has a lower maximum frequency band than the Y signal, even if the minimum unit current of the D / A conversion is reduced, the influence on the operating band of the C signal D / A conversion circuit 15 is not affected. Few. On the other hand, since the Y signal has a wide band, D for C signal is used.
The disturbance to the / A conversion circuit 15 is inconspicuous. Furthermore, the effect of the present invention is effectively utilized by separating the arrangement of the D / A conversion circuit 14 for Y signal and the D / A conversion circuit 15 for C signal on the integrated circuit and taking measures for pattern design. You can
【００１３】[0013]
【発明の効果】上述の如く、本発明によれば、Ｙ信号用
Ｄ／Ａ変換回路１４とＣ信号用Ｄ／Ａ変換回路１５を内
蔵するビデオ信号処理用集積回路において、Ｄ／Ａ変換
回路間のビート妨害を低減できるため、より高画質を実
現できるものである。さらに、集積回路のパターン設計
が容易になり、集積回路完成までの時間が短縮される利
点を有している。As described above, according to the present invention, in the video signal processing integrated circuit incorporating the Y signal D / A conversion circuit 14 and the C signal D / A conversion circuit 15, the D / A conversion circuit is provided. Since the beat interference between them can be reduced, higher image quality can be realized. Further, there is an advantage that the pattern design of the integrated circuit is facilitated and the time required to complete the integrated circuit is shortened.
【図１】本発明の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】従来のビデオ信号処理回路を示すブロック図で
ある。FIG. 2 is a block diagram showing a conventional video signal processing circuit.
１１ 集積回路 １２ Ａ／Ｄ変換回路 １３ デジタル信号処理回路 １４ Ｙ信号用Ｄ／Ａ変換回路 １５ Ｃ信号用Ｄ／Ａ変換回路 １６、１７ ラインメモリ １８ フレームメモリ 11 integrated circuit 12 A / D conversion circuit 13 digital signal processing circuit 14 Y signal D / A conversion circuit 15 C signal D / A conversion circuit 16, 17 line memory 18 frame memory
Claims (1)
続されたラインメモリを用いて輝度信号Ｙと色信号Ｃを
分離するライン間Ｙ／Ｃ分離回路、及び／又は、フレー
ムメモリを用いて輝度信号Ｙと色信号Ｃを分離するフレ
ーム間Ｙ／Ｃ分離回路と、前記ライン間Ｙ／Ｃ分離回路
及び又はフレーム間Ｙ／Ｃ分離回路から出力されるデジ
タルＹ信号とデジタルＣ信号を各々アナログＹ信号とア
ナログＣ信号に変換するＹ信号用Ｄ／Ａ変換回路及びＣ
信号用Ｄ／Ａ変換回路が同一集積回路上に集積されたビ
デオ信号処理用集積回路において、前記Ｙ信号用Ｄ／Ａ
変換回路とＣ信号用Ｄ／Ａ変換回路は、各々デジタルデ
ータに対応して重み付けされた電流源を備えた電流加算
型Ｄ／Ａ変換回路で構成され、前記Ｃ信号用Ｄ／Ａ変換
回路の最小デジタルビットに対応する電流源の電流値
は、前記Ｙ信号用Ｄ／Ａ変換回路の最小デジタルビット
に対応する電流源の電流値より小さく設定されることを
特徴とするビデオ信号処理用集積回路。1. A line-to-line Y / C separation circuit for separating a luminance signal Y and a color signal C from a digitally converted video signal using an externally connected line memory, and / or a luminance signal to a frame memory. An inter-frame Y / C separation circuit that separates Y and the color signal C, and a digital Y signal and a digital C signal output from the inter-line Y / C separation circuit and / or the inter-frame Y / C separation circuit, respectively, are analog Y signals. And Y signal D / A conversion circuit for converting into analog C signal and C
In a video signal processing integrated circuit in which a signal D / A conversion circuit is integrated on the same integrated circuit, the Y signal D / A
The conversion circuit and the C signal D / A conversion circuit are configured by current addition type D / A conversion circuits each having a current source weighted corresponding to digital data. The current value of the current source corresponding to the minimum digital bit is set to be smaller than the current value of the current source corresponding to the minimum digital bit of the Y signal D / A conversion circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31674392A JPH06165212A (en) | 1992-11-26 | 1992-11-26 | Integrated circuit for video signal processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31674392A JPH06165212A (en) | 1992-11-26 | 1992-11-26 | Integrated circuit for video signal processing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06165212A true JPH06165212A (en) | 1994-06-10 |
Family
ID=18080414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31674392A Pending JPH06165212A (en) | 1992-11-26 | 1992-11-26 | Integrated circuit for video signal processing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06165212A (en) |
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| US11860515B2 (en) | 2019-11-25 | 2024-01-02 | Corephotonics Ltd. | Folded zoom camera module with adaptive aperture |
| US11914117B2 (en) | 2020-07-31 | 2024-02-27 | Corephotonics Ltd. | Folded macro-tele camera lens designs including six lenses of ++−+−+ or +−++−+, seven lenses of ++−++−+, or eight lenses of ++−++−++ refractive powers |
| US11930263B2 (en) | 2021-01-25 | 2024-03-12 | Corephotonics Ltd. | Slim pop-out wide camera lenses |
| US11947247B2 (en) | 2020-12-01 | 2024-04-02 | Corephotonics Ltd. | Folded camera with continuously adaptive zoom factor |
| US11962901B2 (en) | 2020-05-30 | 2024-04-16 | Corephotonics Ltd. | Systems and methods for obtaining a super macro image |
| US11966147B2 (en) | 2020-09-18 | 2024-04-23 | Corephotonics Ltd. | Pop-out zoom camera |
| US11985407B2 (en) | 2021-11-02 | 2024-05-14 | Corephotonics Ltd. | Compact double folded tele cameras including four lenses of +−+−, +−++; OR +−−+; or six lenses of +−+−+− or +−+−−− refractive powers |
-
1992
- 1992-11-26 JP JP31674392A patent/JPH06165212A/en active Pending
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| US11838635B2 (en) | 2013-06-13 | 2023-12-05 | Corephotonics Ltd. | Dual aperture zoom digital camera |
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| US10904444B2 (en) | 2013-06-13 | 2021-01-26 | Corephotonics Ltd. | Dual aperture zoom digital camera |
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| US11953659B2 (en) | 2013-07-04 | 2024-04-09 | Corephotonics Ltd. | Miniature telephoto lens assembly |
| US10795134B2 (en) | 2013-07-04 | 2020-10-06 | Corephotonics Ltd. | Miniature telephoto lens assembly |
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| US11543633B2 (en) | 2014-08-10 | 2023-01-03 | Corephotonics Ltd. | Zoom dual-aperture camera with folded lens |
| US11982796B2 (en) | 2014-08-10 | 2024-05-14 | Corephotonics Ltd. | Zoom dual-aperture camera with folded lens |
| US10670827B2 (en) | 2017-02-23 | 2020-06-02 | Corephotonics Ltd. | Folded camera lens designs |
| US11668894B2 (en) | 2017-02-23 | 2023-06-06 | Corephotonics Ltd. | Folded camera lens designs |
| US10948696B2 (en) | 2017-07-23 | 2021-03-16 | Corephotonics Ltd. | Compact folded lenses with large apertures |
| US11477386B2 (en) | 2019-01-03 | 2022-10-18 | Corephotonics Ltd. | Multi-aperture cameras with at least one two state zoom camera |
| US11611706B2 (en) | 2019-01-03 | 2023-03-21 | Corephotonics Ltd. | Multi-aperture cameras with at least one two state zoom camera |
| US11668910B2 (en) | 2019-08-21 | 2023-06-06 | Corephotonics Ltd. | Low total track length for large sensor format including seven lenses of +−+−++− refractive powers |
| US11860515B2 (en) | 2019-11-25 | 2024-01-02 | Corephotonics Ltd. | Folded zoom camera module with adaptive aperture |
| US11962901B2 (en) | 2020-05-30 | 2024-04-16 | Corephotonics Ltd. | Systems and methods for obtaining a super macro image |
| US11914117B2 (en) | 2020-07-31 | 2024-02-27 | Corephotonics Ltd. | Folded macro-tele camera lens designs including six lenses of ++−+−+ or +−++−+, seven lenses of ++−++−+, or eight lenses of ++−++−++ refractive powers |
| US11966147B2 (en) | 2020-09-18 | 2024-04-23 | Corephotonics Ltd. | Pop-out zoom camera |
| US11947247B2 (en) | 2020-12-01 | 2024-04-02 | Corephotonics Ltd. | Folded camera with continuously adaptive zoom factor |
| US11930263B2 (en) | 2021-01-25 | 2024-03-12 | Corephotonics Ltd. | Slim pop-out wide camera lenses |
| US11985407B2 (en) | 2021-11-02 | 2024-05-14 | Corephotonics Ltd. | Compact double folded tele cameras including four lenses of +−+−, +−++; OR +−−+; or six lenses of +−+−+− or +−+−−− refractive powers |
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