JPH06164350A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain the semiconductor integrated circuit device which never becomes abnormal when powered ON or OFF. CONSTITUTION:An abnormal voltage detecting circuit 20 which is a series connection body of a diode 21 and a resistance element 22 is installed between the power terminal 81 and 1st diode 65 in the semiconductor circuit 11 that the semiconductor integrated circuit device 10 is equipped with. The output line 23 led out of the connection point 24 between the abnormal voltage detecting circuit 20 and 1st diode 65 is connected to an input terminal 53a for inputting the reset output 69 from a reset circuit 68 provided to an internal circuit 63. A capacitor element 25 is interposed between the connection point 24 and a ground terminal 82. When the semiconductor integrated circuit device 10 is powered OFF and a High-level signal is inputted to a signal input terminal 83 from outside, the voltage developed at the connection point 24 is utilized to reset the internal circuit 63, and then no signal is outputted from the output terminal 63b of the internal circuit 63.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device provided with a reset circuit which detects a value of a power supply voltage and puts the semiconductor circuit in a reset state when the power supply voltage falls below a set value.

[0002]

2. Description of the Related Art As an example of a semiconductor integrated circuit device equipped with a reset circuit that detects the value of a power supply voltage and puts the semiconductor circuit in a reset state when the power supply voltage falls below a set value,
The one applied to a controller / driver for a CD is known. FIG. 4 shows a conventional semiconductor integrated circuit device as an LC
FIG. 5 is a block circuit diagram of an LCD device applied to a D controller / driver. FIG. 5 is a circuit diagram of a main part of a semiconductor circuit corresponding to one input of the semiconductor integrated circuit device shown in FIG.
FIG. 6 is a circuit diagram of a main part of the semiconductor integrated circuit device shown in FIG.

In FIGS. 4 to 6, reference numeral 50 denotes the LCD 7.
0 is a master CPU that is also a semiconductor integrated circuit device that outputs a plurality of output signals 51 such as display data to be displayed, and 60 is an output signal 5 received from the master CPU 50.
It is an LCD controller driver that is also a slave CPU that converts 1 into a driving data signal 64 for the LCD 70 and then outputs it to the LCD 70, and is also a semiconductor integrated circuit device.

Reference numeral 81 is a power supply terminal for supplying a power supply voltage to each of the master CPU 50 and the LCD controller / driver 60, and 82 is a ground terminal corresponding to the power supply terminal 81. LCD controller driver 60
Is a semiconductor circuit that performs conversion processing corresponding to each single output signal of the plurality of output signals 51 (51a, 51n), and an individual driver 61 (6) for each output signal 51.
1a, to 61n), and each individual driver 61 has a power supply terminal 81, a ground terminal 82, and
A signal input terminal 83 for receiving an output signal 51 from the master CPU 50 is provided, the output signal 51 is buffered by a CMOS inverter 62 that is a buffer amplifier circuit, and then input to an internal circuit 63.
The data is converted into data suitable for driving 70, and output as a driving data signal 64 (64a, to 64n) from the output terminal 63b (63ba, to 63bn).
The CMOS inverter 62 includes a P-MOSFET 62a connected to the power supply terminal 81 side and an N-MOSFET 62b connected to the ground terminal 82 side.
Gates of 2a and 62b are connected to each other to form an input terminal 62c of a CMOS inverter 62, and an output signal 51 is input. Drain of P-MOSFET 62a and N-MOS
The drains of the FETs 62b are connected to each other to form the output terminal 62d of the CMOS inverter 62, and output the buffered output signal 51 'of the master CPU 50 to the internal circuit 63. The internal circuit 63 has an input terminal 63a for receiving a reset output (Vr) 69 output from a reset circuit 68 described later.

Reference numeral 65 is a first diode inserted between the power supply terminal 81 and the signal input terminal 83 via the resistance element 67 with its cathode connected to the power supply terminal 81 side, and 66 is a resistance. The second diode is inserted between the signal input terminal 83 and the ground terminal 82 via the element 67 with its cathode connected to the signal input terminal 83 via the resistance element 67. When the terminals come into contact with the terminals 81, 82, 83 of the LCD controller / driver 60, the electrostatic charge from the charged body is transferred to the diode 6
Discharging through 5, 66 protects the LCD controller / driver 60 from electrostatic damage, and 67 suppresses an excessive current value due to electrostatic charge discharged through the diodes 65, 66. Is a resistance element.

The LCD controller / driver 60, together with the plurality of individual drivers 61, detects the value of the power supply voltage, and when the power supply voltage falls below the set value, the individual driver 61.
A reset circuit 68 is provided for outputting a reset output (Vr) 69 for resetting each of the individual drivers 61 [61a to 61n]. The reset circuit 68 is
Power supply terminal 81, ground terminal 82, and power supply voltage (Vs) applied between power supply terminal 81 and ground terminal 82
, A power supply voltage value determination circuit 68a for determining whether or not the value of is greater than a preset predetermined value.
And a CMOS inverter 62 for buffering the output signal 68b of the power supply voltage value determination circuit 68a. As shown in FIG. 7, the power supply voltage determination circuit 68a has a set value (Vo) slightly lower than a predetermined power supply voltage value (Vs), and whether the power supply voltage does not hinder the operation of the individual driver 61. In the case where the power supply voltage value (Vs) is lower than the set value (Vo) and therefore the operation of the internal circuit 63 included in the individual driver 61 is disturbed, A reset signal 68b for resetting the operation is output.

The reset signal 68b is input to the CMOS inverter 62 from the input end 62c, buffered by the CMOS inverter 62, and then output as the reset output (Vr) 69 from the output end 62d, and input to all the internal circuits 63. It is supplied to the terminals 63a (63aa to 63an). When the power supply voltage value (Vs) is lower than the set value (Vo), the reset output (Vr) 69 becomes a high level output (hereinafter abbreviated as “H” output), and the power supply voltage value (Vs) becomes. When it is higher than the set value (Vo), the reset output (Vr) 69 is a Low level output (hereinafter, “L”).
Abbreviated as output. ). Upon receiving the reset output (Vr) 69 of "H" output, the internal circuit 63 enters the reset state and does not output any output to the LCD 70. If the reset output (Vr) 69 is the “L” output,
The internal circuit 63 enters a normal operation state in which it performs a desired operation, and outputs a drive data signal 64 corresponding to the output signal 51 output from the master CPU 50 to the LCD 70. Even when the power supply voltage value (Vs) is extremely low and equal to or less than the threshold value (Vth) of the power supply voltage value determination circuit 68a at the initial stage of power-on or at the end of power-off, the reset output (Vr) 69 is "L". It will be output,
In this case, the power supply voltage value (Vs) is extremely low,
Since the internal circuit 63 does not enter the operating state, no problem occurs.

LC as a conventional semiconductor integrated circuit device
Since the D controller / driver 60 has the above-described configuration, the internal circuit 63 is reset when the power source voltage is low, such as when the power source voltage is turned on or off, so that the LCD at the low power source voltage is reset. The controller controller / driver 60 is prevented from malfunctioning, and the LCD 70 can be prevented from displaying an abnormal display.

[0009]

In the above-described semiconductor integrated circuit device according to the prior art, when the power is turned on or off to all the semiconductor integrated circuit devices forming the system at the same time, the system is used. Can prevent the occurrence of malfunction, but because of the system configuration requirement, for example, in a system in which the power supply system of the master CPU 50 and the LCD controller / driver 60 are separated, the power is turned on or off. The following problems occur.

That is, when the power of the master CPU 50 is turned on, but the power of the LCD controller driver 60 is shut off, a problem occurs. When the output signal 51 of the master CPU 50 is the “H” output, the “H” output voltage input to the LCD controller driver 60 from the signal input terminal 83 is passed through the resistance element 67 and the first diode 65 to the LCD controller. -Applied to the power line of the driver 60. The value of the voltage applied to the power supply line from the “H” output of the output signal 51 drops in order to pass through the resistance element 67 and the first diode 65 on the way, so that, for example, the power supply of the master CPU 50. When the voltage value is 5 [V], 1 to
It becomes 3 [V].

Even in such a case, the internal circuit 63 operates when the voltage value applied from the "H" output of the output signal 51 to the power supply line exceeds the set value (Vo) of the reset circuit 68. It becomes a state. However, the voltage value applied to the power supply line is the normal power supply voltage value (V
Since the value is lower than s) and is a halfway value, the internal circuit 6
The operation of No. 3 becomes unstable and the abnormal driving data signal 64 that does not correspond to the output signal 51 is sent to the LCD 70, so that the LCD 70 may perform an abnormal display. Further, when the LCD controller / driver 60 is powered on in such a state, a latch-up phenomenon is induced in the semiconductor element in the internal circuit 63 which is operating with a halfway voltage value, An accident may occur in which the semiconductor element and hence the internal circuit 63 are permanently damaged.

The present invention has been made in view of the above-mentioned problems of the prior art, and its object is also to be used in a system constituted by a plurality of semiconductor integrated circuit devices whose power supply systems are separated. An object of the present invention is to provide a semiconductor integrated circuit device in which an abnormal state does not occur when power is turned on or off.

[0013]

SUMMARY OF THE INVENTION In the present invention, the above-mentioned objects are: 1) a reset circuit and a semiconductor circuit, wherein the reset circuit has a power supply terminal for receiving a power supply voltage, a ground terminal, and the power supply terminal. A power supply voltage value determination circuit connected between the ground terminals is provided.
Detecting a value of a power supply voltage and outputting a reset output to the semiconductor circuit, the reset output bringing the semiconductor circuit into a reset state when the power supply voltage falls below a preset value. A power supply terminal for receiving a voltage, a signal input terminal for receiving a signal input voltage, a ground terminal for each of the power supply voltage and the signal input voltage, a cathode inserted between the power supply terminal and the signal input terminal, and a cathode for the power supply. A first diode connected to the terminal side, a second diode inserted between the signal input terminal and the ground terminal and having its cathode connected to the signal input terminal, and protection from electrostatic damage by these diodes And an internal circuit having an input terminal for receiving a reset output from the reset circuit, When the reset output is received from the semiconductor integrated circuit, the internal circuit enters a reset state, and when the reset output that should bring the internal circuit into the reset state is not received from the reset circuit, the semiconductor integrated circuit performs a normal operation according to the signal input voltage. In the device, the semiconductor circuit includes an abnormal voltage detection circuit and an output line thereof, and the abnormal voltage detection circuit is inserted between the power supply terminal and the cathode of the first diode, and between the power supply terminal and the signal input terminal. The output line connects between the abnormal voltage detection circuit and the input terminal of the internal circuit, and the output from the abnormal voltage detection circuit is supplied to the internal circuit together with the reset output from the reset circuit. 2) In the means described in 2) above, the abnormal voltage detection circuit provided in the semiconductor circuit is Sword is a diode connected to the power supply terminal side, the output line,
The cathode of the first diode and the anode of the diode connected to the power supply terminal side are connected to each other, and 3) the abnormal voltage detection circuit provided in the semiconductor circuit according to the means described in 2 above. Is a series connection body of a diode whose cathode is connected to the power supply terminal side and a resistance element which is connected to the anode of this diode, and whose output line is the cathode of the first diode, the diode and the resistor. To be configured to be drawn out from a connection point with a resistance element that a series connection body with the element has,
4) In the means described in the items 1 to 3, the semiconductor integrated circuit device includes an inverter circuit and a semiconductor switch, and the inverter circuit has a reset output from a reset circuit of the semiconductor integrated circuit device at an input terminal thereof. Is input, and the output inverted from the reset output is output from the output terminal to the input terminal that receives the reset output included in the internal circuit of the semiconductor integrated circuit device. A configuration in which the output line of the abnormal voltage detection circuit which is connected between the output terminal of the inverter circuit and the ground terminal and which is included in the semiconductor circuit of the semiconductor integrated circuit device is connected to its gate;
Furthermore, 5) in the means described in the above items 1 to 4, the semiconductor circuit includes a capacitor element, and the capacitor element is connected between a connection point from which an output line of the abnormal voltage detection circuit is drawn out and a ground terminal. It is achieved by adopting a different configuration.

[0014]

According to the present invention, the semiconductor integrated circuit device is connected between the power supply terminal of the semiconductor circuit and the cathode of the first diode, for example, the cathode is a diode connected to the power supply terminal side. , Or an abnormal voltage detection circuit whose cathode is a series connection of a diode and a resistance element connected to the power supply terminal side, and a connection point between the abnormal voltage detection circuit and the cathode of the first diode, In a system including a plurality of semiconductor integrated circuit devices whose power supply systems are separated by including an output line connected to an input terminal of an internal circuit, a semiconductor integrated circuit device (for example, an LCD controller)・ The power of the driver is cut off,
When the power of another semiconductor integrated circuit device (for example, a master CPU) is turned on and the output signal output from the other semiconductor integrated circuit device is the "H" output, this "H" output is a signal input. When the voltage is input from a terminal to a certain semiconductor integrated circuit device, this voltage is applied only to the side connected to the first diode of the abnormal voltage detection circuit provided in the certain semiconductor integrated circuit device. At the connection point between the voltage detection circuit and the first diode, a voltage at the High level of [“H” output− (voltage drop in resistance element + forward voltage drop of first diode)] is generated. This High
The voltage generated at the connection point, which is the level, is supplied to the input terminal provided in the internal circuit through the output line, so that the reset output (Vr) of the reset circuit has the same function as the “H” output. , An internal circuit provided in a semiconductor circuit of a semiconductor integrated circuit device is surely reset.

Further, in the aforementioned semiconductor integrated circuit device, the internal circuit of the semiconductor integrated circuit device receives the reset output from the reset circuit of the semiconductor integrated circuit device at its input terminal, and inverts this reset output and outputs it. Provided is an inverter circuit that outputs from a terminal, and a semiconductor switch that is connected between the output terminal of the inverter circuit and the ground terminal and that connects the output line of the abnormal voltage detection circuit included in the semiconductor circuit of the semiconductor integrated circuit device to its gate. With the configuration, the voltage generated at the connection point between the abnormal voltage detection circuit and the first diode is buffered by the semiconductor switch and then supplied to the internal circuit, so that the above-described operation is performed with high reliability. be able to.

Furthermore, in the above-described semiconductor integrated circuit device, the semiconductor integrated circuit device is configured such that a capacitor element is connected between a connection point from which the output line of the abnormal voltage detection circuit is drawn out and a ground terminal. , Even when the output signal output from another semiconductor integrated circuit device frequently repeats the “H” output and the “L” output, the abnormal voltage detection circuit occurs at the connection point of the first diode. By smoothing the voltage with a capacitor element, a stable voltage is supplied to an internal circuit included in a semiconductor circuit of a semiconductor integrated circuit device through an output line, and the internal circuit is stably held in a reset state.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. Embodiment 1; FIG.
3 is a circuit diagram of a main part of a semiconductor integrated circuit device according to an embodiment corresponding to Nos. 3 and 5, and FIG. 2 is a cross-sectional view showing a structural example of an abnormal voltage detection circuit included in the semiconductor integrated circuit device in FIG. 1. 1 and 2, the same parts as those of the conventional semiconductor integrated circuit device shown in FIGS. 4 to 7 are designated by the same reference numerals, and the description thereof will be omitted.

1 and 2, reference numeral 10 denotes a semiconductor integrated circuit device used as an LCD controller driver, and the LCD controller driver 10 has a single output signal 51 (51a to 51n). An individual driver 11 (11a, 11n) as a plurality of semiconductor circuits that performs conversion processing corresponding to each signal is provided,
Each individual driver 11 includes the abnormal voltage detection circuit 20 between the line on the power supply terminal 81 side and the cathode of the first diode 65.

The abnormal voltage detection circuit 20 includes a diode 21 whose cathode is connected to the power supply terminal 81 side line,
It is configured as a series connection body of the resistance element 22 connected between the anode of the diode 21 and the cathode of the first diode 65. 23 is the abnormal voltage detection circuit 20.
Has one end connected to the connection point 24 between the resistance element 22 of the internal circuit 63 and the cathode of the first diode 65, and the other end connected to the input terminal 63a (63aa, to 63an) of the internal circuit 63. It is an output line. 25 is a connection point 24
And a grounding terminal 82, which is a capacitor element that smoothes the voltage generated at the connection point 24, and hence the output line 23.

FIG. 2 shows an embodiment in which the above-mentioned abnormal voltage detection circuit 20 and its peripheral circuits are formed on a silicon substrate by applying an N-type CMOS process. In FIG. 2, the first diode 65 has an N-
A low concentration N-diffusion layer 3 and a high concentration P + diffusion layer 4 are formed in a region of the substrate 1 which is isolated by the P-well 2, and the diode 21 has a high concentration P + diffusion layer in the N- substrate 1 region. 5, the resistance element 22 is made of polysilicon provided by a method such as vapor deposition on an insulating film (not shown) formed on the N- substrate 1 on which the various circuit elements are formed. Further, the capacitor element 25 is a MOSF (not shown) formed on the N- substrate 1.
It is formed by the junction capacitance of the ET gate and the like. In addition, 6 is
Reference numeral 8 denotes a ring-shaped power contact formed by the low-concentration N-diffusion layer 3 and the high-concentration N + diffusion layer 7 in the N-substrate 1 region, and 8 extends across the N-substrate 1 region and the P-well 2. This is a ring-shaped ground contact formed by the low-concentration P− diffusion layer 9 and the high-concentration P + diffusion layer 5.

As shown in FIG. 2, the above-mentioned abnormal voltage detection circuit 20 and its peripheral circuits can be manufactured by using the CMOS process which is generally adopted for manufacturing semiconductor elements. Since the present invention has the above-described configuration, the power supply of the LCD controller driver 10 is cut off, but the power supply of the master CPU 50 is turned on, and the output signal 51 output from the master CPU 50 is "H" output. In this case, the “H” output of the output signal 51 is used as a power source, and the signal input terminal 83 → resistive element 67 → first diode 65 → connection point 24 → resistive element 22 → diode 21 → LCD controller / driver 10 A current flows through the path of the power supply line → internal circuit 63 → ground line, and a voltage of 1 to 3 [V] similar to the conventional example is generated in the power supply line of the LCD controller driver 10.

When this voltage value exceeds the set value (Vo) of the reset circuit 68, the internal circuit 63 can be in the operating state. However, at the connection point 24, [the output signal 51 is "H"]. Output voltage- (resistive element 67
(Voltage drop inside + forward voltage drop of the first diode 65)], a voltage having a value higher than the voltage of the power supply line of the LCD controller driver 10 is generated, and this voltage is generated through the output line 23 to the internal circuit 63. Reset output (V
Since the value of the voltage from the output line 23 is higher than the set value (Vo) by being applied to the input terminal 63a for receiving the r) 69, it is "H" for the internal circuit 63.
The output is exactly the same as when the reset output (Vr) 69 is received, the internal circuit 63 is surely reset, and the internal circuit 63 does not enter the operating state. Therefore, the output terminal of the internal circuit 63 is used for driving. Data signal 64 (64
a, .about.64n) are not output. Here, the resistance element 22
Is provided for setting the difference between the voltage value generated in the power supply line of the LCD controller driver 10 and the voltage value generated in the output line 23 to a desired value.

The output signal 51 output from the master CPU 50 is "H" by the operation of the master CPU 50.
It may be an output or an "L" output, and these may be repeated frequently. In this case, the value of the voltage from the output line 23 fluctuates, and the operation of the internal circuit 63 repeats the reset state and the normal operation state. Therefore, the value of the voltage from the output line 23 is changed by the capacitor element 25. Smoothing is performed so that the operation of the internal circuit 63 is stably held in the reset state.

When the power of the LCD controller / driver 10 which has been cut off is turned on, a voltage having substantially the same value is applied between the power supply terminal 81 and the signal input terminal 83. The first diode 6
Since 5 is in a non-conducting state, no voltage is generated at the connection point 24. As a result, the internal circuit 63 enters a reset operation state or a normal operation state that is a normal operation state according to the reset output 69 from the reset circuit 68.

The LCD controller / driver 1
When the power of 0 is cut off, the power of the master CPU 50 is turned on, and the output signal 51 output from the master CPU 50 is continuously “L” output, the LCD controller / driver No voltage exceeding the set value (Vo) is generated in the power supply line 10 so that the internal circuit 63 becomes inoperative.

The LCD controller / driver 1
0 and the power of the master CPU 50 are turned on,
Moreover, the output signal 51 output from the master CPU 50
Is an “L” output, the voltage of the power supply line of the LCD controller / driver 10 becomes higher than the voltage of the line connected to the signal input terminal 83 of the LCD controller / driver 10, Since the current from the line is blocked by the diode 21, even in this case, the LCD controller driver 10
Can perform the intended operation without any hindrance.

Furthermore, an external charged body such as human being is LC
Various terminals 81, 82, 8 of the D controller driver 60
Regarding the protection of the LCD controller / driver 60 from the electrostatic damage when it contacts the terminal 3, the terminals 82 and 8
3 is the same as the conventional example, and since the diode 21 and the resistance element 22 are only added to the conventional example between the terminals 83 and 81, the same level of protection as the conventional example is provided. Is what you can do.

In the above description, the abnormal voltage detection circuit 20
Is provided with the resistance element 22, but the present invention is not limited to this, and the resistance element 22 may not be provided. Further, although the capacitor element 25 is inserted between the connection point 24 and the ground terminal 82 in the above description, the invention is not limited to this, and the capacitor element 2 is not limited thereto.
Even without installing 5, the power supply of the LCD controller driver 10 is cut off, but the power supply of the master CPU 50 is still on, and the output signal 51 output from the master CPU 50 is “H” output. The capacitor element 25 is provided if the internal circuit 63 can be stably reset when the output signal 51 is the “H” output even if it varies between the “L” output. It is not necessary.

Embodiment 2; FIG. 3 shows claims 1 and 2 of the present invention.
FIG. 4 is a circuit diagram of a main part of a semiconductor integrated circuit device according to an embodiment corresponding to 2, 3, 4, 5 and corresponds to claims 1, 2, 3, 5 of the present invention shown in FIG. 1 in FIG. 3. The same parts as those of the semiconductor integrated circuit device according to the embodiment and the semiconductor integrated circuit device of the conventional example shown in FIGS. 4 to 7 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 3, reference numeral 30 denotes a semiconductor integrated circuit device used as an LCD controller / driver, and the LCD controller / driver 30 has a plurality of output signals 51 (51a to 51n) for each single output signal. A plurality of individual drivers 31 (31a, 31n) as semiconductor circuits for performing corresponding conversion processing are provided, and each individual driver 31 buffers an output signal 51 by a CMOS inverter 62 that is a buffer amplifier circuit. Is input to the internal circuit 33, converted into data suitable for driving the LCD 70 in the internal circuit 33, and output from the output terminal 63b (63ba, 63bn) as a driving data signal 64 (64a, 64n). To do. Further, the internal circuit 33 has an input terminal 33a (33) for receiving an inversion reset output (Vr ') 41 described later.
aa, ~ 33an). Further, in the individual driver 31, the other end of the output line 23 whose one end is connected to the connection point 24 (the abnormal voltage detection circuit 20 and the cathode of the first diode 65) will be described later. It is connected to the gate 42a of the semiconductor switch 42.

When the internal circuit 33 receives the inverted reset output (Vr ') 41 of "L" output, it enters the reset state and does not output any output to the LCD 70. Also,
When the inverted reset output (Vr ') 41 of "H" output is received, the normal operation state in which the intended operation is performed is performed, and the master CP
Drive data signal 6 according to the output signal 51 from U50
4 (64a, to 64n) is output to the LCD 70. The internal circuit 6 in the first embodiment and the conventional example is the same except for the operation corresponding to the inverted reset output (Vr ′) 41.
The same operation as 3 is performed.

The input 40 receives the reset output (Vr) 69 from the reset circuit 68 from its input terminal 40c, and outputs an inverted reset output (Vr ') 41 inverted with respect to the reset output (Vr) 69 to the output terminal 40d. Is an inverter circuit that simultaneously outputs all the input signals to the input terminals 33a of the internal circuits 33, is configured as a CMOS inverter, and is connected to the power supply terminal 81 side.
ET40a and N-MO connected to the ground terminal 82 side
The SFET 40b is provided, the gates of the MOSFETs 40a and 40b are connected to each other to form the input terminal 40c of the inverter circuit 40, and the drain of the P-MOSFET 40a and the drain of the N-MOSFET 40b are connected to each other to form the output terminal 40d of the inverter circuit 40. There is.

Here, the output terminal 4 of the inverter circuit 40
Inversion reset output (Vr ') 41 output from 0d
When the power supply voltage value (Vs) exceeds the threshold value (Vth), the reset output (Vr) 69 is “L” when the output is “H”, and the reset output (Vr) 69 is “L” when the output is “L”. "H" output. When the power supply voltage value (Vs) is less than or equal to the threshold value (Vth), the inversion reset output (Vr ′) 41 is the reset output (Vr).
Regardless of whether 69 is an "H" output or an "L" output, it becomes an "L" output.

42 is an output terminal 40d of the inverter circuit.
Connected to the ground terminal 82 and its gate 42
N-MOSF in which the other end of the output line 23 is connected to a
A semiconductor switch circuit composed of ET, N-MO
The drain 42b of the SFET is connected to the inverting reset output (Vr ') 41 output from the inverter circuit 40,
The source 42c of the N-MOSFET is connected to the ground terminal 82.

Since the present invention has the above-mentioned configuration, the LCD is
The power supply of the controller controller driver 30 is cut off, but the power supply of the master CPU 50 is still on, and the output signal 51 output from the master CPU 50 is "H".
In the case of an output, as in the case of the LCD controller driver 10 in the first embodiment, the connection point 24 between the cathode of the first diode 65 and the abnormal voltage detection circuit 20.
, A voltage higher than the voltage of the power supply line of the LCD controller driver 30 is generated. This voltage is applied to the gate 42 of the semiconductor switch circuit 42 through the output line 23.
When the semiconductor switch circuit 42 is turned on by being applied to a, the voltage input to the input terminal 33a of the internal circuit 33 is the inverted reset output (Vr ′) 41,
The reset output (Vr) 69 is set to the Low level regardless of whether it is the “H” output or the “L” output. The internal circuit 33 which has received this Low level signal,
In the reset state, no output is issued to the LCD 70.

When the LCD controller / driver 30 which has been cut off is turned on, no voltage is generated at the connection point 24, whereby the semiconductor switch circuit 42 is turned off. , The internal circuit 33 becomes capable of receiving the inverted reset output (Vr ′) 41, and in response to the reset output 69 from the reset circuit 68, enters the reset state or the normal operating state which is the normal operating state. Is the same as the LCD controller / driver 10 in the first embodiment.

[0037]

According to the present invention, the semiconductor integrated circuit device is connected between the power supply terminal of the semiconductor circuit and the cathode of the first diode, for example, the diode whose cathode is connected to the power supply terminal side. Or an abnormal voltage detection circuit whose cathode is connected in series with a diode and a resistance element connected to the power supply terminal side, and a connection point between this abnormal voltage detection circuit and the cathode of the first diode. And an output line connected to the input terminal of the internal circuit, a semiconductor integrated circuit device (for example, L
The power of the CD controller / driver is cut off, but other semiconductor integrated circuit devices (for example, master CPU)
Is turned on, and when the output signal output from another semiconductor integrated circuit device is “H” output,
When this H output is input from a signal input terminal to a certain semiconductor integrated circuit device, this voltage is only connected to the first diode of the abnormal voltage detection circuit provided in the certain semiconductor integrated circuit device. A high level voltage is generated at the connection point between the abnormal voltage detection circuit and the first diode. The voltage generated at the connection point at the high level is supplied to the input terminal of the internal circuit through the output line, so that it is as if the reset output (Vr) of the reset circuit.
Has the same function as the output of "H" and resets the internal circuit included in the semiconductor circuit of a certain semiconductor integrated circuit device, thereby reliably generating an abnormal state in the certain semiconductor integrated circuit device. To be prevented.

In the above-described semiconductor integrated circuit device, the internal circuit of the semiconductor integrated circuit device receives the reset output from the reset circuit of the semiconductor integrated circuit device at its input terminal, inverts the reset output, and outputs the inverted output. Provided is an inverter circuit that outputs from a terminal, and a semiconductor switch that is connected between the output terminal of the inverter circuit and the ground terminal and that connects the output line of the abnormal voltage detection circuit included in the semiconductor circuit of the semiconductor integrated circuit device to its gate. With the configuration, the voltage obtained at the connection point between the abnormal voltage detection circuit and the first diode is supplied to the internal circuit after being buffered by the semiconductor switch, so that the above-described operation / effect can be achieved with high reliability. It can be carried out.

Furthermore, in the above-described semiconductor integrated circuit device, the semiconductor integrated circuit device is configured such that a capacitor element is connected between a connection point from which the output line of the abnormal voltage detection circuit is drawn out and a ground terminal. , Even when the output signal output from another semiconductor integrated circuit device frequently repeats “H” output and “L” output, it occurs at the connection point between the abnormal voltage detection circuit and the first diode. By smoothing the voltage with a capacitor element, a stable voltage is supplied to an internal circuit included in a semiconductor circuit of a certain semiconductor integrated circuit device, and the internal circuit is stably held in a reset state. It is possible to more reliably prevent the occurrence of an abnormal state in the device.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor integrated circuit device according to an embodiment corresponding to claims 1, 2, 3, and 5 of the present invention.

FIG. 2 is a cross-sectional view showing a structural example of an abnormal voltage detection circuit included in the semiconductor integrated circuit device in FIG.

FIG. 3 is a circuit diagram of a main part of a semiconductor integrated circuit device according to an embodiment corresponding to claims 1, 2, 3, 4, and 5 of the present invention.

FIG. 4 is a block circuit diagram of an LCD device using a conventional semiconductor integrated circuit device as an LCD controller driver.

5 is a circuit diagram of a main part of a semiconductor circuit corresponding to one input of the semiconductor integrated circuit device shown in FIG.

6 is a circuit diagram of a main part of the semiconductor integrated circuit device shown in FIG.

7A and 7B show the relationship between the power supply voltage value of the reset output output by the reset circuit included in the semiconductor integrated circuit device shown in FIG. 6, FIG. 7B is the power supply voltage change state, and FIG. FIG.

[Explanation of symbols]

10 Semiconductor Integrated Circuit Device (LCD Controller / Driver) 11 Semiconductor Circuit (Individual Driver) 20 Abnormal Voltage Detection Circuit 21 Diode 22 Resistive Element 23 Output Line 24 Connection Point 25 Capacitor Element 30 Semiconductor Integrated Circuit Device (LCD Controller / Driver) 31 Semiconductor Circuit (individual driver) 33 Internal circuit 33a Input terminal 40 Inverter circuit 40c Input terminal 40d Output terminal 41 Inversion reset output (Vr ') 42 Semiconductor switch 42a Gate 63 Internal circuit 63a Input terminal 63b Output terminal 65 First diode 66 Second Diode 68 Reset circuit 68a Power supply voltage value determination circuit 69 Reset output (Vr) 81 Power supply terminal 82 Earth terminal 83 Signal input terminal Vo Set value

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[Procedure amendment]

[Submission date] December 2, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

Claims (5)

[Claims] 1. A reset circuit and a semiconductor circuit, wherein the reset circuit includes a power supply terminal for receiving a power supply voltage, a ground terminal, and a power supply voltage value determination circuit connected between the power supply terminal and the ground terminal. The power supply voltage value determination circuit detects the value of the power supply voltage, and outputs a reset output to the semiconductor circuit, which resets the semiconductor circuit when the power supply voltage falls below a preset value. The semiconductor circuit is a power supply terminal for receiving a power supply voltage, a signal input terminal for receiving a signal input voltage, a ground terminal for each of the power supply voltage and the signal input voltage,
A first diode inserted between the power supply terminal and the signal input terminal and having a cathode connected to the power supply terminal side; and a cathode inserted between the signal input terminal and the ground terminal, the cathode being the signal input terminal An internal circuit having a second diode connected to, and an input terminal that is protected from electrostatic damage by these diodes and that receives a reset output from the reset circuit. When a reset output is received from the reset circuit, In the semiconductor integrated circuit device, the internal circuit is in a reset state, and when the reset output that should bring the internal circuit into the reset state is not received from the reset circuit, normal operation is performed according to the signal input voltage. Includes an abnormal voltage detection circuit and an output line thereof, wherein the abnormal voltage detection circuit is a power supply. Is inserted between the child and the cathode of the first diode and detects a voltage difference between a power supply terminal and a signal input terminal, and the output line is an input terminal of the abnormal voltage detection circuit and the internal circuit. The semiconductor integrated circuit device is characterized in that an output from the abnormal voltage detection circuit is supplied to an internal circuit together with a reset output from a reset circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the abnormal voltage detection circuit included in the semiconductor circuit is a diode whose cathode is connected to the power supply terminal side, and the output line of which is the first diode. A semiconductor integrated circuit device, which is drawn out from a connection point between a cathode and an anode of a diode connected to the power supply terminal side. 3. The semiconductor integrated circuit device according to claim 1, wherein the abnormal voltage detection circuit included in the semiconductor circuit includes a diode whose cathode is connected to the power supply terminal side, and a resistance element connected to the anode of this diode. Is a serial connection body of the first diode, the output line is drawn from the connection point of the cathode of the first diode and the resistance element of the series connection body of the diode and the resistance element, Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device includes an inverter circuit and a semiconductor switch, and the inverter circuit has an input terminal for resetting the semiconductor integrated circuit device. A reset output from the circuit is input, and an output inverted from the reset output is output from the output terminal to an input terminal that receives the reset output included in the internal circuit of the semiconductor integrated circuit device. The semiconductor switch is connected between the output terminal of the inverter circuit and the ground terminal, and connects the output line of the abnormal voltage detection circuit included in the semiconductor circuit of the semiconductor integrated circuit device to its gate. A characteristic semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor circuit includes a capacitor element, and the capacitor element is provided between a connection point from which an output line of the abnormal voltage detection circuit is drawn out and a ground terminal. A semiconductor integrated circuit device characterized by being connected to a semiconductor integrated circuit device.