JPH06162786A - Information processor using flash memory - Google Patents

Abstract

PURPOSE:To increase the write speed of a flash memory where data is written after block erasing and to extend the life by writing data after erasing held data of the 'flash memory only in the case of noncoincidence between held data of the flash memory and input data. CONSTITUTION:When write data held in a write back cache 4 will be written in a flash memory 5 in block units, a flash memory control part 2 first reads out contents of the write back cache 4 and those of the flash memory 5 into a comparator 6 with one word as the unit. The comparator 6 compares contents of the write back cache 4 and contents of the flash memory 5 corresponding to the write address; and if they do not coincide with each other, the comparator 6 outputs an erase signal 53 to erase contents of the flash memory 5 in a minimum erasable unit including this one-word data. Contents of the cache 4 including one-word data are written by the control of a control part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device using a flash memory, and more particularly, to improvement of continuous data writing speed and reliability in a semiconductor disk device using a flash memory.

[0002]

2. Description of the Related Art A flash memory chip can be read in word units, but rewriting may or may not be possible depending on changes in bits. In the present invention, the direction of rewritable bits is changed from 1 to 0 (for example,
FFh (11111111B) to 55h (01010101B)) and rewriting 0 to 1 (for example, 55h (01010101B) to F
Fh (11111111B)) is described as impossible.

Writing data to a flash memory is
First, existing data must be erased (all bits are set to 1) and new data must be written.
Erasing can be performed only on a chip basis or a block basis of a plurality of words.

In the conventional flash memory writing circuit, even if the contents already written in the flash memory and the contents of the write data match, the existing data is erased before the writing process.

In the EEPROM, for example, Japanese Patent Laid-Open No. 03-
As shown in Japanese Patent No. 283093, a method of comparing held data with input data in byte units and automatically prohibiting writing when trying to write the same content is shown in Japanese Patent Laid-Open No. 03-049099. As described above, there is a method of comparing the held data with the input data and selecting and executing only the erase cycle or only the write cycle.

[0006]

Even if the contents already written in the flash memory and the contents of the write data match, the flash memory write circuit that performs the write process increases the erase count and the write count, and the write process This leads to increase in time, decrease in reliability, and shortening of life.

Therefore, in the present invention, in order to speed up the writing process to the flash memory, a comparator for comparing the contents of the write data and the contents of the flash memory corresponding to the write address is provided, and each minimum erasable unit is In addition, when trying to write the same contents, erasing and writing are automatically prohibited. In addition, in the writing in which the bit is changed from 1 to 0, erasing is prohibited and only the writing is performed to solve the above problem.

[0008]

[Means for Solving the Problems] In order to solve the above problems, the following means can be considered.

A plurality of bits are set as one word and can be read in a word unit, and a flash memory capable of writing and electrically erasing in a chip unit or a plurality of word units is mounted, and data is continuously written in the flash memory. In the device, for each minimum writable unit, the content of the write data is compared with the content of the flash memory corresponding to the write address, and if they do not match, a comparator that outputs a signal that erases the content of the flash memory is turned on. , When the bit is written from 0 to 1, it is a means equipped with a comparator for outputting a signal for erasing the contents of the flash memory as ON.

[0010]

As a configuration example of the present invention, for example, a configuration including a flash memory control unit, a write-back cache, a plurality of flash memories, and a comparator can be considered.
These can be configured by electronic devices.

The operation will be described below based on the above-mentioned configuration example.

Write data is temporarily held in the write-back cache in order to perform writing and reading from the flash memory from the system at high speed. Normally, writing and reading from the system to the flash memory are performed between the write-back cache and the system, and the data of the write-back cache is written to the flash memory on a block-by-block basis as needed.

In the present invention, this writing process is speeded up. First, under the control of the flash memory control unit, the contents of the write-back cache and the contents of the flash memory corresponding to the write address are read out to the comparator. The comparator compares these data and outputs an erase signal if there is a write that changes the bit from 0 to 1 due to a mismatch.

By this processing, if there is a mismatch and there is further writing to change the bit from 0 to 1, erasing and writing are performed.

In the case of non-coincidence and further writing from 1 to 0, only the writing process is performed without erasing.

When the contents already written in the flash memory and the contents of the write data match, the writing process is not performed.

As described above, the number of times of writing can be reduced, the writing speed can be increased and the life can be extended.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG.

In this embodiment, the flash memory controller 2,
It is configured to have a write-back cache 4, a plurality of flash memories 5, a comparator 6, a data bus 50, an address bus 51, a control bus 52, and a standard bus 1.

The standard bus 1 is a bus for transmitting and receiving commands and data from a system such as a personal computer or a workstation to this device.

The flash memory control unit 2 is means for controlling the write-back cache 4, the flash memory 5, the comparator 6, etc., which are the constituent elements of this device, and is, for example,
It is composed of a microprocessor and the like.

The write-back cache 4 is a cache memory that temporarily holds the write data transferred from the standard bus 1 in order to write and read data to and from the flash memory 5 at a high speed.
And other semiconductor devices. Normally, writing and reading from the system to the flash memory 5 are performed between the write-back cache 4 and the system, and the data of the write-back cache 4 is written to the flash memory 5 in block units as needed. The write-back cache 4 may use a part of the data storage area on the system side, not limited to this device.

When writing the contents of the write-back cache to the flash memory in block units, the comparator 6 compares the contents of the write-back cache 4 with the contents of the flash memory 5 corresponding to the write address. It outputs the erase signal 53, and is composed of, for example, electronic devices such as various TTLs, transistors, and resistors.

In this embodiment, the write back cache 4
When writing the write data stored in the flash memory 5 to the flash memory 5 in block units, the flash memory control unit 2 first reads the contents of the write-back cache 4 and the contents of the flash memory 5 into the comparator 6 word by word. I will The comparator 6 compares the contents of the write-back cache 4 and the contents of the flash memory 5 corresponding to the write address, and outputs the erase signal 53 if they do not match,
The contents of the flash memory 5 are erased in the minimum erasable unit including this 1-word data, and the flash memory control unit 2
Under the control of, the writing of the content of the write-back cache 4 in the minimum erasable unit including the 1-word data is performed using the data bus 50 and the address bus 51.

FIG. 2 is a flow chart showing details of the write operation controlled by the flash memory controller 2.

First, the flash memory control unit 2 checks whether or not there is a block to be written in the flash memory 5 in the write-back cache 4 (step 21 in FIG. 2), and if there is a block, it is necessary to write for each minimum erasable unit. Writing is performed by determining whether or not there is. First, one word data is read from the contents of the flash memory 5 corresponding to the write address and the write-back cache 4 (step 22) (step 23). The comparator 6 determines whether the contents of the flash memory 5 corresponding to the write address and the 1-word data read from the write-back cache 4 match (step 24).

If they do not match, the comparator 6 outputs the erase signal 53.
Is output, and the flash memory 5 is erased in the minimum erasable unit including this 1-word data (step 25), and the 1-word data in the write-back cache 4 is included under the control of the flash memory control unit 2. The minimum erasable write data is written in the flash memory 5 (step 26). In addition, write-back cache 4
The write data of the minimum erasable unit of which writing has been completed is erased (step 27), and the process returns to (step 21).

If they match, the flash memory control unit 2 determines whether the comparison of the data for each minimum erasable unit is completed (step 28). If the comparison is completed, the process proceeds to (step 21). If not, (step 2
Perform step 2).

As a second embodiment, the flash memory 5
FIG. 3 shows a configuration in which the write-back cache 4 and the comparator 6 are provided inside.

With this configuration, the process of FIG. 2 is performed inside the flash memory 5.

Since writing from 1 to 0 can be performed in word units without erasing, the contents of the flash memory 5 can be erased and written only when writing from 0 to 1. A third embodiment for performing the processing is shown in FIG.

The second comparator 7 compares the 1-word data of the write-back cache 4 with the contents of the flash memory 5 corresponding to the write address, and in the case of writing to change the bit from 0 to 1 (eg, 0000h to FFFFh. When writing), the erase signal 53 is output,
For example, it is composed of electronic devices such as various TTLs, transistors, and resistors.

FIG. 5 is a flowchart showing details of the write operation controlled by the flash memory control unit 2.

First, as in FIG. 2, the contents of the flash memory 5 corresponding to the write address and the write-back cache 4 are read out to the second comparator 7 (step 22).
(Step 23).

The second comparator 7 determines whether this write processing is a write for changing the bit from 0 to 1. (Step 30) If the write process is a write for changing the bit from 0 to 1, the second comparator 7 outputs the erase signal 53 and performs the same process as in FIG. In the case of other write processing, the process returns to (step 28), and if the comparison of the data for each minimum erasable unit is completed, the write data is written in this minimum erasable unit (step 2).
6).

As a fourth embodiment, the flash memory 5
FIG. 6 shows a configuration in which the write-back cache 4 and the second comparator 7 are provided inside.

With this configuration, the process of FIG. 5 is performed inside the flash memory 5.

Furthermore, a fifth embodiment is shown in FIG. 7 using both the first embodiment and the third embodiment. In the present embodiment, the AND means 8 is used only when the contents of the flash memory 5 corresponding to the write address and the 1-word data read from the write-back cache 4 do not match and there is a write to change the bit from 0 to 1. Erase signal 53
Output and erases.

FIG. 8 is a flowchart showing details of the write operation controlled by the flash memory control unit 2.

First, as in FIG. 2, the contents of the flash memory 5 corresponding to the write address and the write-back cache 4 are read out to the comparator 6 and the second comparator 7 (step 22) (step 23).

It is determined whether or not the contents of the flash memory 5 corresponding to the write address and the 1-word data read from the write-back cache 4 do not match and the bit is written from 0 to 1. (Step 24)
(Step 30) In this case (eg, AAAAh is FF
(Rewrite to FFh) is erased and written as in FIG.

In the case of a write process in which the bits do not match and the bit is changed from 1 to 0 (for example, FFFFh is rewritten to AAAAh), writing is performed without erasing.

If they match, writing is not performed, as in FIG.

An example of this operation is summarized in Table 1.

[0045]

[Table 1]

As a sixth embodiment, the flash memory 5
FIG. 9 shows a configuration in which the write-back cache 4, the comparator 6, and the second comparator 7 are provided inside the memory.

In this configuration, the process of FIG. 8 is performed inside the flash memory 5.

[0048]

As described above, according to the present invention, by the comparator of the data held in the flash memory and the input data,
Only when they do not match, the data held in the flash memory is erased and the data is written, whereby the number of times of writing and the number of times of erasing can be minimized. Therefore, there is an effect that the writing speed of the flash memory in which writing is performed after the block is erased is increased and the life is extended.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment for performing the operation of the present invention.

FIG. 2 is a flow chart showing a write operation in the first embodiment.

FIG. 3 is a block diagram showing a second embodiment for performing the operation of the present invention.

FIG. 4 is a block diagram showing a third embodiment for performing the operation of the present invention.

FIG. 5 is a flowchart showing a write operation in the third embodiment.

FIG. 6 is a block diagram showing a fourth embodiment for performing the operation of the present invention.

FIG. 7 is a block diagram showing a fifth embodiment for performing the operation of the present invention.

FIG. 8 is a flowchart showing a write operation in a fifth embodiment.

FIG. 9 is a block diagram showing a sixth embodiment for performing the operation of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Standard bus, 2 ... Flash memory control part, 4 ... Write-back cache, 5 ... Flash memory, 6 ... Comparator, 7 ... Second comparator, 8 ... AND means, 9 ... Chip, 50 ... Data bus, 51 ... address bus, 52 ... control bus, 53 ... erase signal.

Claims (6)

[Claims] 1. An apparatus for mounting a flash memory, which can be read in a word unit with a plurality of bits as one word, and which can be electrically erased in a chip unit or a plurality of word units, and continuously write data to the flash memory. In the above, the method has a means for comparing the content of the write data with the content of the flash memory corresponding to the write address for each minimum erasable unit, and erases and writes the content of the flash memory only when they do not match. Processing device using the flash memory. 2. A means for comparing the content of write data with the content of the flash memory corresponding to the write address for each minimum erasable unit, and erasing and writing the content of the flash memory only when they do not match. Flash memory featuring. 3. An apparatus for mounting a flash memory which can be read in a word unit with a plurality of bits as one word and which can be electrically erased in a chip unit or a plurality of word units, and continuously write data to the flash memory. 2. An information processing apparatus using a flash memory, characterized in that means for determining whether or not erasure is necessary is provided for each minimum erasable unit. 4. An apparatus for mounting a flash memory, which can be read in word units with a plurality of bits as one word, and which can be electrically erased in chip units or in units of a plurality of words, and which continuously writes data to the flash memory. 2. An information processing device using a flash memory, which is characterized in that, when write data is rewritable, writing is performed without erasing. 5. A flash memory comprising means for determining whether or not erasing is necessary for each erasable minimum unit. 6. A flash memory, wherein when the write data is rewritable, the data is written without being erased.