JPH06161954A - Data width converting buffer device - Google Patents

Abstract

PURPOSE:To convert the input data into the n-fold data width and to output the converted data by providing a control circuit which gives an input instruction to a buffer and controls a selector. CONSTITUTION:A data width converting buffer consists of (n) pieces of buffers 1 having the data width equal to the input data width, an invalid data generator 2 which generates the invalid data having the width equal to the input data width, a selector 3 which selects a buffer 1 to which the input data and the invalid data are supplied, and a control circuit 4 which gives an input instruction to the buffer 1 and controls the selector 3. Thus (n) pieces of buffers 1 have the data width equal to the input data width, and the selector 3 switches the input data to the invalid data generated by the generator 2 and inputs them to the buffers 1. Then the circuit 4 gives the input instructions to the buffers 1 and performs the switching control of the selector 3. Thus the output data have the width (n) times as much as the input data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer device for converting a transfer data width in an electronic circuit.

[0002]

2. Description of the Related Art As semiconductor electronic circuits are highly integrated, the required number of pins serving as input / output terminals of so-called chips on which the circuits are mounted tends to increase. Since it is often structurally difficult to increase the number of pins required, it is often necessary to reduce the number of pins required by changing the data width transferred between chips and the data width in the chip.

As one of the solutions for such a case,
It is used to convert the data width through the buffer. Japanese Laid-Open Patent Publication No. 63-223945 discloses such a technique. In FIG. 2 of this publication, four buffers having the same data width as the input data width are provided, and when all the buffers are full, the data is output as quadruple the data width, and when all the buffers are not full. In the above, there is disclosed a technique for transferring the data, which has been jammed by the DMA controller, to the memory when the data is completed.

[0004]

However, in the case of such a technique, when the data is finished while all the buffers are not full, the data width is only the length of the input data, and the state of the end of the data is reached. Causes the output data width to change.

The present invention has been made in view of the above problems, and provides a data width conversion buffer device which outputs data having a constant width regardless of the end state of data and has a small circuit scale. To aim.

[0006]

To achieve the above object, n buffers 1 having a data width equal to the input data width, an invalid data generator 2 generating invalid data equal to the input data width, It is provided with a selector 3 for selecting which of the buffers 1 the input data and the invalid data are to be put in, and a control circuit 4 for instructing an input to the buffer 1 and controlling the selector 3.

Further, n buffers 11 having a data width larger than the input data width by k bits, and an invalid data generator 12 for generating invalid data equal to the input data width,
A selector 13 for selecting which of the buffers 11 to store the input data and the invalid data, and k bits indicating whether the data input to each of the buffers 11 is the input data or the invalid data are displayed. And a control circuit 14 for adding an input to the buffer 11 and inputting an instruction to the buffer 11 and controlling the selector 13.

Further, the selectors 3 and 13 are configured to directly input the input data to the uppermost buffers 1 and 11.

Further, the invalid data generators 2 and 12 and the selectors 3 and 13 are integrated by directly outputting all the bits of the input data into one of the buffers 1 and 11 or making them invalid data. is there.

Further, all the bits of the input data width or a part of the bits of the input data input data for indicating whether the input data is valid or invalid.

Further, a detector 5 for detecting a signal indicating whether the input data is valid or invalid is provided.

An input buffer 6 for inputting input data is provided in front of the detector 5.

Further, a detector 5 for detecting a signal indicating validity or invalidity of the data stored in the buffers 1 and 11 is provided.

Further, all the bits of the input data width or a part of the bits thereof inputs data indicating the end of the input data.

Further, a detector 7 for detecting a signal indicating the end of input data is provided.

An input buffer 6 for inputting input data is provided in front of the detector 7.

Further, a detector 7 for detecting a signal indicating the end of the data stored in the buffers 1 and 11 is provided.

Further, a signal indicating whether the input data is valid or invalid is input to the control circuits 4 and 14 together with the input data.

Further, a signal indicating the end of the input data is input to the control circuits 4 and 14 together with the input data.

Further, the control circuits 4 and 14 do not input the input data to all the n buffers 1 and 11 when the signal indicating the end of the input data is input. All the buffers 1 and 11 are subordinated to the buffers 1 and 11 containing the input data, and the invalid data are input in order by the selectors 3 and 13.

Further, the control circuits 4 and 14 cause the selectors 3 and 13 to input the invalid data to the remaining buffers 1 and 11 when inputting the input data to the uppermost buffers 1 and 11, and input the next and subsequent inputs. The data is the buffer 1,
When the signal indicating the end of the input data is input, the data in all buffers 1 and 11 at that time is output, and if all the buffers 1 and 11 are full with input data, The data of the buffers 1 and 11 are output.

Further, each time the input of the selector signal output from the control circuits 4 and 14 to the selectors 3 and 13 is input to the next lower buffers 1 and 11, the input data is input, After the signal indicating the end of the input data is input, the invalid data from the invalid data generators 2 and 12 are input.

Further, the buffers 1 and 11 selected by the selector signal are immediately before the selection.
The buffers 1 and 11 are one level lower than the buffers 1 and 11 instructed by the input instruction signal instructing the input to the buffer.

Further, when the input data stored in the n buffers 1 and 11 and the input data are completed, the invalid data from the invalid data generators 2 and 12 are stored as output data, and n data are output. The number of the buffers 1 and 11 containing the input data in the buffers 1 and 11 is output as an independent control signal.

Further, the number of the buffers 1 and 11 containing the input data or the buffers 1 and 11 containing the invalid data in the n buffers 1 and 11 is counted by a counter.

[0026]

Operation: n buffers having a data width equal to the input data width are provided, the selector 3 switches the input data and the invalid data from the invalid data generator 2 and inputs them, and the control circuit 4 inputs them to the buffer 1. Input instruction, selector 3
Switching control. In this way, the output data has a data width n times the width of the input data.

N buffers 11 having a data width larger than the input data width by k bits are provided, and the selector 13 inputs the input data and the invalid data from the invalid data generator 12. The control circuit 14 controls the selector 13 and at the same time, the data of each buffer 11 indicates whether the input data is invalid data by k bits and outputs it as output data. As a result, the output data has a signal indicating whether the data is input data or invalid data in units of the buffer 11.

The selectors 3 and 13 store input data or invalid data in the buffers 1 and 11, respectively. However, only the input data is stored in the top buffers 1 and 11. When invalid data is stored in the top buffers 1 and 11, invalid data is stored in the subsequent buffers 1 and 11, that is, when all invalid data are stored, such data is output. Is not output because there is no.
Therefore, it is sufficient for the selectors 3 and 13 to select and store the input data and the invalid data from the second buffers 1 and 11.

The selectors 3 and 13 input the input data as it is to 1
Either one of the buffers 1 and 11 or the invalid data into one of the buffers 1 and 11 is selected. Select invalid data in advance and select whether to output the input data as it is or to output the predetermined data.
Therefore, the invalid data generators 2 and 12 are unnecessary.

A signal indicating whether the input data is valid data or invalid data is represented by the bit of the input data itself. By inputting such data, the buffer device side can perform buffer input processing according to the input data. For example, when invalid data comes next to valid data, the selectors 3 and 13 input the invalid data to the buffer 1 as they are, so that it is not necessary to input the invalid data from the invalid data generators 2 and 12.

Input data containing a signal indicating such valid / invalid data is input, a detector 5 is provided to detect the signal, and the control circuits 4 and 14 detect whether the input data is valid or invalid. The selectors 3 and 13 are controlled based on the detection result.

The input buffer 6 of the detector 5 is provided, input data is input and then read by the detector 5, and a signal indicating whether the data is valid or invalid is detected. In this case, when this signal is composed of less than the full width of the input data, the input buffer stores only the bit of the signal.

By providing the detector 5 for checking the signal indicating whether the data stored in the buffers 1 and 11 is invalid or valid, it is possible to know whether the data to be output is valid or invalid in the width units of the buffers 1 and 11. .

On the side of the buffer device for inputting data in which a signal indicating whether the input data is the end data is represented by all or a part of the bits of the input data, buffer input processing can be performed according to the input data. For example, when the data indicating the end data is input, the selectors 3 and 13 input the invalid data from the invalid data generators 2 and 12 to the subsequent buffers 1 and 11, respectively.

When inputting input data having a signal indicating such end, the detector 7 detects this signal.
Is provided, an end signal is input, and invalid data input processing is performed by the selectors 3 and 13.

The input buffer 6 is provided in front of the detector 7, and after the input data is temporarily stored in the input buffer 6, the detector 7 detects the read end signal. Input buffer 6
The bit width of may be the bit width forming the end signal.

By detecting a signal indicating the end of the data stored in the buffers 1 and 11 by the detector 7, the selectors 3 are added to the buffers 1 and 11 subsequent to the detected buffers 1 and 11.
Perform processing to input invalid data from 13.

Validity of this input data together with the input data,
By inputting a signal indicating invalidity to the control circuits 4 and 14, it is not necessary to input a signal indicating valid or invalid to the input data and read it.

When the control circuits 4 and 14 receive a signal indicating the end of the input data, the buffers 1 and 11 containing the input data.
The selectors 3 and 13 are controlled so that the invalid data from the invalid data generators 2 and 12 are input to the subsequent buffers 1 and 11, respectively.

The control circuits 4 and 14 have the highest level buffers 1 and 11 respectively.
When the input data is input to, the remaining buffers 1 and 11 also input the invalid data from the selectors 3 and 13. The next input data is overwritten on the buffers 1 and 11 in which invalid data was previously entered. In this way, if a signal indicating the end of the input data is received, the invalid data is already stored in the buffers 1 and 11 that have not yet received the input data, so that it can be output immediately. Even if input data is put into all the buffers 1 and 11, if there is no signal indicating the end, it is outputted as it is. This eliminates the need to put invalid data in the buffers 1 and 11 which have not yet put input data after the end signal comes, and the data can be output earlier.

When a signal indicating the end of the input data is input, the control circuits 4 and 14 receive all the n buffers 1 and 11.
When the input data is stored in, it is output as it is, and when it is not stored in all the buffers 1 and 11,
Invalid data is sequentially stored by the selectors 3 and 13 in all the lower buffers 1 and 11 next to the buffers 1 and 11 in which input data is stored, and all n buffers 1 and 11 are filled with data. Output in a state.

The selector signals output from the control circuits 4 and 14 to the selectors 3 and 13 are input to the next lower buffers 1 and 11 each time input data is input, and the signal indicating the end of the input data is input. After that, invalid data generator 2,
Make sure to enter invalid data from 12 in order. As a result, one selector signal can be used to instruct input of input data and invalid data, and the circuit configurations of the control circuits 4 and 14 and the selectors 3 and 13 can be simplified.

Buffer 1 selected by the selector signal
Immediately before this selection, the buffer 11 is one lower than the buffers 1 and 11 instructed by the input instructing signal instructing the input to the buffers 1 and 11. Thus, the selector signal can be easily generated from the input instruction signal, and the input instruction signal to the buffers 1 and 11 and the selector signal can be substantially processed as one signal.

The n buffers 1 and 11 normally store the input data in all the buffers 1 and 11 to be output data, but when the input data ends, the input data are stored in order from the higher order and thereafter. The invalid data from the invalid data generators 2 and 12 are stored in the buffers 1 and 11, respectively. The number of the buffers 1 and 11 in which the input data of the n buffers 1 and 11 is stored is output as a control signal together with the output data independently of the output data. This allows the receiving side of the output data to know the content of the received data.

A counter for counting the number of input data or the number of invalid data is used as a structure for indicating the number of buffers 1 and 11 in which the input data is contained in the output data.

[0046]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of a first embodiment of the present invention.
This embodiment shows a case where the input data width is expanded three times.
Each buffer 1 has the same number of bits as the input data width and 3
It is composed of one buffer 1. The invalid data generator 2 generates invalid data for one buffer, for example, invalid data of all bits 1 or 0. The selector 3 inputs input data or invalid data to each buffer 1. However, input data is always stored in the uppermost buffer 1, and the data to the second and third buffers 1 is switched. The control circuit 4 receives the input data and selects the selector 3.
To which buffer 1 to store the data, and when the data end signal is input, the invalid data from the invalid data generator 2 is stored in the selector 3 in the buffer 1 and subsequent buffers 1 in which the final input data is stored. When the three buffers 1 are full, the buffer 1 outputs data having a width three times the input data width and outputs an output control signal.

FIG. 2 is a diagram showing a transition of data input to each buffer 1. A, B, and C indicate input data, and N indicates invalid data of the invalid data generator 2. Also, the counter values 0 to 3 represent the states of the respective buffers, the initial state is 0, the case where there is one input data and the number of invalid data is 1, and
The number is 3 when there are two pieces of input data and one piece of invalid data is three. This counter is provided in the control circuit 4 and counts based on a signal for controlling the selector 3. When the input data is one and the data end signal is input, the selector 3 outputs the remaining two buffers 1 with the invalid data N in the state ANN and returns to the initial state (counter 0). If there are two input data and a data end signal is input, it is output by ABN and the state of the counter 0 is returned.
If there are 3 input data and a data end signal is input, ABC
Is output at and returns to the counter 0. However, if there are three input data and the data end signal is not input, the data is output by ABC, then returns to the counter 1 to input the next input data, moves to the counter 2, further moves to the counter 3 and outputs the ABC, and the counters Repeat the state between.

FIG. 2 also shows the following case. That is, when the input data A is first input to the first buffer 1, the selector 3 puts invalid data in the remaining two buffers 1. Next, when the end signal is received, the signal is output as it is, and the counter 0 is returned. This is the case of counter 1. When the next input data B comes without the end signal, the input data B is added to the invalid data input by the counter 1.
Overwrite. Next, when the end signal comes, it outputs in that state and returns to the counter 0. This is the case of counter 2. When the next input data C comes without the end signal, the invalid data is overwritten. Next, when the end signal comes, it outputs in that state and returns to the counter 0. If the input data comes without the end signal, the data is output as it is and the counter 1 is returned. Counter 1 when input data is coming in continuously
~ The state between the counters 3 is repeated. In this way, the output of data becomes faster when the end signal is input.

The selector signals output from the control circuit 4 to the selector 3 switch the selectors 3 so that they are input to the lower buffer 1 one by one when the input data are sequentially stored. When the data end signal is received, the invalid data from the invalid data generator 2 is input to the subsequent lower buffer 1. As a result, two operations, that is, the operation of sequentially storing the input data and the invalid data in the buffer 1 and the operation of switching the input data and the invalid data,
This can be performed with one selector signal, and the control circuit 4 can be simplified and the circuit scale can be reduced.

FIG. 3 is a diagram showing a structure in which the invalid data generator 2 and the selector 3 are integrated. When the data end signal comes, the selector 3 stores the invalid data from the invalid data generator 2 in the buffer 1 thereafter. As invalid data, all bits of the input data width are set to 0 or 1. In (a), OR gates are provided by the number of bits of the input data width, input data is input to one input terminal of each OR gate, and signal A is input to the other terminal. If the signal A is set to 0 when the input data is input, the input data is output as it is. When inputting invalid data to the buffer 1, if A is set to 1, all outputs become 1 and become invalid data. in this case,
The invalid data is assumed to be when all bits are 1.

(B) shows a case in which the selector 3 and the invalid data generator 2 are integrated by an AND gate, and the invalid data is all bits 0 of the input data width. Input data is input to one input terminal of the AND gate, and the signal B is input to the other terminal. If the signal B is set to 1 when the input data is input, the input data is output as it is. When outputting the invalid data, if the signal B is set to 0, the output becomes 0 for all bits. As a result, the invalid data generator 2 and the selector 3 are integrated, and the circuit scale can be reduced. A buffer having a selector on the input side is also commercially available, and the circuit scale of the buffer and the selector can be reduced by using such a buffer.

In the above description, the data end signal is used as the signal to be input to the control circuit 4. However, instead of this data end signal, a control signal indicating the validity / invalidity of the input data is input to invalidate the input data. When the signal indicating that the input data has ended, the input data can be regarded as the end, and control can be performed in the same manner as in the case of the data end signal.

Next, a second embodiment will be described. In this embodiment, when both valid data and invalid data come to the input data, only the valid data is stored in the buffer 1 and the data width is tripled (n times) and output. FIG. 4 shows the configuration of this embodiment. The difference from the first embodiment is that a data valid signal is input together with the input data, and the function of the control circuit 4 which processes the input data by this data valid signal is different.

FIG. 5 is a diagram showing the relationship between input data and a data valid signal. The input data includes valid data and invalid data. When the valid data is valid data, the valid signal is H, and when the valid data is invalid signal, the valid signal is L. (The reverse is also possible.)

FIG. 6 is a diagram showing transition states of the buffer 1 of this embodiment. The counter 0 indicates the initial state and stands by when valid data is not input. This is indicated by a circular arrow in the figure. When valid data is input and invalid data comes next, it waits, and when a data end signal comes after that, invalid data from the invalid data generator 2 is input from the selector 3 to the remaining buffer 1 and output. Counter 1 indicates this state. The counter 2 waits because invalid data has come in after inputting valid data into the two buffers 1, and then when the data end signal is input, the remaining buffers 1
In this case, the selector 3 inputs and outputs invalid data from the invalid data generator 2. The counter 3 returns to the state of the counter 0 after outputting the data when the valid data enters the three buffers 1 and then the data end signal comes. When the valid data comes in succession, when the counter 3 outputs the data, the counter 3 returns to the counter 1, and the counters 1 to 3 are repeated to continuously output the output data.

When invalid data is input in the state of the counters 0 to 2, it is not input to the buffer 1 but the buffer 1 waits until valid data or a data end signal arrives. It is stored in the buffer 1 of. Even if invalid data is received one after another, the data is overwritten in the same buffer 1 and when the data end signal comes, the invalid data from the invalid data generator 2 is input to the buffer 1 and the subsequent buffers 1 and output to output valid data. When invalid, the invalid data may be overwritten.

In the above description, the data end signal and the data valid signal indicating data valid / invalid are input to the control circuit 4 as shown in FIG. 4, but these signals should be included in the input data itself. May be. FIG. 7 shows the input data itself with information indicating the validity / invalidity of the data. (A) shows an example of the invalid data, and all bits are set to 0. All bits may be 1. Except in this case, if the data is valid, it is possible to determine whether the data is valid or invalid.
(B) shows the validity / invalidity of the data with the most significant bit. When the value is 1, the data is invalid, and when it is 0, it is valid (or vice versa). However, in the case of (b), the most significant bit of the input data is always used for the information indicating the validity / invalidity of the data. On the other hand, in the case of (a), when it is valid data, it can be used for all bit data.

Although FIG. 7 represents the data valid / invalid signal, the data end signal may be represented by the same method. In the case of (a), when this data is sent next to the valid data, it indicates that the previous valid data is the last valid data. In the case of (b), the input data having 1 at the highest level indicates the end of data. Therefore, it is set to 0 in the normal case. Therefore, the most significant bit cannot be used for data.

FIG. 8 shows a state in which the detector 7 for detecting the data end signal included in the input data is provided. The input data is input to the end data detector 7, a data end signal is detected and output to the control circuit 4. The valid data detector 5 may be similarly used when detecting the valid data signal.

FIG. 9 shows a case in which the input buffer 8 is provided in FIG. 8. Input data is once received by the input buffer 8 and then input to the end data detector 7, the buffer 1 and the selector 3.
It should be noted that instead of the end data detector 7, the effective data detector 5
May be provided.

FIG. 10 shows a case where the input buffer 8 provided in FIG. 9 is provided in parallel with the buffer 1 and the selector 3. By doing so, when the data end signal and the data valid / invalid signal have one bit as shown in FIG. 7B, only that bit needs to be stored, and therefore the capacity of the input buffer 8 can be reduced.

FIG. 11 shows a case where the end data detector 7 reads the end data signal from the data after inputting it to the buffer 1. In this case, the end data detector 7 is provided in each buffer 1.
Need to be provided. The end data detector 7 can be replaced with the valid data detector 5.

Next, a third embodiment will be described. The present embodiment is a case where the output data itself includes information indicating the validity / invalidity of the data in the data width unit of each buffer. FIG. 12 shows the configuration of this embodiment. Each buffer 11 has a bit number that is k bits larger than the input data width.
Indicates whether the data in 11 is valid or invalid. The invalid data generator 12 is the same as that in FIG. 1, and the selector 13 stuffs the input data or the invalid data from the invalid data generator 12 after the upper k bits of the buffer 11 or from the upper bits, and vacates the lower k bits. Input to buffer 11 in the state. Based on the data valid signal, the control circuit 4 attaches information indicating whether the data of the buffer 11 is valid data or invalid data with k bits of the buffer 11 and outputs it. In addition, also in this embodiment, FIGS. 2, 3, 5, 5, 6, 7, 8, 9, 10 and 11.
The technology described in Section 1 can be applied.

FIG. 13 is a diagram showing output data according to this embodiment. The first 1 bit of each section indicates whether the data of the section is valid data or invalid data. In the figure, 1 represents valid data and 0 represents invalid data, but the reverse is also possible.

[0065]

As is clear from the above description, according to the present invention, input data can be converted into a data width of n times and output. Even when the input data is small and the data width is not n times as wide, invalid data is added and output for the shortage.
The output data width is always the same. Further, the circuit size is reduced by using a single selector signal or by integrating the invalid data generator and the selector.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing transition states of a buffer according to the first embodiment.

FIG. 3 is a diagram showing a circuit configuration in which an invalid data generator and a selector are integrated.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment.

FIG. 5 is a diagram illustrating a data valid signal.

FIG. 6 is a diagram showing transition states of a buffer according to the second embodiment.

FIG. 7 is a diagram illustrating a case where data valid / invalid and a data end signal are embedded in data itself.

FIG. 8 is a diagram showing a case where an end data detector is provided.

9 is a diagram showing a case where an input buffer is provided in the device of FIG.

10 shows a case where the input buffer of FIG. 9 is dedicated to an end data detector.

FIG. 11 is a diagram showing a case where an end data detector is connected to a buffer.

FIG. 12 is a diagram showing a configuration of a third exemplary embodiment.

FIG. 13 is a diagram showing an example of output data of the third embodiment.

[Explanation of symbols]

 1,11 Buffer 2,12 Invalid data generator 3,13 Selector 4,14 Control circuit 5,7 Detector 6 Input buffer

Claims (20)

[Claims] 1. N buffers (1) having a data width equal to an input data width, an invalid data generator (2) generating invalid data equal to the input data width, the input data and the invalid data. A selector (3) for selecting which of the buffers (1) is to be put into, and a control circuit (4) for instructing an input to the buffer (1) and controlling the selector (3). Characteristic data width conversion buffer device. 2. N buffers (11) having a data width larger than the input data width by k bits, and an invalid data generator (12) for generating invalid data equal to the input data width.
And a selector (13) for selecting which of the buffers (11) should contain the input data and the invalid data.
And whether the data input to each of the buffers (11) is input data or invalid data is displayed by the k bits and is added to the data of each of the buffers (11).
A data width conversion buffer device comprising: a control circuit (14) for inputting an instruction to 1) and controlling the selector (13). 3. The data width according to claim 1, wherein the selector (3, 13) is configured to directly input the input data to the uppermost buffer (1, 11). Conversion buffer device. 4. The invalid data generator (2,12) and the selector (3,13) by outputting all the bits of the input data into one of the buffers (1,11) as they are or by making them invalid data. The data width conversion buffer device according to claim 1, wherein the data width conversion buffer device is integrated. 5. The input data width all bits or a part of the bits input data indicating whether the input data is valid or invalid.
A data width conversion buffer device according to any one of 1. 6. The data width conversion buffer device according to claim 5, further comprising a detector (5) for detecting a signal indicating whether the input data is valid or invalid. 7. The data width conversion buffer device according to claim 6, further comprising an input buffer (6) for inputting input data in front of the detector (5). 8. A data width buffer device according to claim 5, further comprising a detector 5 for detecting a signal indicating whether the data stored in said buffer (1, 11) is valid or invalid. 9. The data width according to claim 1, wherein all bits or a part of the bits of the input data width inputs data indicating the end of the input data. Conversion buffer device. 10. A detector (7) for detecting a signal indicating the end of input data is provided.
Data width conversion buffer device described. 11. The data width conversion buffer device according to claim 9, wherein an input buffer (6) for inputting input data is provided in front of the detector (7). 12. The data width conversion buffer device according to claim 9, further comprising a detector (7) for detecting a signal indicating the end of the data stored in said buffer (1, 11). 13. The input data and a signal indicating whether the input data is valid or invalid are input to the control circuit (4, 14).
A data width conversion buffer device according to any one of 1. 14. The data according to claim 1, wherein a signal indicating the end of the input data is input to the control circuit (4, 14) together with the input data. Width conversion buffer device. 15. The control circuit (4, 14), when input data is not input to all n buffers (1, 11) when a signal indicating the end of the input data is input, All the buffers that have not been input (1, 11)
15. The selector (3, 13) sequentially inputs the invalid data as a lower level of a buffer (1, 11) containing input data.
A data width conversion buffer device according to any one of 1. 16. The control circuit (4, 14) inputs invalid data to the remaining buffers (1, 11) by the selector (3, 13) when inputting data to the uppermost buffer (1, 11). When the signal indicating the end of the input data is input, all the buffers (1, 11) at that time are input. Data is output, and when all buffers (1, 11) are filled with input data, the data in all buffers (1, 11) at that time are output. A data width conversion buffer device according to any one of the above. 17. A selector signal output from the control circuit (4, 14) to the selector (3, 13) is input to the next lower buffer (1, 11) each time input data is input. The invalid data generator (2,
16. The data width conversion buffer device according to claim 15, wherein invalid data from 12) is input. 18. The buffer (1, 11) selected by the selector signal is a buffer (1, 11) designated by an input instruction signal that directs an input to the buffer (1, 11) immediately before making this selection. One lower buffer (1,11)
18. The data width conversion buffer device according to claim 17, wherein: 19. The invalid data from the invalid data generator (2, 12) is stored as output data when the input data and the input data stored in the n buffers (1, 11) are completed. N buffers (1, 11)
19. The data width conversion buffer device according to claim 15, wherein the number of buffers (1, 11) containing input data therein is output as an independent control signal. 20. A counter counts the number of buffers (1, 11) containing input data or buffers (1, 11) containing invalid data in the n buffers (1, 11). Claims 1-8, 13, 15, 1 characterized in that
The data width conversion buffer device according to any one of 6, 18, and 19.