JPH06161620A - Output simultaneous change control system - Google Patents

Abstract

PURPOSE:To provide an output simultaneous change control system reducing the effect on a power source/GND at the time of the output simultaneous driving of an IC, an LSI, etc., which are represented by a gate array. CONSTITUTION:This system has a selector 3 outputting a data input signal 1 when a polarity switch signal 5 is '0' and outputting the output signal of an inverter 2 when the signal to '1'. Caption number 11 is a data output signal where the output signal of a latch 7a is outputted to an external terminal via the output buffer 9a of an LSI and caption number 12 is a polarity information output signal where the output signal of a latch 7b is outputted to the external terminal via the output buffer 9b of the LSI. The system has a inversion number decision circuit 13 where the polarity switch signal 5 becomes '1' when the number of bits whose logical value is difficult is more than 5 bits and the signal 5 becomes '0' at the time other than that case as a result of comparison between respective bits corresponding to the signal 1 and the latch 7a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit having a group of simultaneously changing signals such as a data bus, and more particularly to a logic circuit which simultaneously outputs and changes a large number of signals in an integrated circuit such as a gate array.

[0002]

2. Description of the Related Art ICs represented by gate arrays,
In recent years, LSIs have been increasing in capacity and in number of terminals. Especially when multiple output signal terminals such as a data bus are driven at the same time due to the increase in the number of terminals, the power supply near the output signal terminals
Noise is generated in the GND, which may affect the input signal arranged near the power source / GND in which the noise is generated, which may cause a malfunction. In particular, when the simultaneous drive output signal terminals are continuously arranged, it has a great influence on the nearby power source / GND.

In such a case, a power supply / GND terminal may be added between consecutively arranged simultaneous drive output terminals, or the simultaneous drive output terminals may be dispersed and arranged in signal terminal groups having different power supply / GND terminals. By doing so, a method of reducing the influence of noise on the power supply / GND and a method of avoiding the influence of noise on the input signal by arranging an input signal vulnerable to noise away from the simultaneous drive output terminal have been adopted. .

Further, as a method of avoiding the simultaneous drive output in terms of a circuit, Japanese Patent Laid-Open No. 3-44108 and Japanese Patent Laid-Open No. 3-2.
As disclosed in Japanese Laid-Open Patent Publication No. 22518, there is a method of dividing the simultaneous drive output signals into several groups and shifting the changing points by using delay elements to reduce the influence of noise on the power supply / GND.

[0005]

When the ratio of the simultaneous drive output signal terminals to the total number of terminals of the LSI / IC is large, in the above-mentioned conventional technique, the power source / GND terminal is connected between the consecutive simultaneous drive output signal terminals. In addition, a method is adopted in which an input signal terminal that is vulnerable to noise is placed away from the simultaneous drive output signal terminal group. However, when the ratio of the simultaneous drive output signal terminals is particularly large, it becomes difficult to dispose the input signal terminals, which are vulnerable to noise, away from each other, and it becomes impossible to avoid the influence on the input signals.

Further, the method of shifting the changing point of the simultaneous drive output signal reduces the timing margin on the side of taking in the simultaneous drive output signal, and there is a problem that it cannot be applied to high speed data transfer.

An object of the present invention is to reduce the number of output signal terminals in which polarity inversion occurs at the simultaneous drive output signal terminals, thereby reducing the influence of noise on the power supply / GND near the simultaneous drive output signal terminals, and An object of the present invention is to provide a simultaneous output change control method adaptable to high-speed data transfer.

[0008]

The above problems can be solved by using any of the following means.

According to means 1, in a circuit for inputting a plurality of input signals having the same change point and outputting from a plurality of output terminals, a means for inverting the polarity of a plurality of input signals and a non-input signal for the same inverted signal. It has means capable of selectively outputting the inverted input signal, and selects the input signal of the inverted / non-inverted input signal whose polarity inversion number decreases when the signal changes at the output terminal, and the polarity of this output signal Inverted / non-inverted information is output.

On the receiving side, a correct signal can be received by inverting / non-inverting the signal based on the polarity inversion / non-inversion information.

In the means 2, a plurality of input signals having the same change point are input and, in an output circuit for outputting from a plurality of output terminals, a means for inverting the polarity of the plurality of input signals to the same,
A means for selectively outputting the same inverted input signal and a non-inverted input signal, and selecting the same inverted input signal when the H level exceeds half of the non-inverted input signal polarity,
This output signal and the polarity inversion / non-inversion information are output.

Further, the means 2 may be configured to select the same inverted input signal when the L level exceeds half of the non-inverted input signal polarity.

[0013]

When the means 1 is used, the number of polarity reversals at the time of output signal change can be limited to half or less of the number of simultaneously changing output signals in the consecutive output simultaneous changing terminals,
Since the number of signals whose polarities change at the same time is reduced, the influence on the power supply / GND near the simultaneous output change terminals is reduced.

Further, if the means 2 is used, the number of H-level signals output from the output terminals is always less than half at the output simultaneous change terminals arranged consecutively, and H to L
The number of signals that change to is less than half. Also, L
The number of signals changing from H to H is also less than half. As a result, the case where all the signals change from H to L is eliminated, and the maximum value of the influence on the power supply / GND near the simultaneous output change terminals is reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment using the means 1 of the present invention will be described below with reference to FIGS. 1, 2, 3 and 4 and Table 1.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing specific examples of the polarity switching means 4 and the bit inversion number judging circuit 13 in FIG. 1, respectively. FIG. 4 is a diagram showing the operation timing of FIG. Table 1 is a table showing a specific example of the relationship between the data input signal 1, the data output signal 11, and the polarity information output signal 12 according to this embodiment.

FIG. 1 is a block diagram showing the circuit configuration of an LSI, and 1 is a data input signal output from another circuit block (not shown), and is composed of 8 bits. 2 is an inverter that inputs the data input signal 1 and outputs the polarity inversion signal of each bit. 3 is the polarity switching signal 5
A selector which outputs the data input signal 1 when it is 0 "and an output signal of the inverter 2 when it is" 1 ", and 4 is a polarity switching means composed of the inverter 2 and the selector 3.

A specific example of the polarity switching means 4 is shown in FIG.
In the figure, one input of the exclusive OR circuit 20 is used as each bit of the data input signal 1, and the polarity switching signal 5 is commonly input to the other one input, whereby the polarity switching signal 5 is input.
If the value is "1", the polarity-inverted output of the data input signal 1 is output, and if the value is "0", the data input signal 1 is output as it is.

6 is a latch signal for controlling switching of the data output signal 11, 7a is a latch for holding the output signal of the polarity switching means 4 by the latch signal 6, 7b is a latch for holding the polarity switching signal 5 by the latch signal 6, 11 is a latch 7a
Is a data output signal output to an external terminal via the output buffer 9a of the LSI, and 12 is a polarity information output signal output from the latch 7b to an external terminal via the output buffer 9b of the LSI. .

The data output signal 11 is also composed of 8 bits like the data input signal 1, and is continuously arranged on the external terminal.

As a result of comparing the corresponding bits of the data input signal 1 and the output signal of the latch 7a, 13 indicates that the polarity switching signal 5 is "5" when the number of bits having different logical values is 5 or more.
It is a bit inversion number determination circuit that becomes "1" and otherwise becomes "0".

A specific example of the bit inversion number determination circuit 13 is shown in FIG. In the figure, reference numeral 30 is composed of eight exclusive OR circuits 32, and the data input signal 1 and the latch 7 shown in FIG.
a polarity change bit detection circuit that takes an exclusive OR between the corresponding bits of input A and input B corresponding to the output signal a,
Reference numeral 31 is composed of 56 five-input logical product circuits 33 and one 56-input logical sum circuit 34.
1 is a majority circuit that outputs "1" when the number of bits that become "1" is 5 bits or more and "0" when it is 4 bits or less. The determination output from the majority circuit 31 is shown in FIG. Of the polarity switching signal 5.

[0023]

[Table 1]

Next, the overall operation of this embodiment will be described in detail with reference to FIGS. 1 and 4 and Table 1.

As an initial state, the latch 7a and the latch 7 are
It is assumed that all bits of b are 0.

Therefore, the data output signal 11 is "0000".
0000 (00h) "and the polarity information output signal 12
Is "0".

First, the value "11111111 (FFh)" of the data input signal when N = 1 in Table 1 is input to the bit inversion number determination circuit 13 as the data input signal 1 of FIG. At this time, the output signal of the latch 7a "00000000 (00
h) ”is input, and at the timing of n1 in FIG.
The bit inversion number determination circuit 13 outputs "1" as the polarity switching signal 5. The polarity switching signal 5 is input to the latch 7b and also to the polarity switching means 4,
By the operation described above, the signal obtained by inverting the polarity of the data input signal 1 is input to the latch 7a as the output signal of the polarity switching means 4.

Thereafter, the latched signal 6 causes the latched signals 7a and 7b to be fetched and held, respectively. Further, the outputs of the latches 7a and 7b are output via the output buffers 9a and 9b,
The value "0" of the data output signal 11 at the timing of n2 in FIG.
0000000 (00h) "and polarity information output signal 12
The value "1" is output.

The operation described above is based on N = 2 shown in Table 1.
The same is repeated for the value of the data input signal of 3,
The value of the data output signal and the value of the polarity information output signal shown in the table are sequentially output from the data output signal 11 and the polarity information output signal 12. When N = 1, the polarity switching signal 5
Is "1", but when N = 2 and 3, it becomes "1" and "0" respectively, and it goes without saying that the corresponding operation is performed.

According to this embodiment, the number of polarity reversals at the time of output signal change can be set to half or less of the number of simultaneously changing output signals (that is, 4 or less than 8), and the signals whose polarities change at the same time. Since the number is reduced, it is possible to reduce the influence on the power supply / GND when the simultaneous change signals are continuously arranged at the output terminals.

In the present embodiment, the data output signal 11
Although the case where the number of bits is 8 bits has been described, the same effect can be expected even if the number of bits of each block in FIG.

Further, the data output signal 11 is the power source / GND.
In the case of dividing and arranging by dividing, by applying this embodiment for each divided unit, the same effect can be expected.

In the present embodiment, the case of the output-only terminal has been described, but in the case of the input / output terminal, the value of the data output signal 7 is another external circuit connected to the LSI shown in the present embodiment. Therefore, the configuration shown in FIG. 5 is adopted, and the data input signal 1 and the input buffer 14 are used as input signals of the bit inversion number determination circuit 13.
The same effect can be expected by using the output signal of

Next, the circuit configuration on the side receiving the data output signal 11 of FIG. 1 will be described with reference to FIG.

In FIG. 6, 40 is a data output signal 11
Corresponding to the data input signal, 41 indicates the polarity information output signal 1
A polarity information input signal corresponding to 2 and a transfer clock 42 for receiving the data input signal 40 and the polarity information input 41. 45, 46, and 47 are components 2 of the same name in FIG.
The latch 48 has the same functions as those 3 and 4, and 48 is a latch which receives the output of the polarity switching means 47 as an input and takes in by using the transfer clock 42, and this output is a data output signal 49.

The polarity switching means 47 has a polarity information input signal 41.
Is "1", an inverted polarity signal of the data input signal 40 is output, and when "0", a non-inverted polarity signal is output. Therefore, when the data input signal 40 is the signal inverted in the block of FIG. 1, since the polarity information input signal 41 is “1”, the inverted polarity signal of the data input signal 40 is output as the data output signal 49. It If the data input signal 40 is a signal that is not inverted in the block of FIG. 1, the polarity information input signal 41 is “0”, so the data output signal 4
A non-inverted polarity signal of the data input signal 40 is output to 9.

FIG. 7 shows the operation timing of FIG.

FIG. 7 shows the timing when the data output signal 11 shown in FIG. 4 and Table 1 is input as the input data signal 40 and similarly the polarity information output 12 is input as the polarity information input signal 41. At the falling timing (t1) of the transfer clock 42 in FIG.
The value of the data input signal 1 shown in FIG. 1 can be output to the data output signal 49 by taking in the output of the polarity switching means 47.

Next, an embodiment using the means 2 will be described with reference to FIGS. 8, 9, 10 and Table 2.

[0040]

[Table 2]

FIG. 8 is a block diagram of this embodiment. Figure 9
8 is a circuit diagram showing a specific example of the same polarity bit number determination circuit 63 in FIG. 8, FIG. 10 is a diagram showing the operation timing of FIG. 8, and Table 2 is a data input signal 51 and data in this embodiment. Output signal 61, polarity information output signal 62
It is a table showing the relationship.

Similar to FIG. 1, FIG. 8 is a block diagram showing the circuit configuration of the LSI. In FIG.
54, 55, 56, 57a, 57b, 59a, 59b,
Reference numerals 61 and 62 have the same functions as the components of the same name in FIG. Further, 63 receives the data input signal 51 as an input, outputs "0" to the polarity switching signal 55 when the number of "1" s of each bit of the data input signal 51 is 4 bits or less, and outputs 5 when it is 5 bits or more. Is a same polarity bit number determination circuit that outputs "1" to the polarity switching signal 55.

A specific example of the same polarity bit number determination circuit is shown in FIG. The circuit shown in the figure has the same configuration and function as the majority decision circuit 31 shown in FIG.

Next, an example of the operation of this embodiment will be described with reference to FIGS. 8 and 10 and Table 2.

In the initial state (N = 0), the latch 57
It is assumed that the bits a and the latch 57b are all "0". Therefore, the output signal 61 is "00000000 (00
h) "and the polarity information output signal 62 is also" 0 ".

First, the value "11111111 (FFh)" of the data input signal when N = 1 in Table 2 is input to the same polarity bit number determination circuit 63 as the data input signal 51 of FIG. From the operation described above, "1" is output as the polarity switching signal 55 from the same polarity bit number determination circuit 63 at the timing of n1 in FIG. This polarity switching signal 55
Is input to the latch 57b and the polarity switching means 5
4 and the data input signal 5 by the above-mentioned operation.
A signal obtained by inverting the polarity of 1 is input to the latch 57a as an output signal of the polarity switching means 54.

After this, the latch signal 56 causes the latch 57.
The input signals are respectively captured and held in the a and the latch 57b. Further, the latch 57a and the latch 5
The output of 7b is output through the respective output buffers 59a and 59b, at the timing of n2 in FIG. 10, the value "00000000 (00h)" of the data output signal 61 and the value "1" of the polarity information output signal 62. .

The operation described above is based on N = 2 shown in Table 2,
The same is repeated for the values of the data input signals 3 ... 6 and the values of the data output signal and the polarity information output signal shown in the table are sequentially output from the data output signal 61 and the polarity information output signal 62. To be done.

In the present embodiment, the data output signal 61
Although the description has been made for the case where the number of bits is 8 bits, the same effect can be expected even if the number of bits of each block is increased or decreased with other numbers of bits.

According to this embodiment, the number of polarities changing from "1" to "0" in the data output signal 61 is less than half at maximum, and similarly the number of polarities changing from "0" to "1". Is less than half. Therefore, the maximum number of bits whose polarity changes in the same direction is less than half, and there is no case where the influence on the power supply such as the change from all bits “1” to all bits “0” becomes the maximum. The maximum effect can be reduced. Also, means 1
It is possible to realize a circuit for generating the polarity switching signal 55 with a small circuit scale as compared with.

[0051]

As described in detail above, the means 1 of the present invention
According to the method, it is possible to reduce the number of polarity reversals of signals at the output terminals at the time of simultaneous output driving, and according to the means 2, the polarity change of the signals at the output terminals at the same time in the simultaneous driving of outputs in the same direction. It is possible to reduce the number. As a result, it is possible to reduce the influence of noise on the power supply / GND due to simultaneous output driving.

In this embodiment, the data output signal is inverted /
A signal for polarity information to indicate non-inversion is newly required, and the number of usable terminals is reduced as in the addition method of power supply / GND. However, unlike the power supply / GND, it is a normal signal line, so the test It can be used in combination with the signal for use, and the applicability is higher than the method of adding the power supply / GND.

[Brief description of drawings]

FIG. 1 is a block diagram of an LSI circuit configuration showing an embodiment by means 1 of the present invention.

FIG. 2 is a circuit diagram showing a specific example of the polarity switching means 4 in FIG.

3 is a circuit diagram showing a specific example of a bit inversion number determination circuit 13 in FIG.

FIG. 4 is a diagram showing the operation timing of FIG. 1;

FIG. 5 is a block diagram of an LSI circuit configuration showing another embodiment according to the means 1 of the present invention.

6 is a block diagram showing a configuration of a receiving side circuit of FIG.

FIG. 7 is a diagram showing the operation timing of FIG. 6;

FIG. 8 is a block diagram of an LSI circuit configuration showing an embodiment by means 2 of the present invention.

9 is a circuit diagram showing a specific example of the same polarity bit number determination circuit 63 in FIG.

FIG. 10 is a diagram showing the operation timing of FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Data input signal, 2 ... Inverter, 3 ... Selector, 7a, 7b ... Latch, 11 ... Data output signal, 12 ... Polarity information signal output, 13 ... Bit inversion number determination circuit, 30 ... Polarity change bit detection circuit, 31 ... majority circuit, 51 ... data input signal, 52 ... inverter, 53 ... selector, 57a, 57b ... latch, 61 ... data output signal, 62 ... polarity information signal output, 63 ... same polarity bit number judging circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hidehito Yamada Inventor Hidehito Yamada 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Information Company Hitachi Image Information Systems (72) Inventor Tomokazu Yokoyama 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Image Information System

Claims (4)

[Claims] 1. A circuit for inputting a plurality of input signals having the same change point and driving a plurality of output signals from an output terminal at the same change point, and means for inverting the polarities of the plurality of input signals and a plurality of the inverted signals. An output simultaneous circuit characterized by having means capable of selectively outputting an input signal and a plurality of non-inverted input signals, and selecting the selection circuit so that the number of polarity inversions of the plurality of output signals driven by the output terminal is reduced. Change control method. 2. A circuit for inputting a plurality of input signals having the same change point and driving a plurality of output signals from an output terminal at the same change point, and a means for inverting the polarities of the plurality of input signals and a plurality of the inverted signals. A means for selectively outputting an input signal and a plurality of non-inverted input signals is provided, and when the H level exceeds half due to the input polarity of the plurality of input signals, the inverted multiple input signals are selected, and the H level is selected. A simultaneous output change control method characterized by selecting a plurality of non-inverted input signals when the number is less than half. 3. A circuit for inputting a plurality of input signals having the same change point and driving a plurality of output signals from an output terminal at the same change point, a means for inverting the polarities of the plurality of input signals, and a plurality of the inverted signals. The input signal and a plurality of non-inverted input signals can be selectively output, and when the L level exceeds half of the polarity at the time of inputting the plurality of input signals, the inverted multiple input signals are selected and the L level is changed. A simultaneous output change control method characterized by selecting a plurality of non-inverted input signals when the number is less than half. 4. A means for holding a plurality of output signals as a method for selecting a selection circuit so as to reduce the number of polarity inversions of a plurality of output signals driven by an output terminal, according to claim 1.
Means for obtaining an exclusive OR of the signal polarities of the held multiple output signals and the signal polarities of the input signals of the plurality of input signals;
An output which is provided with means for judging the number of "1" s in the exclusive OR output, and selecting a plurality of inverted input signals when the number of "1" s is more than half or more than half. Simultaneous change control method.