JPH06152390A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to oscillate also a crystal oscillation circuit whose oscillation start voltage becomes higher than battery voltage due to manufacturing dispersion and to improve the yield of the circuit by providing a semiconductor integrated circuit with a boosting circuit and an oscillation circuit. CONSTITUTION:When the generation of a clock pulse is started in a frequency dividing circuit 13, an oscillation detecting circuit 16 detects the pulse generation and supplies a detection signal to a timer circuit 17. The circuit 17 counts up time necessary for stabilizing the output voltage V2 of the boosting circuit 15 and inverts the logical level of a timer signal from 'H' to 'L'. A power supply switching circuit 11 switches boosting voltage V2 to battery voltage V1 and outputs the voltage V1 to the crystal oscillation circuit 10. The oscillation starting voltage Vsta of the circuit 10 is 1.2V e.g. and the oscillation maintaining voltage of the circuit 10 having about 1.2V Vsta is about 1.0V, so that even when voltage supplied from the circuit 11 is dropped to about 1.5V corresponding to the V1, the circuit 10 can continuously oscillate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for a watch or the like which uses a battery as a power source, and more particularly to a semiconductor integrated circuit incorporating a crystal oscillation circuit.

[0002]

2. Description of the Related Art A block diagram of a conventional timepiece semiconductor integrated circuit is shown in FIG. This semiconductor integrated circuit has, for example, about 1.5V.
The clock pulse generated by the crystal oscillating circuit 50 is supplied to the frequency dividing circuit 51. The frequency dividing circuit 51 is composed of a plurality of frequency dividing stages. By dividing the clock pulse, each frequency dividing stage generates a clock pulse of a frequency required by the CPU 52 and the booster circuit 53. The booster circuit 53 doubles the battery voltage to generate a voltage V2 of about 3.0 V, which is supplied to the liquid crystal display drive circuit 54. The CPU 52 generates display data by arithmetic processing, and this display data is supplied to the display drive circuit 54. The display drive circuit 54 generates a display drive signal from the battery voltage V1, the boosted voltage V2, the ground voltage of 0V and the display data, and based on the display drive signal, a character corresponding to the display data is displayed on a liquid crystal display (not shown). , A graphic is displayed.

By the way, the crystal oscillation circuit 50 is generally constructed as shown in FIG. 5, and a crystal oscillator 61 is externally attached between external terminals 62 and 63. The output fout of the crystal oscillator circuit is supplied to the frequency dividing circuit 51 as the clock pulse.

By the way, the CMOS type inverter amplifier 64 used in the above crystal oscillation circuit is composed of P and N channel MOS transistors. The threshold voltage of the P and N channel MOS transistors is often manufactured with deviation from the design value. Therefore, common specifications (standards) required for all MOS transistors used in an integrated circuit including a crystal oscillation circuit are set, and the integrated circuits are selected based on this. The threshold voltage is usually 0.4 to 1.1V for both P and N channels.
Is.

FIG. 6 shows the threshold voltage specifications of the P and N channel MOS transistors, respectively, | VthP | and VthN. In the figure, a square area a indicates the range of the above specifications 0.4 to 1.1V.

[0006]

However, the specifications of the inverter amplifier used in the crystal oscillator circuit are severely limited. The factors that limit this specification will be described below. The crystal oscillating circuit starts an oscillating operation when a voltage having a value equal to or higher than the oscillation starting voltage Vsta is supplied, and after the oscillation is started, an oscillation maintaining voltage Vhold having a value lower than the Vsta is supplied to maintain the oscillation. be able to. And
ΣVth, which is the sum of Vsta and Vhold and the threshold voltage of the P and N channel MOS transistors of the inverter amplifier
There is a proportional relationship with (= | VthP | + VthN) as shown in FIG. From Figure 7, when ΣVth becomes higher, Vsta
It is understood that both Vhold and Vhold become high, and that there is always a relation of Vsta> Vhold with respect to an arbitrary ΣVth.

Therefore, Vsta is limited by the voltage value that can be supplied to the crystal oscillation circuit, and Vsta limits ΣVth. Here, when the voltage supplied to the crystal oscillation circuit 50 in FIG. 4 is about 1.5 V which is the battery voltage V1, Vsta on the spec is 1.4 V with a margin. And Vsta
When the value of ΣVth corresponding to is ΣVmax, Vsta is
When it is 1.4V, ΣVmax becomes about 1.75V.

Therefore, the threshold voltages VthN and | Vth
The specifications of P | are both shown by the area a in FIG.
A crystal oscillation circuit using an inverter amplifier whose sum ΣVth exceeds ΣVmax does not oscillate even if it is within 1.1V. Therefore, this ΣVmax is required as the specifications of the inverter amplifier used in the crystal oscillation circuit.

In FIG. 6, the straight line b is a straight line on │VthP│ + VthN = 1.75V indicating this ΣVmax. A shaded region c is a region where ΣVth exceeds ΣVmax even if both | VthP | and VthN fall within the region a, and an inverter amplifier having ΣVth corresponding to this region. The crystal oscillator circuit using is not a product because it does not oscillate at the battery voltage. Therefore, there is a problem that the yield of the semiconductor integrated circuit having the crystal oscillation circuit deteriorates.

The present invention has been made in consideration of the above circumstances, and an object thereof is to be able to oscillate even a crystal oscillating circuit in which an oscillation starting voltage is higher than a battery voltage due to variations in manufacturing. It is an object of the present invention to provide a battery-driven semiconductor integrated circuit capable of improving yield.

[0011]

A semiconductor integrated circuit according to the present invention uses a first oscillating circuit which starts oscillating when a power source voltage is applied, and an output signal of the first oscillating circuit, which is more than the power source voltage. It is characterized by including a booster circuit that outputs a high voltage and a second oscillator circuit that starts oscillation by being applied with the output voltage of the booster circuit.

[0012]

The function is to oscillate the oscillation circuit having the characteristic that the oscillation start voltage is higher than the power supply voltage.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a first embodiment circuit in which the present invention is applied to a timepiece semiconductor integrated circuit. In the figure, a crystal oscillation circuit 10 operates by a voltage supplied from a power supply switching circuit 11 and generates a clock pulse. This clock pulse is supplied to the frequency dividing circuit 13 via the clocked inverter 12. The frequency dividing circuit 13 has a plurality of frequency dividing stages, and each frequency dividing stage generates a clock pulse having a frequency required by the CPU 14, the booster circuit 15, the oscillation detecting circuit 16 and the timer circuit 17.

The booster circuit 15 boosts the battery voltage V1 based on the clock pulse supplied from the frequency divider circuit 13 to obtain V1.
Generates a higher voltage V2. This voltage V2 is supplied to the liquid crystal display drive circuit 18 and the power supply switching circuit 11. The battery potential V1 is also supplied to the liquid crystal display drive circuit 18 and the power supply switching circuit 11. The CPU 14 uses the clock pulse output from the frequency dividing circuit 13 as a synchronizing signal to perform arithmetic processing to generate display data. This display data is supplied to the liquid crystal drive circuit 18 to generate a display drive signal for displaying characters, figures and the like. The display drive signal is supplied to a liquid crystal display (not shown) to display characters, figures, and the like.

On the other hand, the oscillation detecting circuit 16 detects that a clock pulse is being output from the frequency dividing circuit 13, and the detection signal is supplied to the timer circuit 17. The timer circuit 17 generates a timer signal based on the detection signal. This timer signal is supplied to the power supply switching circuit 11 and the CR oscillation circuit 19 as a control signal. Further, the timer signal output from the timer circuit 38 is supplied to the clock input terminal of the clocked inverter 20 and the inverter 21.

The output signal of the inverter 21 is supplied to the clock input terminal of the clocked inverter 12. The CR oscillator circuit 19 uses the battery voltage V1 as a power source, its operation is controlled by the timer signal, and generates a clock pulse during operation. The clock pulse output from the CR oscillator circuit 19 is supplied to the frequency dividing circuit 13 via the clocked inverter 20.

Next, the operation of the circuit configured as described above will be described. Now, assume that the value of the battery voltage V1 is 1.5V, for example. Immediately after the battery voltage V1 is supplied to each circuit, the timer circuit 17 sets the timer signal to the "H" level. When this signal is at "H" level, clocked inverter 20
Becomes operable. In addition, the other clocked inverter 12 becomes inoperative. Further, the CR oscillating circuit 40 is in a state capable of oscillating when the timer signal is at the "H" level. Therefore, after the battery voltage V1 is supplied, when the value exceeds the oscillation start voltage Vsta (0.6 to 0.7V), CR
The oscillating circuit 19 starts the oscillating operation, and the clock pulse is supplied to the frequency dividing circuit 13 via the clocked inverter 20 in the operable state. The frequency dividing circuit 13 divides this clock pulse and outputs a clock pulse of a predetermined frequency from each frequency dividing stage. By the way, the oscillation frequency of the CR oscillation circuit 19 can be arbitrarily set by a circuit constant.
The value is determined according to the boosting efficiency of the booster circuit 15 and the frequency division value of the frequency divider circuit 13. The booster circuit 15 doubles the battery voltage V1 of 1.5V to about 3.0V by using the clock pulse output from the frequency divider circuit 13 as a control signal and outputs the voltage V2.

On the other hand, the power supply switching circuit 11 selects the voltage V2 and supplies it to the crystal oscillation circuit 10 immediately after the power is turned on. Therefore, the crystal oscillation circuit 10 starts the oscillation operation when the output voltage of the booster circuit 15 rises and becomes equal to or higher than the oscillation start voltage Vsta. Here, for example, Vsta is about 1.2V
Then, after V2 reaches this value, the crystal oscillation circuit 10 starts oscillating and generates a clock pulse.

The oscillation detection circuit 16 detects the start of generation of a clock pulse in the frequency divider circuit 13 and detects it. The detection signal is supplied to the timer circuit 17. When this detection signal is input, the timer circuit 17 counts the time required for the preset output voltage V2 of the booster circuit 15 to be sufficiently stable by counting the clock pulse from the frequency divider circuit 13. Then, when the counting of the predetermined number of clock pulses is completed, the timer circuit 17 inverts the logic level of the timer signal from "H" to "L".

When the timer signal of the timer circuit 38 changes to the "L" level, the power supply switching circuit 11 switches from the boosted voltage V2 selected so far to the battery voltage V1, and the crystal oscillation circuit 10
Output to. The oscillation start voltage Vsta of the crystal oscillation circuit 10 is 1.2 V as described above, the oscillation maintaining voltage of the crystal oscillation circuit having Vsta of this level is about 1.0 V, and the voltage supplied from the power supply switching circuit 11 is V1. The crystal oscillation circuit 10 can continue to oscillate as it is even if it is lowered to about 1.5V.

When the output signal of the timer circuit 17 becomes "L" level, the CR oscillation circuit 19 stops the oscillation operation.
Further, the clocked inverter 20 becomes inoperable, and instead the clocked inverter 12 becomes operable. Therefore, the clock pulse output from the crystal oscillation circuit 10 is supplied to the frequency dividing circuit 13 in place of the clock pulse output from the CR oscillation circuit 19 until now.

The CPU 14 operates in synchronization with the clock pulse output from the frequency dividing circuit 13 to calculate and supply display data to be input to the liquid crystal display drive circuit 18 at regular time intervals. The liquid crystal display drive circuit 18 generates a display drive signal using the supplied voltages of three kinds of values, that is, the ground line voltages of V1, V2 and 0V and the display data. Then, this display drive signal is supplied to a liquid crystal display (not shown), and characters and figures corresponding to this display drive signal are displayed.

In the circuit of this embodiment, a voltage higher than the battery voltage is supplied when the crystal oscillation circuit 10 starts the oscillation, and the battery voltage is supplied as it is after the oscillation. Therefore, if the oscillation maintaining voltage Vhold is equal to or lower than the battery voltage, the crystal oscillation circuit having the oscillation starting voltage Vsta higher than the battery voltage can also oscillate.

By the way, as described with reference to FIG. 7, when the sum ΣVth of the threshold voltages of the P and N channel MOS transistors forming the inverter amplifier used in the crystal oscillation circuit increases, the oscillation start voltage Vsta also increases. Get higher

Therefore, in the circuit of this embodiment, the upper limit of ΣVth at which the crystal oscillation circuit can oscillate is higher than that when the oscillation is started by the battery voltage. As a result, ΣVth of the inverter amplifier increases due to manufacturing variations, and a crystal oscillation circuit that could not oscillate with a battery voltage can also oscillate, and the yield of a semiconductor integrated circuit equipped with a crystal oscillation circuit improves.

FIG. 2 is a block diagram of a second embodiment circuit when the present invention is applied to a timepiece semiconductor integrated circuit. It should be noted that parts corresponding to those in FIG. In this embodiment circuit, a voltage regulator 22 and another frequency dividing circuit 23 are newly added to the embodiment circuit of FIG. 1, and the power supply switching circuit 11 and the oscillation detection circuit 1 are added.
6, timer circuit 17, clocked inverters 12, 20, and inverter 21 are removed.

The voltage regulator 22 is, for example, 1.3V.
Stable voltage V of about 1.1V from the battery voltage V1 of
1'is output. This voltage V1 'is applied to the frequency dividing circuits 13 and C.
It is supplied to the PU 14, the booster circuit 15, the liquid crystal display drive circuit 18, the CR oscillation circuit 19 and the newly added frequency dividing circuit 23. On the other hand, the crystal oscillator circuit 10 has a boosted output voltage V of the booster circuit 15.
2 is supplied. The boosted output voltage V2 is also supplied to the liquid crystal display drive circuit 18.

When the battery voltage V1 is supplied to the integrated circuit having the above structure, the voltage regulator 22 outputs a stable voltage V1 'of about 1.1V. CR oscillation circuit 19
Assuming that the oscillation start voltage Vsta is about 0.6 to 0.7 V, the battery voltage V1 is supplied and the voltage V1 'is 1.1.
By the time the voltage reaches V, the CR oscillation circuit 19 starts an oscillating operation and generates a clock pulse.

The frequency divider circuit 13 frequency-divides the clock pulse and supplies it to the booster circuit 15. The booster circuit 15 doubles the voltage V1 'of about 1.1V by using the divided clock pulse to generate a voltage V2 of about 2.2V. This voltage V2 is supplied to the crystal oscillation circuit 10 and the liquid crystal display drive circuit 18. Therefore, if the oscillation start voltage Vsta is 2.2 V or less, the crystal oscillation circuit 10 starts the oscillation operation by being supplied with this voltage V2. Here, Vsta is, for example, 1.35 V, and the crystal oscillation circuit 10 starts oscillation and generates a clock pulse.

The frequency dividing circuit 23 frequency-divides the clock pulse output from the crystal oscillation circuit 10 and supplies it to the CPU 14.
The CPU 14 uses the clock pulse from the frequency dividing circuit 23 as a synchronizing signal to calculate the display data to be supplied to the liquid crystal display drive circuit 18 at fixed time intervals. Liquid crystal display drive circuit 18
Is the supplied voltage of three values, that is, V
A display drive signal is generated using the ground line voltages of 1 ', V2, 0V and the display data. Then, characters, figures, etc. corresponding to this display drive signal are displayed on a liquid crystal display (not shown).

Also in the case of this embodiment circuit, the crystal oscillation circuit
When oscillating 10, a voltage higher than the battery voltage is supplied. Therefore, it becomes possible to oscillate the crystal oscillating circuit that did not oscillate when the battery voltage is supplied as it is, and the yield of the semiconductor integrated circuit mounting the crystal oscillating circuit improves. Further, in the circuit of this embodiment, with respect to the crystal oscillation circuit 10,
Since the voltage higher than the battery voltage is continuously supplied even after the oscillation is started, the oscillation can be maintained even when the battery voltage drops and becomes lower than the oscillation maintaining voltage of the crystal oscillation circuit 10. Therefore, the life of the battery is extended as compared with the conventional circuit that supplies the battery voltage itself to maintain the oscillation of the crystal oscillation circuit.

Next, the third embodiment will be described.
FIG. 3 is a block diagram in which the present invention is applied to a semiconductor integrated circuit for a timepiece, and the portions corresponding to those in FIG. 1 and FIG.

This embodiment circuit is different from the embodiment circuits of FIGS. 1 and 2 in that a voltage detection circuit 24, a signal switching circuit 25,
An OR gate circuit 26, an AND gate circuit 27, and a NOR gate circuit 28 are added. The voltage detection circuit 24 detects the value of the battery voltage V1 and generates a detection signal according to whether it exceeds the oscillation maintaining voltage Vhold of the crystal oscillation circuit 10. This signal is supplied to the OR gate circuit 26, the AND gate circuit 27, the NOR gate circuit 28, and the crystal oscillation circuit 10.

The oscillation detection circuit 16 detects that a clock pulse is generated in the frequency dividing circuit 23, and the detection signal is supplied to the OR gate circuit 26, the AND gate circuit 27 and the NOR gate circuit 28. The signal detection circuit 25 receives the output signal of the OR gate circuit 26 and, according to this signal, a frequency dividing circuit.
13 or the clock pulse output from the frequency divider circuit 23 is selected and supplied to the booster circuit 15. The power switching circuit 11 is the OR
Based on the output signal of the gate circuit 27, the boosted output voltage V2 and the battery voltage V1 of the booster circuit 15 are selected and output to the crystal oscillation circuit 10.

The output signal of the NOR gate circuit 28 is supplied to the voltage regulator 22, the CR oscillation circuit 19 and the frequency dividing circuit 13, and the operations of these circuits 22, 19 and 13 are NOR.
It is controlled based on the output signal of the gate circuit 28.

In such a configuration, when the battery voltage V1 of 1.5 V is supplied, the crystal oscillation circuit 10 is not operating immediately after the voltage V1 is supplied, and the frequency dividing circuit 23 outputs a clock pulse. Therefore, the output signal of the oscillation detection circuit 16 becomes "H" level. At this time, the battery voltage V1
The value of is 1.5V, and the oscillation sustaining voltage V of the crystal oscillation circuit 10
Since the voltage exceeds the hold, the output signal of the voltage detection circuit 24 becomes "L" level. At this time, the NOR gate circuit 28
Output signal becomes "L" level and voltage regulator 2
2. The CR oscillating circuit 19 and the frequency dividing circuit 13 are each in an operable state. That is, the voltage regulator 22 outputs a stable voltage V1 'which is slightly lower than the voltage V1. Upon receipt of this voltage V1', the CR oscillation circuit 19 starts an oscillating operation to generate a clock pulse. Is divided by the frequency dividing circuit 13.

On the other hand, the signal switching circuit 25 is an OR gate circuit 26.
When the output signal of is at "H" level, the divided clock pulse output from the frequency dividing circuit 13 is selected. Then, the supply of this clock pulse causes the booster circuit 15 to start operating, and the battery voltage V1 is boosted by about twice to obtain the voltage V2. The power supply switching circuit 11 raises the boosted voltage V when the output signal of the AND gate circuit 27 is at "H" level.
2 has a function of selecting the battery voltage V1 when it is at "L" level. At this time, since the output signal of the AND gate circuit 27 is at the "H" level, the power supply switching circuit 11 selectively outputs the battery voltage V1. The supply of this voltage V1 causes the crystal oscillation circuit 10 to start an oscillating operation, whereby the frequency dividing circuit 23, the CPU 14 and the liquid crystal display drive circuit 18 operate. On the other hand, when the frequency dividing circuit 23 operates and the generation of the clock pulse is detected by the oscillation detecting circuit 16, the output signal of the oscillation detecting circuit 16 becomes "L" level, which causes NO.
The output signal of the R gate circuit 28 becomes "H" level, and as a result, the voltage regulator 22, the CR oscillation circuit 19 and the frequency divider circuit 13 do not operate. In addition, the oscillation detection circuit 16
When the output signal of the OR gate circuit 26 becomes "L" level and the output signal of the OR gate circuit 26 becomes "L" level, the signal switching circuit 25 selects the clock pulse output from the frequency dividing circuit 23 instead of the frequency dividing circuit 13. To do. Therefore, after this, the booster circuit 15 operates by the output of the frequency divider circuit 23.

Next, when this value is lower than the oscillation maintaining voltage Vhold of the crystal oscillation circuit 10 when the voltage V1 is supplied,
The output signal of the oscillation detection circuit 16 becomes "H" level, the output signal of the voltage detection circuit 24 also becomes "H" level, the output signal of the NOR gate circuit 28 becomes "L" level, and the voltage regulator 22, CR oscillation circuit 19 and Each of the frequency dividing circuits 13 becomes operable. Further, since the output signal of the OR gate circuit 26 is at "H" level, the signal switching circuit 25 causes the frequency dividing circuit 13
Is selected and supplied to the booster circuit 15. Also, A
Since the output signal of the ND gate circuit 27 is at "H" level, the power supply switching circuit 11 selects the output voltage V2 of the booster circuit 15 and supplies it to the crystal oscillation circuit 10.

Therefore, the voltage regulator 22, the CR oscillator circuit 19, and the frequency divider circuit 13 continue to operate when the battery voltage V1
Is lower than the oscillation maintaining voltage Vhold of the crystal oscillation circuit 10, that is, when the output signal of the voltage detection circuit 24 is at the “H” level.

The output signal of the voltage detection circuit 24 is supplied to the crystal oscillating circuit 10 because it operates at the output voltage V2 of the booster circuit 15 whose operating voltage is higher than when operating at the battery voltage V1. This is because the current consumption is reduced by performing control so that the gm value of the internal inverter amplifier becomes smaller when the above is performed.

As described above, according to the circuit of the above embodiment, the battery can be operated even if the battery voltage V1 becomes lower than the oscillation maintaining voltage Vhold of the crystal oscillation circuit 10 and further drops to the minimum operating voltage of the CR oscillation circuit 19. It should be noted that the present invention can be implemented not only in the integrated circuit for timepieces but also in integrated circuits for other applications using the crystal oscillation circuit.

[0043]

As described above, according to the present invention, it is possible to provide a battery-powered semiconductor integrated circuit capable of oscillating even a crystal oscillating circuit whose oscillation start voltage is higher than the battery voltage due to variations in manufacturing. The yield of semiconductor integrated circuits is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional timepiece integrated circuit.

5 is a circuit diagram of a crystal oscillation circuit used in the integrated circuit of FIG.

FIG. 6 is a diagram showing the standard of threshold voltage of P and N channel MOS transistors constituting the inverter amplifier used in the crystal oscillation circuit shown in FIG. 5.

FIG. 7 is a relationship diagram of Vsta and Vhold with respect to ΣVth.

[Explanation of symbols]

10 ... Crystal oscillator circuit, 11 ... Power supply switching circuit, 13 ... Dividing circuit,
14 ... CPU, 15 ... Booster circuit, 16 ... Oscillation detection circuit, 17 ... Timer circuit, 18 ... Liquid crystal display drive circuit, 19 ... CR oscillation circuit,
22 ... Voltage regulator, 23 ... Frequency divider circuit, 24 ... Voltage detection circuit, 25 ... Signal switching circuit.

Claims (4)

[Claims] 1. A first oscillating circuit that starts to oscillate when a power supply voltage is applied, a booster circuit that outputs a voltage higher than the power supply voltage by using an output signal of the first oscillating circuit, and the booster circuit. A second oscillating circuit that starts to oscillate when the output voltage of 1. is applied to the semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, further comprising: a frequency divider circuit that divides an output signal of the first oscillator circuit and inputs the divided signal to the booster circuit. 3. A means for stopping the oscillation of the first oscillating circuit after the second oscillating circuit starts oscillating, and inputting to the frequency dividing circuit after the second oscillating circuit starts oscillating. Means for switching a signal from the output signal of the first oscillator circuit to the output signal of the second oscillator circuit; and a step of boosting the voltage applied to the second oscillator circuit after the second oscillator circuit starts oscillating. 3. The semiconductor integrated circuit according to claim 2, further comprising means for switching the output voltage of the circuit to the power supply voltage. 4. The semiconductor integrated circuit according to claim 1, further comprising: a voltage regulator which receives a power supply voltage as an input and applies a stable voltage to the first oscillation circuit.