JPH06151815A - Semiconductor device and manufacture threof - Google Patents
Semiconductor device and manufacture threofInfo
- Publication number
- JPH06151815A JPH06151815A JP32846492A JP32846492A JPH06151815A JP H06151815 A JPH06151815 A JP H06151815A JP 32846492 A JP32846492 A JP 32846492A JP 32846492 A JP32846492 A JP 32846492A JP H06151815 A JPH06151815 A JP H06151815A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- silicon substrate
- tin film
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は大規模集積回路に適する
半導体装置とその製造方法に関し、特にシリコン基板と
アルミニウム系メタル配線層との間のコンタクト部分の
構造に特徴をもつ半導体装置とその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for a large-scale integrated circuit and a method for manufacturing the same, and more particularly to a semiconductor device characterized by the structure of a contact portion between a silicon substrate and an aluminum-based metal wiring layer and the manufacturing thereof. It is about the method.
【０００２】[0002]
【従来の技術】シリコン基板を被う絶縁膜にコンタクト
ホールを設け、そのコンタクトホールを介してアルミニ
ウム又はアルミニウムに１％程度のシリコンを含有した
アルミニウム合金などにてなるメタル配線（アルミニウ
ム系配線という）をシリコン基板に接続する場合、基板
のシリコンがアルミニウム中に溶け出してスパイクを発
生し、これが拡散層をつき破る不都合が生じる。そのた
め、シリコン基板とアルミニウム系メタル配線との間に
バリアメタル層として窒化チタン（ＴｉＮ）膜を設ける
ことが行なわれている。バリアメタル層としてＴｉＮ膜
を形成するには反応性スパッタリング法が用いられてい
る。2. Description of the Related Art A metal wiring (referred to as an aluminum-based wiring) made of aluminum or an aluminum alloy containing about 1% of silicon in aluminum through a contact hole provided in an insulating film covering a silicon substrate. Is connected to a silicon substrate, the silicon of the substrate melts into aluminum to generate spikes, which inconveniently breaks through the diffusion layer. Therefore, a titanium nitride (TiN) film is provided as a barrier metal layer between the silicon substrate and the aluminum-based metal wiring. Reactive sputtering is used to form a TiN film as a barrier metal layer.
【０００３】反応性スパッタリング法により形成された
窒化チタン膜はバリア層として広く利用されているが、
チタンは酸素吸着能力が大きい材料であることから、形
成されたＴｉＮ膜は原子数で３０％程度の酸素を含み、
体積抵抗率が非常に高くなる。また、膜構造はスパッタ
膜の特徴である柱状構造であり、低密度である。柱状構
造で低密度なＴｉＮ膜は、柱状構造の間のボイドを通し
て基板のシリコンが容易に拡散することや高抵抗である
という理由から、半導体装置のシリコン基板とアルミニ
ウム系メタル配線間の拡散防止膜としては問題がある。A titanium nitride film formed by the reactive sputtering method is widely used as a barrier layer.
Since titanium is a material having a large oxygen adsorption capacity, the formed TiN film contains about 30% oxygen in atomic number,
The volume resistivity becomes very high. Further, the film structure is a columnar structure which is a characteristic of the sputtered film and has a low density. The columnar structure and low density TiN film is a diffusion prevention film between the silicon substrate of the semiconductor device and the aluminum-based metal wiring because the silicon of the substrate easily diffuses through the voids between the columnar structures and has high resistance. There is a problem as
【０００４】この問題を解決するために、従来は反応性
スパッタリング法によりＴｉＮ膜を形成する際、基板に
適当な大きさの負電圧を印加することにより、低抵抗
で、かつ高密度な微結晶粒構造のＴｉＮ膜を形成してい
る。基板に負電圧を印加すると、基板の負電圧により基
板に対して不活性気体の陽イオンが加速されて衝突し、
基板に堆積したＴｉＮに付着した酸素を選択的に脱離
し、また堆積中のＴｉＮ表面を活性化して原子の移動が
可能になるようなエネルギーを与える。そのため、基板
に印加する負電圧は、そのような作用を示すように、通
常−５０〜−３００Ｖの電圧に設定される。In order to solve this problem, conventionally, when a TiN film is formed by a reactive sputtering method, a negative voltage of an appropriate magnitude is applied to a substrate to obtain a low-resistance and high-density microcrystal. A TiN film having a grain structure is formed. When a negative voltage is applied to the substrate, the negative voltage of the substrate accelerates and collides the cations of the inert gas with the substrate,
Oxygen attached to TiN deposited on the substrate is selectively desorbed, and the TiN surface during deposition is activated to give energy that enables movement of atoms. Therefore, the negative voltage applied to the substrate is usually set to a voltage of -50 to -300V so as to exhibit such an action.
【０００５】[0005]
【発明が解決しようとする課題】基板に負電圧を印加し
てＴｉＮ膜を形成すると、アルゴンイオン粒子がＴｉＮ
膜に衝突することにより高い圧縮内部応力が発生する
（J. Vac. Sci. Technol.,A(4), 1850-1854 (1986)参
照）。また、基板に負電圧を印加しながら形成した厚さ
約１０００ÅのＴｉＮ膜は内部応力が高く、５５０℃程
度の高温でＴｉＮ膜が基板から剥離する問題がある（J.
Electrochem. Soc., Vol. 130, 1215-1218 (1983)参
照）。本発明はバリアメタル層としてのＴｉＮ膜の従来
の欠点を解決し、低応力でバリア性の高いバリア層をも
つコンタクトを備えた半導体装置と、そのコンタクトの
形成方法を提供することを目的とするものである。When a negative voltage is applied to the substrate to form a TiN film, argon ion particles are converted into TiN film.
A high compressive internal stress is generated by the collision with the membrane (see J. Vac. Sci. Technol., A (4), 1850-1854 (1986)). Further, the TiN film having a thickness of about 1000Å formed while applying a negative voltage to the substrate has a high internal stress, and there is a problem that the TiN film is separated from the substrate at a high temperature of about 550 ° C (J.
Electrochem. Soc., Vol. 130, 1215-1218 (1983)). It is an object of the present invention to solve the conventional drawbacks of a TiN film as a barrier metal layer, and to provide a semiconductor device having a contact having a barrier layer having a low stress and a high barrier property, and a method for forming the contact. It is a thing.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置で
は、シリコン基板を被う絶縁膜にシリコン基板の拡散層
上でコンタクトホールが形成され、そのコンタクトホー
ルではシリコン基板とオーミック接触を得るためのメタ
ル低抵抗層及びその上のバリアメタル層を介してアルミ
ニウム系メタル配線層が形成されており、バリアメタル
層は柱状構造の低密度な下層とその上の微結晶粒構造の
高密度な層とを少なくとも含む多層構造である。好まし
い態様では、バリアメタル層は柱状構造で低密度な下層
とその上の微結晶粒構造で高密度な層と、さらにその上
の柱状構造で低密度な層とからなる３層構造である。In a semiconductor device of the present invention, a contact hole is formed in an insulating film covering a silicon substrate on a diffusion layer of the silicon substrate, and the contact hole is used to obtain ohmic contact with the silicon substrate. An aluminum-based metal wiring layer is formed via a metal low resistance layer and a barrier metal layer thereabove, and the barrier metal layer is composed of a low-density columnar structure lower layer and a fine-grain structure high-density layer above it. It is a multi-layer structure including at least. In a preferred embodiment, the barrier metal layer has a three-layer structure including a lower layer having a columnar structure and a low density, a layer having a fine crystal grain structure and a high density thereon, and a layer having a columnar structure and a low density further thereon.
【０００７】本発明の製造方法は以下の工程（Ａ）から
（Ｇ）を含んでいる。（Ａ）不純物拡散層が形成された
シリコン基板を被う絶縁膜のうち、シリコン基板とコン
タクトを形成すべき領域にコンタクトホールを形成する
工程、（Ｂ）メタル低抵抗膜を堆積する工程、（Ｃ）そ
のメタル低抵抗膜上に、反応性スパッタリングを行な
い、柱状構造で低密度な第１層目の窒化チタン膜を堆積
する工程、（Ｄ）シリコン基板側に負電圧を印加し、チ
タンをターゲットとしたアルゴンガスと窒素ガスの雰囲
気中での反応性スパッタリングにより微結晶粒構造で高
密度な第２層目の窒化チタン膜を堆積する工程、（Ｅ）
シリコン基板側の電圧印加を停止し、チタンをターゲッ
トとしたアルゴンガスと窒素ガスの雰囲気中での反応性
スパッタリングにより柱状構造で低密度な第３層目の窒
化チタン膜を堆積する工程、（Ｆ）アルミニウム系導電
膜を堆積する工程、（Ｇ）前記導電膜、第１、第２及び
第３層目の窒化シリコン膜、並びに前記メタル低抵抗膜
をパターン化して配線とする工程。The manufacturing method of the present invention includes the following steps (A) to (G). (A) A step of forming a contact hole in a region of the insulating film covering the silicon substrate on which the impurity diffusion layer is formed to form a contact with the silicon substrate, (B) a step of depositing a metal low resistance film, C) A step of performing reactive sputtering on the metal low-resistance film to deposit a titanium nitride film of the first layer having a columnar structure and a low density, (D) applying a negative voltage to the silicon substrate side to remove titanium. A step of depositing a high-density second layer titanium nitride film having a fine crystal grain structure by reactive sputtering in a target atmosphere of argon gas and nitrogen gas, (E)
A step of stopping the voltage application on the silicon substrate side and depositing a third-layer titanium nitride film having a columnar structure and low density by reactive sputtering in an atmosphere of argon gas and nitrogen gas targeting titanium; ) A step of depositing an aluminum-based conductive film, and (G) a step of patterning the conductive film, the first, second and third silicon nitride films and the metal low resistance film to form wiring.
【０００８】[0008]
【作用】本発明の半導体装置のコンタクトでは、バリア
層の最下層が柱状構造の低密度なＴｉＮ膜で、その上に
微結晶粒構造の高密度なＴｉＮ膜を含む少なくとも２層
を含んでいるので、微結晶粒構造のＴｉＮ膜が高いバリ
ア性を有し、最下層の柱状構造のＴｉＮ膜は低応力であ
り、高温印加時にもバリア層の下側界面での膜の剥離を
防止する役割を果たす。柱状構造のＴｉＮ膜のボイドを
通って拡散したシリコンは微結晶粒構造のＴｉＮ膜で止
められる。微結晶粒構造のＴｉＮ膜の高い圧縮応力は下
側の柱状構造のＴｉＮ膜により緩和される。In the contact of the semiconductor device of the present invention, the lowermost layer of the barrier layer is a low density TiN film having a columnar structure, and at least two layers including a high density TiN film having a fine crystal grain structure are provided thereon. Therefore, the TiN film having the fine crystal grain structure has a high barrier property, and the TiN film having the columnar structure at the lowermost layer has a low stress. The role of preventing the peeling of the film at the lower interface of the barrier layer even when a high temperature is applied. Fulfill. The silicon diffused through the voids of the TiN film having the columnar structure is stopped by the TiN film having the fine crystal grain structure. The high compressive stress of the TiN film having the fine crystal grain structure is relaxed by the TiN film having the columnar structure on the lower side.
【０００９】微結晶粒構造のＴｉＮ膜の上にさらに柱状
構造で低密度なＴｉＮ膜を設けたときは、微結晶粒構造
のＴｉＮ膜の高い圧縮応力が下層の柱状構造のＴｉＮ膜
だけでなく上層の柱状構造のＴｉＮ膜によっても緩和さ
れる。柱状構造で低密度なＴｉＮ膜とするか微結晶粒構
造で高密度なＴｉＮ膜とするかは、基板側に負電圧を印
加しないか印加するかにより切り替えることができるの
で、ＴｉＮ膜の堆積では基板側への負電圧の印加のオン
・オフにより連続して両膜を積層することができる。When a TiN film having a columnar structure and a low density is further provided on the TiN film having a fine crystal grain structure, the high compressive stress of the TiN film having a fine crystal grain structure causes not only the TiN film of the lower columnar structure but also It is also relaxed by the upper columnar TiN film. Whether the columnar structure is a low-density TiN film or the microcrystalline structure is a high-density TiN film can be switched depending on whether or not a negative voltage is applied to the substrate side. Both films can be continuously laminated by turning on / off the application of the negative voltage to the substrate side.
【００１０】[0010]
【実施例】図１は第１の実施例を表わす。Ｐ型シリコン
基板１に半導体素子を構成するＮ型拡散層３１が形成さ
れており、シリコン基板１の表面を被うＳｉＯ2膜２に
は拡散層３１上にコンタクトホール３２が形成されてい
る。ＳｉＯ2膜２上からはコンタクトホール３２によっ
て露出したシリコン基板１の表面とオーミック接触をす
るためのチタン膜３が約２００Åの厚さに形成されてい
る。チタン膜３上にはシリコン基板１とアルミニウム系
配線とのバリア層として３層構造のＴｉＮバリアメタル
層４，５，６が形成されている。バリアメタル層の最下
層４は厚さが約２５０Åで、柱状構造で低密度なＴｉＮ
膜である。その上の第２層目のＴｉＮ膜５は厚さが約５
００Åで、微結晶粒構造で高密度なＴｉＮ膜であり、そ
のＴｉＮ膜５の結晶粒は直径１００〜１５０Å程度であ
る。その上の第３層目のＴｉＮ膜６は厚さが約２５０Å
で、柱状構造で低密度なＴｉＮ膜である。この３層のＴ
ｉＮ膜４，５，６上にはアルミニウム系配線７がアルミ
ニウム膜又はアルミニウムにシリコンを１％含有したア
ルミニウム合金膜により形成されている。チタン膜３、
ＴｉＮ膜４，５，６及び配線７はパターン化されてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment. An N type diffusion layer 31 forming a semiconductor element is formed on the P type silicon substrate 1, and a contact hole 32 is formed on the diffusion layer 31 in the SiO 2 film 2 covering the surface of the silicon substrate 1. A titanium film 3 for making ohmic contact with the surface of the silicon substrate 1 exposed by the contact holes 32 is formed on the SiO 2 film 2 to a thickness of about 200Å. On the titanium film 3, TiN barrier metal layers 4, 5 and 6 having a three-layer structure are formed as barrier layers between the silicon substrate 1 and aluminum-based wiring. The bottom layer 4 of the barrier metal layer has a thickness of about 250 Å and has a columnar structure and low density of TiN.
It is a film. The second TiN film 5 on the second layer has a thickness of about 5
It is a TiN film having a fine crystal grain structure and a high density, and the crystal grains of the TiN film 5 have a diameter of about 100 to 150 Å. The thickness of the third TiN film 6 on it is about 250Å
The columnar structure is a low density TiN film. This 3 layer T
Aluminum wiring 7 is formed on the iN films 4, 5 and 6 by an aluminum film or an aluminum alloy film containing 1% of silicon in aluminum. Titanium film 3,
The TiN films 4, 5, 6 and the wiring 7 are patterned.
【００１１】図１の実施例では、バリアメタル層が中間
に微結晶粒構造のＴｉＮ膜５を挾んで上下の層が柱状構
造のＴｉＮ膜４，６となっているので、柱状構造のＴｉ
Ｎ膜４，６の結晶粒界及びボイドが微結晶粒構造のＴｉ
Ｎ膜５で中断され、また微結晶粒構造のＴｉＮ膜５のバ
リア性が高いことから、上層のアルミニウム系配線７と
下層のシリコン基板１が結晶粒界を通じて拡散すること
はない。その結果、例えば６００℃で１時間の熱処理を
施した後にもアルミニウムスパイクによる接合破壊はみ
られなかった。In the embodiment shown in FIG. 1, the barrier metal layer sandwiches the TiN film 5 having a fine crystal grain structure in the middle, and the upper and lower layers are the TiN films 4 and 6 having a columnar structure.
Ti of the grain boundaries and voids of the N films 4 and 6 having a fine grain structure
Since the TiN film 5 having the fine crystal grain structure is interrupted by the N film 5 and the barrier property of the TiN film 5 is high, the upper aluminum-based wiring 7 and the lower silicon substrate 1 do not diffuse through the crystal grain boundaries. As a result, no junction breakage due to aluminum spikes was observed even after heat treatment at 600 ° C. for 1 hour.
【００１２】また、高圧縮応力をもつ微結晶粒構造のＴ
ｉＮ膜５が低応力の柱状構造のＴｉＮ膜４，６により両
側から挾まれており、バリアメタル層と上層のアルミニ
ウム系配線７との界面及び下層のチタン膜３との界面は
それぞれ応力の低い柱状構造のＴｉＮ層４，６で接して
いるので、６００℃１時間の高温処理によっても膜の剥
離もなかった。Further, the T having a fine grain structure having a high compressive stress is used.
The iN film 5 is sandwiched by the TiN films 4 and 6 having a low stress columnar structure from both sides, and the interface between the barrier metal layer and the upper aluminum-based wiring 7 and the interface between the lower titanium film 3 have low stress. Since the TiN layers 4 and 6 having a columnar structure are in contact with each other, the film was not peeled off even by the high temperature treatment at 600 ° C. for 1 hour.
【００１３】図２は第２の実施例を表わす。図１の実施
例と比較すると、バリアメタル層が柱状構造の第１層目
のＴｉＮ膜４と微結晶粒構造の第２層のＴｉＮ膜５の２
層構造となっている点で相違する。膜厚は第１層目Ｔｉ
Ｎ膜４が約５００Å、第２層ＴｉＮ膜５が約５００Åで
ある。FIG. 2 shows a second embodiment. Compared to the embodiment of FIG. 1, two barrier metal layers, a first-layer TiN film 4 having a columnar structure and a second-layer TiN film 5 having a microcrystalline structure, are used.
The difference is that it has a layered structure. The film thickness is the first layer Ti
The N film 4 has a thickness of about 500Å, and the second-layer TiN film 5 has a thickness of about 500Å.
【００１４】図２の実施例においても微結晶粒構造のＴ
ｉＮ膜５が存在することによって柱状構造のＴｉＮ膜４
の結晶粒界及びボイドがアルミニウム系配線７まで到達
することなく、また微結晶粒構造のＴｉＮ膜５のバリア
性の高いことによりアルミニウム系配線７とシリコン基
板１が結晶粒界を通じて拡散することはなく、６００℃
で１時間の熱処理によってもアルミニウムスパイクによ
る接合破壊はみられなかった。しかも、図１の実施例と
同様に、微結晶粒構造のＴｉＮ膜５とチタン膜３との界
面は応力の低い柱状構造のＴｉＮ膜４で接しているた
め、６００℃で１時間の熱処理時にも応力による膜の剥
離もなかった。Also in the embodiment of FIG. 2, T having a fine crystal grain structure is used.
Due to the presence of the iN film 5, the TiN film 4 having a columnar structure is formed.
Does not reach the aluminum-based wiring 7 and the high barrier property of the TiN film 5 having the fine crystal grain structure prevents the aluminum-based wiring 7 and the silicon substrate 1 from diffusing through the crystal grain boundary. Without, 600 ℃
No joint failure due to aluminum spike was observed even after the heat treatment for 1 hour. Moreover, as in the embodiment of FIG. 1, since the interface between the TiN film 5 having the fine crystal grain structure and the titanium film 3 is in contact with the TiN film 4 having the columnar structure having a low stress, the heat treatment at 600 ° C. for 1 hour is performed. There was no peeling of the film due to stress.
【００１５】次に、図１の実施例の製造方法を図３と図
４により説明する。 （Ａ）表層にＮ型拡散層３１が形成されているＰ型シリ
コン基板１上に、ＣＶＤ法によりＳｉＯ2絶縁膜２を形
成する。 （Ｂ）ホトリソグラフィー法により絶縁膜２のＮ型拡散
層３１に対応する領域に開口３２を設ける。Next, the manufacturing method of the embodiment shown in FIG. 1 will be described with reference to FIGS. (A) The SiO 2 insulating film 2 is formed by the CVD method on the P-type silicon substrate 1 having the N-type diffusion layer 31 formed on the surface thereof. (B) An opening 32 is provided in a region of the insulating film 2 corresponding to the N-type diffusion layer 31 by a photolithography method.
【００１６】（Ｃ）この開口３２によって露出したシリ
コン基板１の表面と絶縁膜２の表面とに例えばスパッタ
リング層を用いて厚さが約２００Åのチタン膜３を堆積
する。 （Ｄ）続いて、１０-8Torr台のベースプレッシャーの真
空チャンバ内にこのシリコン基板をおき、アルゴンガス
と窒素ガスを流量比で１：１となり、全圧が３．５ｍTo
rrになるように導入し、Ｄ．Ｃ．マグネトロン法により
０．１Ｗ／ｃｍ2の直流電力をチタンターゲットに投入
することにより、第１層目の柱状構造のＴｉＮ膜４を約
５００Å／分の堆積速度で、厚さ約２５０Åに堆積す
る。この工程において、形成されるＴｉＮ膜４の柱の直
径は３００Å程度である。この反応性スパッタリング法
では、真空チャンバ内の全圧が３ｍTorr以上の圧力で成
膜すれば柱状構造のＴｉＮ膜が形成される。(C) A titanium film 3 having a thickness of about 200Å is deposited on the surface of the silicon substrate 1 and the surface of the insulating film 2 exposed by the opening 32 by using, for example, a sputtering layer. (D) Subsequently, the silicon substrate was placed in a vacuum chamber of base pressure of 10 −8 Torr level, the flow ratio of argon gas and nitrogen gas was 1: 1 and the total pressure was 3.5 mTo.
rr. C. By applying a DC power of 0.1 W / cm 2 to the titanium target by the magnetron method, the TiN film 4 having the columnar structure of the first layer is deposited to a thickness of about 250Å at a deposition rate of about 500Å / min. In this step, the diameter of the columns of the TiN film 4 formed is about 300Å. In this reactive sputtering method, if the total pressure in the vacuum chamber is 3 mTorr or more, a TiN film having a columnar structure is formed.
【００１７】（Ｅ）１層目のＴｉＮ膜４の堆積を始めて
から３０秒後に基板側に−８０Ｖの電圧の印加を開始す
る。７５秒間負電圧を印加することにより、１層目のＴ
ｉＮ膜４上に厚さが約５００Åの微結晶粒構造のＴｉＮ
膜５が堆積される。この工程で形成されるＴｉＮ膜５の
結晶粒は直径１００〜１５０Å程度である。 （Ｆ）ＴｉＮ膜５を形成するための負電圧印加を停止し
た後、引続き３０秒間スパッタリングを続けることによ
り、ＴｉＮ膜５上に柱状構造のＴｉＮ膜６が約２５０Å
の厚さに堆積する。(E) The application of a voltage of -80 V to the substrate side is started 30 seconds after the first TiN film 4 is deposited. By applying a negative voltage for 75 seconds, the first layer T
TiN having a fine crystal grain structure with a thickness of about 500Å on the iN film 4
The film 5 is deposited. The crystal grains of the TiN film 5 formed in this step have a diameter of about 100 to 150Å. (F) After the negative voltage application for forming the TiN film 5 is stopped, the TiN film 6 having a columnar structure has a TiN film 6 of about 250 Å by continuing the sputtering for 30 seconds.
Deposited to a thickness of.
【００１８】（Ｇ）ＴｉＮ膜６上にアルミニウム又はア
ルミニウムにシリコンを１％含有したアルミニウム合金
にてなるアルミニウム系導電膜７を堆積する。その後、
ホトリソグラフィー法によりチタン膜３、ＴｉＮ膜６，
２，４及び導電膜７にパターン化を施して電極や配線を
形成する。(G) On the TiN film 6, an aluminum-based conductive film 7 made of aluminum or an aluminum alloy containing 1% of silicon in aluminum is deposited. afterwards,
Titanium film 3, TiN film 6 by photolithography method
The electrodes 2 and 4 and the conductive film 7 are patterned to form electrodes and wirings.
【００１９】図２の実施例を製造する方法も図１の実施
例を製造する方法と同様である。ただし、１層目ＴｉＮ
膜４の膜厚を図１のものより厚い約５００Åにするため
にＴｉＮ膜４のためのスパッタリング時間を６０秒間と
長くする点及び、３層目のＴｉＮ膜６を設けないことか
らそのためのスパッタリング工程が不要になる点で異な
っている。The method of manufacturing the embodiment of FIG. 2 is similar to the method of manufacturing the embodiment of FIG. However, the first layer TiN
In order to make the film thickness of the film 4 thicker than that of FIG. The difference is that the process is unnecessary.
【００２０】図３及び図４の製造方法では、バリアメタ
ル層を形成する工程では１層目のＴｉＮ膜４を堆積した
後、半導体基板をチャンバから取り出すことなく連続し
て２層目のＴｉＮ膜５を堆積することができ、さらに３
層目のＴｉＮ膜６を設けるときはそれも基板をチャンバ
から取り出すことなく連続して堆積することができるの
で、ＴｉＮ膜４とＴｉＮ膜５の間、ＴｉＮ膜５とＴｉＮ
膜６の間に自然酸化膜が形成されることはなく、電極や
配線の抵抗が不必要に増加することがない。その結果、
例えば０．３μｍサイズのコンタクトホールにおける接
触抵抗も１００Ω以下の低い値であった。In the manufacturing method of FIGS. 3 and 4, in the step of forming the barrier metal layer, after depositing the first-layer TiN film 4, the second-layer TiN film is continuously removed without taking out the semiconductor substrate from the chamber. 5 can be deposited, 3 more
Since the TiN film 6 of the layer can be continuously deposited without taking out the substrate from the chamber, the TiN film 5 and the TiN film 5 and the TiN film 5 can be continuously deposited.
No natural oxide film is formed between the films 6, and the resistance of the electrodes and wiring does not unnecessarily increase. as a result,
For example, the contact resistance in a 0.3 μm size contact hole was a low value of 100Ω or less.
【００２１】また、反応性スパッタリング法によるＴｉ
Ｎ膜形成に使用するアルゴンと窒素以外のガスを供給し
て結晶粒界及びボイドを遮断する層を形成する必要がな
いことからも、電極配線の抵抗増加を招くことがない。
実施例ではバリアメタル層が３層及び２層である場合に
ついて示しているが、４層以上の場合も柱状構造のＴｉ
Ｎ膜と微結晶粒構造のＴｉＮ膜を交互に積層することに
より、シリコンの粒界拡散を抑制し、かつ圧縮応力を緩
和したバリアメタル層とすることができる。Ti produced by the reactive sputtering method is also used.
Since it is not necessary to supply a gas other than argon and nitrogen used for forming the N film to form a layer that blocks the crystal grain boundaries and the voids, the resistance of the electrode wiring does not increase.
Although the examples show the cases where the barrier metal layer is composed of three layers and two layers, Ti having a columnar structure is also formed in the case of four layers or more.
By alternately laminating the N films and the TiN films having a fine crystal grain structure, it is possible to obtain a barrier metal layer in which the grain boundary diffusion of silicon is suppressed and the compressive stress is relaxed.
【００２２】[0022]
【発明の効果】本発明ではシリコン基板とアルミニウム
系メタル配線との間のバリアメタル層として、柱状構造
の低密度な下層ＴｉＮ膜とその上の微結晶粒構造の高密
度なＴｉＮ膜とを少なくとも含む多層構造としたので、
柱状構造のＴｉＮ膜の結晶粒界及びボイドが微結晶粒構
造のＴｉＮ膜で中断され、また微結晶粒構造のＴｉＮ膜
のバリア性が高いことから、上層のアルミニウム系配線
と下層のシリコン基板が結晶粒界を通じて拡散すること
がなくなり、その結果、例えば６００℃で１時間の熱処
理を施した後にもアルミニウムスパイクによる接合破壊
はみられなかった。According to the present invention, as the barrier metal layer between the silicon substrate and the aluminum-based metal wiring, at least a low-density lower-layer TiN film having a columnar structure and a high-density TiN film having a fine crystal grain structure thereon are formed. Because it has a multilayer structure including
Since the crystal grain boundaries and voids of the columnar TiN film are interrupted by the fine crystal grain TiN film and the TiN film having the fine crystal grain structure has a high barrier property, the upper aluminum-based wiring and the lower silicon substrate are It did not diffuse through the grain boundaries, and as a result, no junction breakage due to aluminum spikes was observed even after heat treatment at 600 ° C. for 1 hour.
【００２３】また、高圧縮応力をもつ微結晶粒構造のＴ
ｉＮ膜の少なくとも下層には低応力の柱状構造のＴｉＮ
膜が存在するので、６００℃１時間の高温処理によって
もバリア層の剥離もなかった。高圧縮応力をもつ微結晶
粒構造のＴｉＮ膜の上下を低応力の柱状構造のＴｉＮ膜
で挾む構造にすることにより、さらに応力を緩和するこ
とができる。Further, the T having a fine grain structure having a high compressive stress is used.
At least the lower layer of the iN film has a low stress columnar structure TiN.
Since the film was present, the barrier layer was not peeled off even by the high temperature treatment at 600 ° C. for 1 hour. The stress can be further alleviated by forming a structure in which the TiN film having a fine crystal grain structure having a high compressive stress is sandwiched between the TiN film having a columnar structure having a low stress.
【図１】一実施例を示す要部断面図である。FIG. 1 is a sectional view of an essential part showing an embodiment.
【図２】他の実施例を示す要部断面図である。FIG. 2 is a cross-sectional view of an essential part showing another embodiment.
【図３】一実施例の製造方法を示す工程前半の断面図で
ある。FIG. 3 is a cross-sectional view of the first half of the steps showing the manufacturing method of the embodiment.
【図４】同実施例の製造方法を示す工程後半の断面図で
ある。FIG. 4 is a cross-sectional view of the latter half of the steps showing the manufacturing method of the embodiment.
１ Ｐ型シリコン基板 ２ 絶縁膜 ３ チタン膜 ４，６ 柱状構造のＴｉＮ膜 ５ 微結晶粒構造のＴｉＮ膜 ７ アルミニウム系配線 ３１ Ｎ型拡散層 ３２ コンタクトホール 1 P-type silicon substrate 2 Insulating film 3 Titanium film 4, 6 TiN film having a columnar structure 5 TiN film having a microcrystalline structure 7 Aluminum-based wiring 31 N-type diffusion layer 32 Contact hole
Claims (3)
板の拡散層上でコンタクトホールが形成され、そのコン
タクトホールではシリコン基板とオーミック接触を得る
ためのメタル低抵抗層及びその上のバリアメタル層を介
してアルミニウム系メタル配線層が形成されており、前
記バリアメタル層は柱状構造の低密度な下層とその上の
微結晶粒構造の高密度な層とを少なくとも含む多層構造
であることを特徴とする半導体装置。1. A contact hole is formed in an insulating film covering a silicon substrate on a diffusion layer of the silicon substrate, and in the contact hole, a metal low resistance layer for obtaining ohmic contact with the silicon substrate and a barrier metal layer thereon. An aluminum-based metal wiring layer is formed through the barrier metal layer, and the barrier metal layer has a multi-layer structure including at least a lower layer having a columnar structure and a higher layer having a fine crystal grain structure on the lower layer. Semiconductor device.
な下層とその上の微結晶粒構造で高密度な層と、さらに
その上の柱状構造で低密度な層とからなる３層構造であ
る請求項１に記載の半導体装置。2. The barrier metal layer has a three-layer structure including a lower layer having a columnar structure and a lower density, a layer having a fine crystal grain structure and a higher density thereon, and a layer having a columnar structure and a lower density thereon. The semiconductor device according to claim 1.
リコン基板とのコンタクトを形成することを特徴とする
半導体装置の製造方法。 （Ａ）不純物拡散層が形成されたシリコン基板を被う絶
縁膜のうち、シリコン基板とコンタクトを形成すべき領
域にコンタクトホールを形成する工程、（Ｂ）メタル低
抵抗膜を堆積する工程、（Ｃ）そのメタル低抵抗膜上
に、反応性スパッタリングを行ない、柱状構造で低密度
な第１層目の窒化チタン膜を堆積する工程、（Ｄ）シリ
コン基板側に負電圧を印加し、チタンをターゲットとし
たアルゴンガスと窒素ガスの雰囲気中での反応性スパッ
タリングにより微結晶粒構造で高密度な第２層目の窒化
チタン膜を堆積する工程、（Ｅ）シリコン基板側の電圧
印加を停止し、チタンをターゲットとしたアルゴンガス
と窒素ガスの雰囲気中での反応性スパッタリングにより
柱状構造で低密度な第３層目の窒化チタン膜を堆積する
工程、（Ｆ）アルミニウム系導電膜を堆積する工程、
（Ｇ）前記導電膜、第１、第２及び第３層目の窒化シリ
コン膜、並びに前記メタル低抵抗膜をパターン化して配
線とする工程。3. A method of manufacturing a semiconductor device, which comprises forming a contact with a silicon substrate by including the following steps (A) to (G). (A) A step of forming a contact hole in a region of the insulating film covering the silicon substrate on which the impurity diffusion layer is formed to form a contact with the silicon substrate, (B) a step of depositing a metal low resistance film, C) A step of performing reactive sputtering on the metal low-resistance film to deposit a titanium nitride film of the first layer having a columnar structure and a low density, (D) applying a negative voltage to the silicon substrate side to remove titanium. A step of depositing a high-density second layer titanium nitride film having a fine crystal grain structure by reactive sputtering in a target atmosphere of argon gas and nitrogen gas, (E) stopping the voltage application on the silicon substrate side. A step of depositing a low density third layer titanium nitride film having a columnar structure by reactive sputtering in an atmosphere of argon gas and nitrogen gas targeting titanium, (F) aluminum Depositing a um based conductive film,
(G) A step of patterning the conductive film, the silicon nitride films of the first, second and third layers, and the metal low resistance film into wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32846492A JPH06151815A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture threof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32846492A JPH06151815A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture threof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151815A true JPH06151815A (en) | 1994-05-31 |
Family
ID=18210564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32846492A Pending JPH06151815A (en) | 1992-11-13 | 1992-11-13 | Semiconductor device and manufacture threof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151815A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0697729A2 (en) * | 1994-08-18 | 1996-02-21 | Oki Electric Industry Co., Ltd. | Contact structure using barrier metal and method of manufacturing the same |
| US5763948A (en) * | 1994-09-22 | 1998-06-09 | Sony Corporation | Semiconductor apparatus including a tin barrier layer having a (III) crystal lattice direction |
| US5880526A (en) * | 1996-04-15 | 1999-03-09 | Tokyo Electron Limited | Barrier metal layer |
| US6066891A (en) * | 1994-04-28 | 2000-05-23 | Nippondenso Co., Ltd | Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
| JP2006116837A (en) * | 2004-10-22 | 2006-05-11 | Sony Corp | Liquid discharging head, liquid discharging apparatus and manufacturing method for liquid discharging head |
| JP2006237394A (en) * | 2005-02-25 | 2006-09-07 | Rohm Co Ltd | Semiconductor device and its fabrication process |
| JP2010209465A (en) * | 2009-02-20 | 2010-09-24 | Asm Internatl Nv | Protection of conductor from oxidation in deposition chamber |
| US7812452B2 (en) | 2006-09-11 | 2010-10-12 | Oki Semiconductor Co., Ltd. | Semiconductor device having barrier layer comprised of dissimilar materials, and method for fabricating the same |
| JP2010267899A (en) * | 2009-05-18 | 2010-11-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| JP2011044477A (en) * | 2009-08-19 | 2011-03-03 | Stanley Electric Co Ltd | Optical semiconductor device and method for manufacturing the same |
| US7964502B2 (en) * | 2008-11-25 | 2011-06-21 | Freescale Semiconductor, Inc. | Multilayered through via |
| US8889565B2 (en) | 2009-02-13 | 2014-11-18 | Asm International N.V. | Selective removal of oxygen from metal-containing materials |
| KR20160124001A (en) | 2015-04-16 | 2016-10-26 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device and method of manufacturing same |
| JP2018050009A (en) * | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing the same |
-
1992
- 1992-11-13 JP JP32846492A patent/JPH06151815A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6066891A (en) * | 1994-04-28 | 2000-05-23 | Nippondenso Co., Ltd | Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same |
| US6348735B1 (en) | 1994-04-28 | 2002-02-19 | Nippondenso Co., Lt. | Electrode for semiconductor device and method for manufacturing same |
| EP0697729A2 (en) * | 1994-08-18 | 1996-02-21 | Oki Electric Industry Co., Ltd. | Contact structure using barrier metal and method of manufacturing the same |
| EP0697729A3 (en) * | 1994-08-18 | 1996-11-13 | Oki Electric Ind Co Ltd | Contact structure using barrier metal and method of manufacturing the same |
| US5654235A (en) * | 1994-08-18 | 1997-08-05 | Oki Electric Industry Co., Ltd. | Method of manufacturing contact structure using barrier metal |
| US5920122A (en) * | 1994-08-18 | 1999-07-06 | Oki Electric Industry Co., Ltd. | Contact structure using barrier metal and method of manufacturing the same |
| US5763948A (en) * | 1994-09-22 | 1998-06-09 | Sony Corporation | Semiconductor apparatus including a tin barrier layer having a (III) crystal lattice direction |
| US5880526A (en) * | 1996-04-15 | 1999-03-09 | Tokyo Electron Limited | Barrier metal layer |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
| US6908857B2 (en) | 1999-08-20 | 2005-06-21 | Denso Corporation | Method of manufacturing semiconductor device |
| JP2006116837A (en) * | 2004-10-22 | 2006-05-11 | Sony Corp | Liquid discharging head, liquid discharging apparatus and manufacturing method for liquid discharging head |
| JP4661162B2 (en) * | 2004-10-22 | 2011-03-30 | ソニー株式会社 | Liquid discharge head, liquid discharge apparatus, and method of manufacturing liquid discharge head |
| JP2006237394A (en) * | 2005-02-25 | 2006-09-07 | Rohm Co Ltd | Semiconductor device and its fabrication process |
| US7812452B2 (en) | 2006-09-11 | 2010-10-12 | Oki Semiconductor Co., Ltd. | Semiconductor device having barrier layer comprised of dissimilar materials, and method for fabricating the same |
| US7964502B2 (en) * | 2008-11-25 | 2011-06-21 | Freescale Semiconductor, Inc. | Multilayered through via |
| US8178950B2 (en) | 2008-11-25 | 2012-05-15 | Freescale Semiconductor, Inc. | Multilayered through a via |
| US8889565B2 (en) | 2009-02-13 | 2014-11-18 | Asm International N.V. | Selective removal of oxygen from metal-containing materials |
| JP2010209465A (en) * | 2009-02-20 | 2010-09-24 | Asm Internatl Nv | Protection of conductor from oxidation in deposition chamber |
| JP2010267899A (en) * | 2009-05-18 | 2010-11-25 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| JP2011044477A (en) * | 2009-08-19 | 2011-03-03 | Stanley Electric Co Ltd | Optical semiconductor device and method for manufacturing the same |
| US8597969B2 (en) | 2009-08-19 | 2013-12-03 | Stanley Electric Co., Ltd. | Manufacturing method for optical semiconductor device having metal body including at least one metal layer having triple structure with coarse portion sandwiched by tight portions of a same material as coarse portion |
| KR20160124001A (en) | 2015-04-16 | 2016-10-26 | 르네사스 일렉트로닉스 가부시키가이샤 | Semiconductor device and method of manufacturing same |
| JP2018050009A (en) * | 2016-09-23 | 2018-03-29 | 東芝メモリ株式会社 | Semiconductor device and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH06151815A (en) | Semiconductor device and manufacture threof | |
| JP3353727B2 (en) | Method for forming wiring structure of semiconductor device | |
| JPH08232080A (en) | New tungsten welding process | |
| JPH07221181A (en) | Formation of metal wiring of semiconductor element | |
| JP3328359B2 (en) | Method for manufacturing semiconductor device | |
| JP2001176875A (en) | Semiconductor device | |
| JP3447922B2 (en) | Capacitive element and method of manufacturing the same | |
| JPH0594990A (en) | Manufacture of multilayer interconnection | |
| JPH04256313A (en) | Manufacture of semiconductor device | |
| JPH06140401A (en) | Integrated circuit device | |
| JP3329148B2 (en) | Wiring formation method | |
| JP3339901B2 (en) | Semiconductor device having a multilayer wiring structure and method of manufacturing the same | |
| JPH02235372A (en) | Semiconductor device and its manufacture | |
| JPH065544A (en) | Manufacture of semiconductor device | |
| JPH05129223A (en) | Manufacture of semiconductor device | |
| JP3518110B2 (en) | Multi-layer wiring formation method | |
| JPH0472733A (en) | Manufacture of semiconductor device | |
| JPH0235731A (en) | Manufacture of semiconductor device | |
| JPH06318591A (en) | Wiring structure of semiconductor integrated circuit | |
| JPH11284071A (en) | Semiconductor device and manufacture thereof | |
| JPS62118539A (en) | Formation of multilayer interconnection | |
| JP2003124216A (en) | Seed film for wiring and wiring method of semiconductor device | |
| JPH02125431A (en) | Semiconductor device | |
| JPH06318594A (en) | Wiring structure of semiconductor integrated circuit and its manufacture | |
| JPH04278540A (en) | Al alloy multilayered wiring structure |