JPH06151774A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device provided with intersecting connections such as an SRAM, wherein either a source region or a drain region and a valid contact region of a MOS transistor are surely and electrically connected together producing no level difference between them. CONSTITUTION:A valid contact region 6 is formed on a silicon substrate 1, a connection wiring 8 is formed on the valid contact region 6 partially overlapping a gate insulating film 3, an impurity region 10 of the same conductivity type with the valid contact region 6 is provided to the silicon substrate 1 wider than the overlap, and a source region 11 is formed in the silicon substrate 1 as joined to the impurity region 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, as in a high resistance load type static random access memory (hereinafter referred to as SRAM), a crossing connecting one gate electrode of one of two transistors to the drain region or source region of the other is mutually connected. The present invention relates to a method for manufacturing a semiconductor device having a connecting portion.

[0002]

2. Description of the Related Art In a high resistance load type SRAM or the like, the source region or the drain region of a MOS transistor which constitutes the memory cell is replaced with another MOS in the same memory cell.
When they are mutually connected to the gate electrode of the transistor, they are electrically connected via a valid contact (contact between the semiconductor layer and the metal layer). A method of manufacturing a valid contact portion of such a semiconductor device is shown in FIG.

First, as shown in FIG. 2A, for example, a LO made of a thick SiO ₂ film is formed on a silicon substrate 52, for example.
After forming the COS oxide film 53, a thin gate insulating film 54 made of, for example, SiO ₂ is formed by an oxidation method.
Then, the gate insulating film 54 is selectively removed by etching using the first mask 55.

Then, as shown in FIG. 2B, a polysilicon (or polycide formed of a layer of polysilicon and metal) layer 57 is formed as a conductive layer over the entire upper surface of the silicon substrate 52. Impurities (for example, group 5 elemental ions) are mixed in the polysilicon layer 57 to improve conductivity, and the impurities are diffused into the silicon substrate 52 from the removed portion of the gate insulating film 54, so that N ^{A +} type valid contact region 56 is formed.

Next, as shown in FIG. 2C, a second mask 58 having a predetermined pattern for forming a gate electrode and a source region or a drain region described later is applied. At this time, the opening of the second mask 58 overlaps with the valid contact region 56, which is inside by a distance W from the side face, in the region 59. This is because the source or drain region after the implantation of impurities, which will be described later, is formed into the valid contact region 56.
This is because it is electrically connected to. When the polysilicon layer 57 is etched by the second mask 58, the gate electrode 57a and the connection wiring 60 having the predetermined pattern made of the polysilicon (or polycide) layer 57 are formed.
At the same time, the silicon substrate 52 is also etched, and a step 61 is formed on the silicon substrate 52.

Further, as shown in FIG. 2 (d), the same impurities (fifth impurity) as in the formation of the valid contact region 56 are formed.
(Group element ions) are introduced into the silicon substrate 52 by an ion implantation method to form an N ⁺ -type source region or drain region (hereinafter represented by a source region) 62. As a result, the source region 62 and the valid contact region 56 are electrically connected.

After that, as shown in FIG. 2E, the whole is covered with an interlayer insulating film 63. Further, in order to connect the electrodes of each memory cell, a wiring 64 made of aluminum or the like is formed thereon.

[0008]

However, when the polysilicon layer 57 is etched using the second mask 58 as described above, the valid contact in which the opening of the second mask 58 and the gate insulating film 54 are removed. Since the region 56 overlaps with the region 59, the overlapped portion, that is, the surface of the silicon substrate 52 from which the gate insulating film 54 is removed is etched. As a result, not only the silicon substrate 52 is damaged at the time of etching to form a step, but also an element or compound other than Group 5 enters the silicon substrate 52 from the damaged portion, which deteriorates the reliability of the MOS transistor 51. Invite.

Further, there is a possibility that the wiring 64 made of aluminum or the like formed on the interlayer insulating film may be bent and broken at the step portion.

The present invention has been made in order to solve such a problem, and there is no possibility that a step portion is formed between the MOS transistor formation region and the valid contact region, and the metal film wiring may be bent and broken. It is an object of the present invention to provide a manufacturing method of a semiconductor device which does not exist.

[0011]

The manufacturing method of the present invention comprises (a)
An opening for a valid contact region is provided in a gate insulating film provided on a semiconductor substrate, and (b) a conductive layer containing an impurity is formed on the entire surface of the semiconductor substrate, and at the same time, the impurity is removed from the opening of the gate insulating film. Providing a valid contact region by diffusing into the semiconductor substrate,
(C) The gate electrode of the first transistor is formed by etching the conductive layer, and the valid contact region is completely covered with connection wiring connecting the gate electrode of the second transistor and the valid contact region. And (d) a part of the valid contact region and a part of the gate electrode of the first transistor which is open from the end of the connection wiring are formed so as to slightly overlap with the gate insulating film. Is provided, and an impurity region having the same conductivity type as that of the impurity is ion-implanted to connect with the valid contact region to provide an impurity region, and (e) the gate electrode of the first transistor and the connection wiring are used as a mask. By implanting an impurity of the same conductivity type as the impurity, the drain region of the first transistor Or a source region is provided so as to be connected to the valid contact region via the impurity region, (f) an insulating film is provided on the entire surface of the semiconductor substrate, and a metal film wiring having a predetermined pattern is further provided thereon. It is characterized by that.

[0012]

According to the present invention, the conductive layer is etched to form the gate electrode of the first transistor and the gate electrode of the second transistor and the source region or drain region of the first transistor (hereinafter, represented by the source region). When forming the connection wiring for connecting with, the conductive layer is left at least over the entire valid contact region for etching. Therefore, when the conductive layer is etched, since there is no exposed portion of the valid contact region, the valid contact region is not damaged and a step is not formed in the silicon substrate, and the silicon substrate is not contaminated through the damaged portion. further,
Before forming the source region of the first transistor, an impurity region electrically connected to the valid contact region is provided, and the source region is provided so that the impurity region and the source region are electrically connected. Therefore, the source region of the first transistor and the gate electrode of the second transistor are reliably connected.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method of manufacturing a semiconductor device of the present invention will be described with reference to the attached drawings.

FIG. 1 is a process drawing showing an embodiment of the manufacturing method of the present invention. As shown in FIG. 1A, a LOCOS insulating film 2 made of, for example, a silicon oxide film having a thickness of, for example, about 0.6 μm is formed to separate element forming regions such as MOS transistors on the silicon substrate 1. . In the MOS transistor formation portion, a silicon oxide film having a thickness of, for example, 200 Å is formed as the gate insulating film 3. Next, a first mask 4 having a shape pattern of a valid contact region, which will be described later, is provided on the entire silicon substrate 1 by coating, exposing, and developing processes such as photoresist, and a part of the gate insulating film 3 is removed by etching. Then, an opening is provided.

Next, as shown in FIG. 1B, a polysilicon (or polycide) layer is formed as the conductive layer 5 on the entire silicon substrate 1. Impurities (for example, group 5 element ions) are mixed in the conductive layer 5, and the impurities diffuse into the silicon substrate 1 through the opening of the gate insulating film 3 to form the N ⁺ -type valid contact region 6 To form.

Next, as shown in FIG. 1C, the second mask 7 is formed so that the opening is located at a position separated from the valid contact region 6 by a predetermined distance. Then, etching is performed using this second mask 7 to selectively remove the conductive layer 5, thereby forming the gate electrode 5a of the first transistor and the gate electrode (not shown) of the second transistor and the first electrode. An opening is formed by being separated into a connection wiring 8 that connects the source region 11 of the transistor. At this time, the connection wiring 8 partially overlaps the gate insulating film 3.

Next, as shown in FIG. 1D, an opening wider than the overlapping portion of the connection wiring 8 and the gate insulating film 3 is formed by a third mask 9, and a valid contact is formed in a region adjacent to the valid contact region 6. The same impurities as in the region 6 are ion-implanted through the connection wiring to form an N ⁺ type impurity region 10
To form.

Further, as shown in FIG. 1E, the third mask 9 is removed and the same impurities as those in the valid contact region 6 are implanted by, for example, an ion implantation method or the like, whereby the N ⁺ type first transistor is formed. Forming a source region 11 of.

As a result, the valid contact region 6 and the source region 11 can be electrically connected to each other without causing a step in the silicon substrate 1 due to the impurity region 10 or causing contamination from a damaged portion.

After that, an interlayer insulating film 12 is provided on the entire upper part of the MOS transistor by a normal semiconductor process such as a CVD method, and further, a metal film wiring 13 such as aluminum for connecting the electrodes of each memory cell, a protective film (not shown). And so on.

Although a silicon substrate is used as the semiconductor substrate in the above-mentioned embodiment, a semiconductor substrate other than silicon can be used. Furthermore, although a silicon oxide film is used for the LOCOS insulating film and the gate insulating film, the present invention is not limited to these.

In addition, the source region 11 and the connection wiring 8 are
Ions of Group 5 elements such as phosphorus and arsenic were used as the impurities, but in the opposite P type, if ions of Group 3 elements such as boron were used as impurities, the connection wiring was formed as in the present invention. it can. Further, although the conductive layer 5, that is, the polysilicon layer doped with impurities is used for the gate electrode 5a and the connection wiring 8, a silicide which is a compound of silicon and a metal such as tungsten may be used, and a stacked structure of polysilicon and silicide is further used. Polycide which is can also be adopted. Further, as the interlayer insulating film 12, a silicon nitride film or the like can be formed in addition to the silicon oxide film.

Further, well-known semiconductor processes are appropriately adopted for patterning the mask, etching, ion implantation and diffusion of impurities, and the like.

[0024]

According to the method of manufacturing a semiconductor device of the present invention, M
When the source region of the OS transistor is connected to the gate electrode of another MOS transistor through the valid contact region, the valid contact and the source region can be surely conducted without a step, and the manufacturing stage In the above, it is possible to obtain a highly reliable semiconductor device without damaging or contaminating the silicon substrate.

[Brief description of drawings]

FIG. 1 is a process drawing showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a process chart showing an example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Silicon Substrate 3 Gate Insulating Film 5 Conductive Layer 5a Gate Electrode 6 Valid Contact Area 8 Connection Wiring 10 Impurity Area 11 Source Area 12 Interlayer Insulation Film 13 Metal Film Wiring

Claims (1)

[Claims] 1. (a) An opening for a valid contact region is provided in a gate insulating film provided on a semiconductor substrate,
(B) forming a conductive layer containing an impurity on the entire surface of the semiconductor substrate, and at the same time providing a valid contact region by diffusing the impurity into the semiconductor substrate through an opening of the gate insulating film; and (c) the conductive layer. Forming a gate electrode of the first transistor by etching, and completely covering the valid contact region with a connection wiring connecting the gate electrode of the second transistor and the valid contact region, and the gate insulation. And a mask so that a part of the valid contact region and a part of the gate line of the first transistor from the end of the connection wiring are opened. Impurities of the same conductivity type as the impurities are ion-implanted to connect with the valid contact region and fail. (E) by implanting an impurity of the same conductivity type as the impurity with the gate electrode of the first transistor and the connection wiring as a mask, the drain region or the source region of the first transistor is A semiconductor device, which is provided so as to be connected to the valid contact region via an impurity region, (f) an insulating film is provided on the entire surface of the semiconductor substrate, and a metal film wiring having a predetermined pattern is further provided thereon. Manufacturing method.