JPH06150698A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To easily carry out an efficient test in a short period of time with simple constitution by simultaneously using plural memory circuits of the same type, operating these circuits, comparing the output results of these circuits with each other and testing. CONSTITUTION:Data and addresses for test are inputted from terminals a, c to input data forming circuits 10 and address forming counter circuits 12 in the respective LSI chips. The data for testing are inputted to the same addresses of the memory circuits 14-1, 14-2 of the same type assigned by the circuits 12 and are compared by an output data comparator circuit 16. The results of the comparison are designed to be nondefective in the case of coincidence. The test is then made with the other data. The results are decided to be defective in the case of noncoincidence. The test is then ended at the point of this time. The continuing of the test to the final address regardless of the presence or absence of the noncoincidence output and the deciding of the presence or absence of the noncoincidence output in the final are equally good. As a result, the efficient test is easily carried out in a short period of time by the simple constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a memory circuit test in which a plurality of memories of the same type are mounted in an LSI chip in a shorter time than before.
The present invention relates to a semiconductor integrated circuit which can be easily performed.

[0002]

2. Description of the Related Art In an LSI chip, as a memory circuit, an embedded memory circuit designed in advance as a single memory circuit, or in response to a user's request regarding the number of words, the number of bits, an area, a shape (aspect ratio), etc. hand,
A memory circuit generated by the generator is mounted. At this time, it is often the case that a plurality of memory circuits of the same type are mounted due to restrictions on the circuits mounted.

As described above, as a circuit test method in the case where a plurality of memory circuits are mounted inside the LSI chip, conventionally, a test pattern is input from the outside of the chip to test one circuit at a time, or The method used was to provide a test circuit inside the chip and test each circuit again.

[0004]

However, the conventional test method has a problem that the test takes a long time because the test is performed one circuit at a time. Originally, a large number of patterns are necessary for rigorous testing, but this requires a very large amount of time,
Since it is unrealistic, we are testing only representative patterns, but there was a problem that it took too long.

Further, even when a plurality of memories of the same type are mounted, the same test is performed for each circuit,
Even with the same type of memory, there is a problem in that it takes test time and labor for the number of circuits.

The present invention has been made to solve the above-mentioned conventional problems. When a plurality of memory circuits of the same type are mounted in an LSI chip, the memory circuit is tested.
An object of the present invention is to provide a semiconductor integrated circuit that realizes a circuit configuration that can be effectively performed in a shorter time.

[0007]

According to the present invention, in a semiconductor integrated circuit in which a plurality of memories of the same type having the same word and bit configurations are mounted inside an LSI chip, the same input is applied to the same address of a plurality of memories. An input data generation circuit and an address generation counter circuit, which are provided at timings, and an output data comparison circuit that detects output coincidence, are provided, and if the outputs do not match, the memory circuit is tested. To make it easier
The above object is achieved.

[0008]

According to the present invention, when a plurality of memory circuits of the same type in the LSI chip are tested, the memory circuits of the same type are simultaneously used as shown in FIG. That is, at the same address in multiple same-type memories,
The same input is input by the input data generation circuit and the address generation counter circuit at the same timing, and the same data is output from the same address of the plurality of memory circuits,
The output results are compared with each other by a comparison circuit, and if they match, it is determined to be good, and if they do not match, it is determined to be defective.

Therefore, an efficient and effective test can be performed in a short time with a simple structure.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an outline of an embodiment of the present invention for the case where two memory circuits of the same type are mounted. In FIG. 2, 10 is an input data generation circuit, 12 is an address generation counter circuit, 14-1 and 1
Reference numeral 4-2 is a memory circuit of the same type (that is, the word and bit configurations are the same), and 16 is an output data comparison circuit.

Test data and addresses are input to the input data generation circuit 10 and the address generation counter circuit 12 inside the chip from terminals a and c, respectively. The test input data is transferred to the address generation counter circuit 12
Memory circuits 14-1, 14 of the same type designated by
-2 is input to the same address, the data is output from the address, and the output data comparison circuit 16 compares the data.
As a result of the comparison, it is determined that they match, and the test is performed with other data. If they do not match, the test ends at that point.

In this embodiment, the test is terminated immediately when the discrepancies occur, so that the test time is particularly short. Note that the test may be continued up to the last address regardless of the presence / absence of the mismatch output, and the presence / absence of the mismatch output may be finally determined.

Further, in FIG. 2, for the input terminal c to the address generation counter circuit 12, the address generation counter circuit 12 outputs a signal to the input data generation circuit 10.
If it is received, the terminal c can be omitted, and the number of terminals for testing can be further reduced.

In this embodiment, the memory circuit of the same type has two
Although the number of memory circuits is individually connected, the number of memory circuits is not limited to two, and it is clear that the same test can be easily performed with a plurality of two or more. Further, if the number of words and the number of bits are the same, the physical shapes (size and aspect ratio) may be different.

[0016]

As described above, according to the present invention, a plurality of memory circuits of the same type are simultaneously used to operate, and a test is executed by comparing the output results of these circuits with each other. With a simple structure, an efficient and effective test can be performed in a shorter time, and the test is simplified.

As a result of further shortening the time, there is an excellent effect that the test accuracy can be increased by increasing the number of test patterns.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a memory circuit test according to the present invention.

FIG. 2 is a block diagram showing an outline of an embodiment of the present invention.

[Explanation of symbols]

 10 ... Input data generation circuit 12 ... Address generation counter circuit 14-1, 14-2 ... Same-type memory circuit 16 ... Output data comparison circuit

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which a plurality of memories of the same type having the same word and bit configurations are mounted inside an LSI chip, an input for giving the same input to the same address of a plurality of memories at the same timing. Equipped with a data generation circuit and an address generation counter circuit, and an output data comparison circuit that detects whether the outputs from each memory match, and if the outputs do not match, the memory circuit can be easily tested by determining a failure. A semiconductor integrated circuit characterized by the above.