JPH0614526Y2 - Clock extraction circuit of receiver - Google Patents

Description

[Detailed description of the device] [Industrial applications]

The present invention relates to a clock extraction circuit used in a receiver of a multi-drop LAN (local area network) in which signals are transmitted in bursts, and particularly to simplification of the circuit configuration.

[Background technology]

The multi-drop LAN is, for example, IEEE802.4 Token Bu
s Phase-coherent modulation signal (Phase Coherent Frequenc
Coaxial LA using y shift Keying modulation signal)
There is N. It is connected in parallel to a transmission medium shared by a plurality of stations and uses the transmission medium in a time division manner. Therefore, signals are often bursty, and there is a characteristic that a no-signal state (silent state) also occurs. FIG. 3 is a block diagram of a conventional transmission / reception circuit (modem). In the figure, the connector 1 is used for connection with a transmission cable. The preamplifier 2 amplifies the signal received by the connector 1. The demodulation reception comparator 11 compares the signal output from the preamplifier 2 with a reference voltage to determine whether the signal is positive or negative, and outputs a logical level “0” or “1”. The tank circuit driver unit 12 includes a demodulation reception comparator 11
The tank circuit 13 is driven by the output of. Tank circuit 1
Reference numeral 3 is a circuit for detecting bit timing, and for example, an LC circuit or a filter using a crystal is used. The clock comparator 14 receives the sine wave signal output from the tank circuit 13 and extracts a logic signal level with a duty ratio of 50% as a clock signal. The reception logic control unit 15 converts the signal from the demodulation reception comparator 11 into the clock comparator 1.
It demodulates at the timing of the clock output from No. 4 and reports it to the upper communication control unit 30. The reception signal presence detection comparator 21 receives the output of the preamplifier 2, and the output does not change when there is no signal input exceeding the threshold value. Here, the threshold value is often set between the minimum received signal level and the zero level. The silent detection unit 22 inputs the output signal of the reception signal presence detection comparator 21, and observes the usage state of the cable. That is, when the output of the comparator 21 does not change for a certain period of time or more, it is considered silent and the transmission cable is recognized as open. This information is transmitted to the upper communication control unit 30. The higher-level communication control unit 30 performs exchange control of transmission rights (also called tokens or batons), retransmission control when a transmission error occurs, and interface with an application device based on the transmission protocol. The modulation unit 41 performs modulation based on the transmission information instructed to be transmitted by the higher-level communication control unit 30 and outputs it to the cable driver 42. The cable driver 42 level-converts the signal from the modulator 10 and outputs it to the cable. FIG. 4 is a waveform diagram of such a phase locked modulation signal,
(A) shows the received signal, (B) shows the output signal of the demodulation receiving comparator 11, and (C) shows the clock extracted by the clock comparator 14. The phase synchronous modulation signal has the following properties. There is always a level change between the bit boundary and the middle. When there is a signal of one cycle during the 1-bit time T1, it represents "1", and there is no level change at 1/4 and 3/4 from the beginning of the bit. When there is a signal of two cycles during the 1-bit time T1, it represents "0", and there is a level change at 1/4 and 3/4 from the beginning of the bit. A non-data bit has a frequency change in the middle of the bit and a level change at either 1/4 or 3/4 from the beginning of the bit. A non-data bit is used to indicate the start and end of a frame composed of a plurality of bytes. A training pattern in which data 0 and 1 are alternately arranged is arranged at the tip of the frame, which is useful for clock extraction.

[Prior art]

FIG. 5 is a block diagram showing a configuration of a conventional clock extraction circuit in a circuit for receiving a phase synchronization modulation signal. Incidentally, in FIG. 5, the same reference numerals are given to those having the same functions as those in FIG. 3, and the description thereof will be omitted. In the figure,
The mono-multi 121 generates a pulse having a width of one-quarter (T1 / 4) of one bit time, triggered by an edge of the output signal of the demodulation reception comparator 11. The first delay adjustment unit 122 inputs the output signal of the mono-multi 121, delays it for a predetermined time, and supplies it to the mono-multi 121. First
While the output signal of the delay adjustment unit 122 is H, even if an edge occurs in the output signal of the demodulation reception comparator 11, it will not be triggered. The second delay adjustment unit 123 is a monomulti 121.
Output signal is input, delayed by a predetermined time, and supplied to the tank circuit 6. The operation of the apparatus thus configured will be described below. Sixth
The figure is a waveform diagram of the output signal of each element in FIG. 5, where (B) is the demodulation reception comparator 11, (D) is the monomulti 121, (E) is the first delay adjustment unit 122, and (F) is Second delay adjustment unit 123, (G)
Indicates a tank circuit, and (C) indicates the clock extracted by the clock comparator 14. The mono-multi 121 extracts twice the frequency from the 1-bit time signal extracted by the demodulation reception comparator 11. The first delay adjustment unit 122 sends a signal for the level transition in the non-data bit so that the mono-multi 121 is not triggered. The second delay adjustment unit 123 delays the signal output from the monomulti 121 by a predetermined phase. The tank circuit 6 extracts a sine wave from the rectangular wave, compares it with the zero level by the clock comparator 14, and sends the extraction clock having a half cycle of one bit time to the reception logic control unit 15.

[Problems to be solved by the device]

However, the conventional device has a plurality of delay adjusting units 122 and 123, which causes a problem of increasing the number of parts and the adjusting man-hour. Further, in the case of high-speed communication such as 10 Mbps, an expensive element such as ECL that operates at high speed is used as the logic element, or when the logic is configured by TTL, the output signal of the first delay adjustment unit 122 Therefore, there is a problem that it is not easy to mask the edges. The present invention solves such a problem, and provides a clock extraction circuit of a receiving device which simplifies the configuration by providing a single delay adjustment unit and can operate even a relatively slow-moving element such as TTL. With the goal.

[Means for Solving the Problems]

The present invention which achieves such an object is provided with a demodulation reception comparator (11) having a threshold value corresponding to a zero level input, which receives a phase synchronization modulation signal of a transmission cable in which a signal is transmitted in a burst. , A tank circuit (16) that generates a sine wave for extracting bit timing from the output signal of the demodulation reception comparator, the output signal of the tank circuit, and a threshold value corresponding to a state in which the tank circuit is not driven. Compared with the voltage, the duty ratio is 50%
Clock comparator that outputs the clock signal of
7) and a reception logic control unit (19) for extracting information from the signal output from the demodulation reception comparator at a timing of a predetermined clock signal, wherein the phase-locked modulation signal has a bit boundary. There is always a level change in the middle, and when there is a signal of one cycle during 1 bit time T1, it represents "1" and 2 during 1 bit time T1.
When there is a periodic signal, it represents “0”, the non-data bit has a frequency change in the middle of the bit, and “0” and “1” are repeated in the training portion of the phase synchronization modulation signal. It is configured. That is, at the edge of the signal output from the demodulation reception comparator, 8 bits of the 1-bit time (T1) of the phase synchronization modulation signal are detected.
Mono-multi (12
4), a phase adjusting means (125) for inputting a signal generated by this monomulti, delaying the phase for a predetermined time and supplying it to the tank circuit, and the 1-bit time 4 extracted by the clock comparator. A frequency divider circuit (18) for inputting a clock having a period of 1/1/2, dividing the frequency by 1/2, and supplying a clock of a half (T1 / 2) of the 1-bit time to the reception logic control unit as a clock signal. And the output signal of the demodulation reception comparator and the clock signal output from the frequency dividing circuit are input, and it is compared whether the output signal level is different between the falling edge of the clock signal and the subsequent rising edge. A synchronization monitoring circuit (20) is provided. If the synchronization monitoring circuit recognizes that the sampling results are the same, and if the synchronization monitoring circuit or the frequency dividing circuit is in the training portion of the phase synchronization modulation signal, the frequency dividing circuit outputs the input clock. For the delay time of the phase adjusting means, the rising edge of the clock signal of the frequency dividing circuit is 8 times the 1-bit time of the rising edge of the output signal of the demodulation reception comparator. It is characterized in that it is delayed within a range of one-half or less.

[Action]

Each component of the present invention has the following functions. Monomulti generates a pulse signal having a width of 1/8 of 1 bit time.
The phase adjusting means sets the phase of the extracted clock to an appropriate value for the output signal of the demodulation reception comparator. The tank circuit generates a 1-bit time quadrant sine wave, and the clock comparator generates a 1-bit time quad cycle clock signal based on this signal. The frequency dividing circuit supplies a clock signal having a half cycle of one bit time to the reception logic control unit. If the synchronization monitoring circuit finds that the clock signal output from the frequency divider is not synchronized during the training period,
In order to synchronize, the dividing operation of the frequency dividing circuit is paused once to synchronize.

【Example】

The present invention will be described below with reference to the drawings. FIG. 1 is a configuration block diagram showing an embodiment of the present invention. Incidentally, in FIG. 1, those having the same functions as those in FIG. In the figure, the mono-multi 124 generates a pulse signal having a width of ⅛ of 1 bit time (T1) of the phase synchronization modulation signal at the edge of the signal output from the demodulation reception comparator 11. The phase adjusting means 125 inputs the signal generated by the monomulti 124, delays the phase for a predetermined time, and supplies it to the tank circuit 16.
The tank circuit 16 extracts a sine wave signal having a cycle of 1/4 (T1 / 4) of one bit time from the signal output from the phase adjusting means 125. The clock comparator 17 extracts from the sine wave output from the tank circuit 16 a clock signal having a duty ratio of 50% and a cycle of 1/4 of one bit time. The frequency divider circuit 18 inputs the clock extracted by the clock comparator 17, divides the frequency by 1/2, and clocks a clock (sub-bit clock) half the bit time (T1 / 2) to the reception logic controller 19. Supply as a signal. The reception logic control unit 19 demodulates the signal output from the demodulation reception comparator 11 at the timing output from the frequency dividing circuit 18, and reports it to the higher-level communication control unit 30 as necessary. The synchronization monitoring circuit 20 inputs the output signal of the demodulation reception comparator 11 and the clock signal output from the frequency dividing circuit 18, and the output signal level is different between the trailing edge of the clock signal and the trailing edge thereof. And compare. If the sampling results are the same, the frequency is not synchronized and the frequency divider circuit 18 is notified. Frequency divider 1
8 receives the training detection signal output from the reception logic control unit 19 and divides the clock by one clock only when the phase synchronization shift signal is received from the synchronization monitoring circuit 20 only during the training reception. Pause operation. The phase adjusting means 125 adjusts the phase so that the output edge of the demodulating comparator 11 is located at the center of the adjacent edges of the sub-bit clock obtained from the frequency dividing circuit 18. By doing so, even if the received signal has a large jitter, it is possible to correctly determine the synchronous state and the asynchronous state. The specific delay time of the phase adjusting means 125 is not more than 1/8 of the one-bit time zero beyond the edge of the output signal of the demodulation reception comparator 11 at the rising edge of the clock signal of the frequency dividing circuit 18. The delay is performed in the range to absorb the delay due to the circuit elements of the monomulti 124, the tank circuit 16, the comparator 17, and the frequency dividing circuit 18. The operation of the apparatus thus configured will be described below. Second
The figure is a waveform diagram of the output signal of each element of FIG. 1, where (B) is the demodulation reception comparator 11, (H) is the phase adjusting means 125, and (I).
Is the tank circuit 16, and (J) is the clock comparator 1.
7, (K) is a frequency dividing circuit 18, (L) is a synchronization abnormality display signal of the synchronization monitoring circuit 20, and (M) is a training detection signal of the reception logic control unit 19. The clock signal output from the clock comparator 17 has a unit of quarter of one bit time.
Since the clock to be extracted by 8 becomes half of one bit time, two relations can be selected as the phase state. One is synchronous and the other is asynchronous. First, the case where the training detection signal becomes H when the training pattern is sent and also becomes in an asynchronous state will be taken up. At time (a), the clock signal of the frequency dividing circuit 18 falls, but the signal level output from the demodulation reception comparator 11 is H. At the time (b), the clock signal of the frequency dividing circuit 18 rises, but the signal level output from the demodulation reception comparator 11 is H as a dependency. Therefore, at the time (C), the synchronization monitoring circuit 20 sets the synchronization abnormality display signal to H and the frequency dividing circuit 1
8 stops the frequency dividing operation for one clock with respect to the input clock. At the time (d) when this stop period ends, the synchronization monitoring circuit 20 returns the synchronization abnormality display signal to L. Then, after time (e), the state transitions to the synchronized state. In the synchronized state, during the training period, the signal level output by the demodulation reception comparator 11 is always different between the falling edge of the clock signal output by the frequency dividing circuit 18 and the subsequent rising edge. That is, when the phase synchronization modulation signal is “0”, the demodulation reception comparator 11 is provided between the falling edge (time point) of the clock signal output from the frequency dividing circuit 18 and the rising edge (time point) that follows this. Are different because the signal levels output by are L and H, respectively.
Similarly, when the phase-locked modulation signal is "1", the demodulation reception comparator is provided between the falling edge (time point H) of the clock signal output from the frequency dividing circuit 18 and the rising edge (time point R) continuous thereto. The signal levels output from 11 are H and L, respectively.
It is different because it is. Even if the synchronization monitoring circuit 20 recognizes that there is a synchronization error when entering a message, the communication is not always abnormal because there are non-data bits. In the above embodiment, the training detection signal is input to the frequency dividing circuit 18 to determine the suitability of the synchronization abnormality signal. However, the training detection signal is input to the synchronization monitoring circuit 20 side to determine whether the synchronization abnormality signal is valid. The frequency divider circuit 18 does not have to judge the characteristics.

[Effect of device]

As described above, according to the present invention, the phase adjusting means 125
Since the configuration is simplified by simplifying the above, there is a practical effect that even a relatively slow-moving means such as TTL can follow high-speed communication. Further, although the frequency dividing circuit 18 and the synchronization monitoring circuit 20 have an increased logical function, the first delay adjustment unit 122 is not necessary in manufacturing the gate array, and the edge mask function of the monomulti 121 is also unnecessary. Is much larger and has the effect of facilitating manufacturing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the apparatus shown in FIG. FIG. 3 is a conventional transmission / reception circuit using a clock extraction circuit, FIG. 4 is a waveform diagram of a phase shift synchronous modulation signal, FIG. 5 is a block diagram of a clock extraction circuit of a conventional receiver, and FIG.
The figure is a waveform diagram illustrating the operation of the apparatus of FIG. 11 ... Demodulation reception comparator, 124 ... Mono-multi, 125 ... Phase adjusting means, 16 ... Tank circuit, 1
7 ... Clock comparator, 18 ... Divider circuit, 1
9 ... Reception logic control unit, 20 ... Synchronous monitoring circuit.

Claims (1)

[Scope of utility model registration request] 1. A demodulation reception comparator (11) having a threshold value corresponding to a zero level input, to which a phase synchronization modulation signal of a transmission cable for transmitting a signal in a burst is input.
And a tank circuit (1 that generates a sine wave for extracting bit timing from the output signal of the demodulation reception comparator
6) and the output signal of this tank circuit are compared with the threshold voltage corresponding to the state where the tank circuit is not driven, and a clock comparator (17) for outputting a clock signal with a duty ratio of 50% And a reception logic control unit (19) for extracting information from a signal output from a demodulation reception comparator at a timing of a predetermined clock signal, wherein the phase-locked modulated signal is in the middle of a bit boundary. Indicates that there is always a level change, and when there is a signal of one cycle during 1 bit time T1, it represents "1" and 1 bit time T1
If there is a signal of two cycles between the two, it represents "0", the non-data bit has a frequency change in the middle of the bit, and "0", "1" in the training portion of the phase synchronization modulation signal.
Where 1/8 time of 1 bit time (T1) of the phase-locked modulation signal is generated at the edge of the signal output from the demodulation reception comparator.
A mono-multi (124) that generates a pulse signal having a width of
A phase adjusting means (125) for inputting a signal generated by this monomulti and delaying the phase for a predetermined time and supplying it to the tank circuit, and a quarter of the 1-bit time extracted by the clock comparator are provided. Input a clock to be cycled, divide it by 1/2 and divide it by half of the 1 bit time (T1 /
The frequency divider circuit (18) for supplying the clock of 2) to the reception logic control unit as a clock signal, the output signal of the demodulation reception comparator and the clock signal output from the frequency divider circuit are input, and the clock signal And a synchronization monitoring circuit (20) for comparing whether the output signal level is different between the trailing edge of the signal and the trailing edge of the trailing edge of the signal, and the synchronization monitoring circuit recognizes that the sampling results are the same. When it is recognized that the synchronization monitoring circuit or the frequency dividing circuit is in the training portion of the phase synchronization modulation signal, the frequency dividing circuit suspends the frequency dividing operation for one clock with respect to the input clock, The delay time is such that the rising edge of the clock signal of the frequency dividing circuit is 1/8 of the 1-bit time or more than the rising edge of the output signal of the demodulation reception comparator. A clock extraction circuit of a receiving device characterized by delaying in a lower range.