JPH06139071A - Parallel computers - Google Patents

Abstract

PURPOSE:To realize the data by-pass circuit of a memory access instruction in parallel computers. CONSTITUTION:A super scalar processor 20 is constituted of an instruction fetching stage 4, an instruction decoding stage 5, plural functional units 6 to 9 having pipeline structure respectively, a register file 3 to hold temporarily data to be used for executing an instruction, a memory data by-pass 10, and a data by-pass 12, and it can access the data memory 2 of the outside through a data bus 11. One functional unit is constituted of an execution stage 61, a memory access stage 62 and a write back stage 63. Thus, the data can be transferred between pipelines without waiting for the data to be written in a memory, and further, the data can be transferred to the pipeline requesting the read memory data, and the finish of a read instruction need not be waited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data bypass, in which data used in a plurality of instructions processed in parallel can be directly transferred between pipelines in a parallel computer, and more particularly to a data bypass of a memory access instruction. Regarding bypass.

[0002]

2. Description of the Related Art "Superscalar" is known as one of the architectures for increasing the processing speed of a parallel computer. In superscalar, an instruction that can be processed simultaneously is detected from a plurality of given instructions, and the detected instruction is processed simultaneously using a plurality of pipelines.

FIG. 14 is a block diagram of a superscalar processor showing the background of the present invention. The configuration will be described below. The superscalar 20 is an instruction fetch stage 4 for fetching a plurality of instructions stored in the instruction memory 1.
An instruction decode stage 5 for decoding the instruction fetched in the instruction fetch stage 4, a plurality of functional units 6 to 9 each having a pipeline structure, and temporarily holding data used for processing the instruction. Register file 3 for

The functional units 6 to 9 can access the external data memory 2 via the data bus 11. The register file 3 is composed of RAM,
It is accessed from the functional units 6-9.

The instruction fetch stage 4 has a program counter, and supplies the address signal generated from the program counter to the instruction memory 1. A plurality of instructions designated by a given address signal are stored in the instruction memory 1
Are fetched from the CPU and sent to the instruction decode stage 5.

The instruction decode stage 5 includes an instruction memory 1
Decode multiple instructions received from. By decoding the instruction, an instruction that can be simultaneously processed is detected from a plurality of given instructions. In addition to this, in the instruction decoding stage 5, the functional units 6 to 9 read the data used for processing the given instruction from the register file 3 and give the read data to the functional units 6 to 9.

The functional units 6, 7, 8 and 9 each have a pipeline structure. Each of the four functional units includes an execute (EXC) stage 61, a memory access (MEM) stage 62, and a writeback (WB) stage 63. Generally, the execute stage 61 performs address calculations for operations and memory accesses. Further, the memory access stage 62 performs reading from the data memory 2 or writing to the data memory 2. The write back stage 63 writes the calculation result and the read data from the data memory 2 into the register file 3.

Superscalar processor 20 also operates in response to an externally applied two-phase non-overlap clock signal. FIG. 15 is a timing diagram showing an example of a two-phase non-overlap clock signal.

The operation of the superscalar processor 20 is as follows. First, the instruction decode stage 5 detects an instruction which can be simultaneously processed among a plurality of given instructions. The detected instruction is the functional unit 6 ...
9 (possibly some of the functional units 6-9). Since the functional units 6 to 9 have a pipeline structure, they can process given instructions at the same time.

FIG. 16 is a timing chart showing an example of the progress of the pipeline processing in this case. Functional units 6, 7, and 8 are pipelines PL1 and PL, respectively.
2, can be considered to form part of PL3. The instruction fetch stage 4 and the instruction decode stage 5 are components of any pipeline.

It is assumed that all the instructions 11, 12 and 13 can be processed at the same time, and the pipelines PL1 and PL respectively.
2, PL3.

Pipelines PL1, PL2, and PL3
So done processing IF in the instruction fetch stage 4 in the period T _1, in a period T ₂ process ID in the instruction decode stage 5 is performed. In the execution stage 61, the memory access stage 62, and the write back stage 63, execution (EXC) and memory access (M) are performed in the periods T ₃ , T ₄ , and T ₅ , respectively.
EM) and write back (WB) processing is performed.

[0013]

However, in the following cases, a problem arises from the viewpoint of processing time.

Now, it is assumed that the three instructions 11, 12, and 13 are a store instruction, a load instruction, and an operation instruction, respectively.
It is assumed that these are given as being processable at the same time and are processed in pipelines PL1, PL2, PL3, respectively. In addition to this, the data is
The data is stored (stored) in the memory 2, the data is read (loaded) by the processing of the instruction 12, and once written in the register file 3, the register file 3 is accessed in the instruction 13 and processing is performed using the data. Suppose you do.

In such a case, in the configuration shown in FIG. 14, the execution of the instruction 12 is not completed until the completion of the execution of the instruction 11 is waited.

FIG. 17 is a timing diagram showing how instructions 11, 12, and 13 are processed. First, the instruction 11 is executed, and the processing ends. That is done processing IF in the instruction fetch stage 4 in the period T _1, in a period T ₂ process ID in the instruction decode stage 5 is performed. Then, in the periods T ₃ , T ₄ , and T ₅ , the execution stage 61, the memory access stage 62, and
Processing EXC, ME in write-back stage 63
M and WB are executed.

On the other hand, in the period T ₁ , the pipeline PL2 for the instruction 11 in the pipeline PL2
In 3, the processing IF of the instruction fetch stage 4 for the instruction 12 is performed. Furthermore, in the period T ₂ ,
The process ID in the instruction decode stage 5 is performed for the instruction 11 in the pipeline PL2 and for the instruction 12 in the pipeline PL3.

However, the execution of the instruction 12 is stopped in the periods T ₄ and T ₅ , and the execution of the instruction 13 is stopped in the periods T _{3 to} T ₈ . This is because the instruction 12 uses the data stored in the data memory 2 by the execution of the instruction 11 as described above, and thus the instruction 12 cannot be executed until the execution of the instruction 11 is completed.
Is to use the data read from the data memory 2 by the instruction 12, the instruction 13 cannot be executed unless the execution of the instruction 12 is completed.

That is, the pipeline PL2 is in a standby state (pipeline interlock) in the periods T ₄ and T ₅ , and the execution (EXC) is restarted in the period T ₆ . Therefore, the processes in the execution stage 61, the memory access stage 62, and the write back stage 63 are executed in the periods T ₆ , T ₇ , and T ₈ , respectively.
The pipe line PL3 is in a standby state in the period T ₃ and period T _8, the process ID in the instruction decode stage 5 in the period T ₉ is resumed.

That is, as shown in FIG.
The data read by the execution of is already obtained at the time of the period T ₃ , but since it has not been written in the data memory 2, it cannot be read unless the execution of the instruction 11 is completed. Also, the data used by the instruction 13 has not been written in the register file 3 although it has already been obtained by the process EXC in the execution stage 61 of the period T ₆ unless the execution of the instruction 12 is stopped. Therefore, it is necessary to wait for the end of the execution of the instruction 12. As a result, it took a long time to complete the execution of the instruction, and the processing capacity of the computer was lowered.

[0021]

A parallel computer according to the present invention fetches a plurality of pipeline processing execution means and a plurality of given instructions, and selects from among the fetched pipeline processing execution means a plurality of instructions. Pipeline processing execution means Pipeline processing execution means Pipeline processing execution means Instructions for inputting predetermined instructions to pipeline processing execution means and pipeline processing execution means Compare data when processing predetermined instructions A temporary data storage means for holding for a relatively short period of time, an external memory for holding data for a relatively long term, a pipeline processing execution means, and a data bypass bus for transmitting data handled by the pipeline processing execution means. Each of the pipeline process executing means has a bypass control means for determining whether to use the data transmitted by the pipeline process executing means data bypass bus.

One pipeline processing executing means In the pipeline processing executing means, the pipeline processing executing means bypass control means is one pipeline processing executing means, one pipeline processing executing means corresponding to the pipeline processing executing means. Pipeline processing execution means obtained in the instruction Memory address of the external memory and other pipeline processing execution means Other pipeline processing execution means Corresponding to pipeline processing execution means Pipeline processing execution obtained in a predetermined instruction Means: An external memory address match detection means for detecting a match with the memory address of the external memory is provided. Further, according to the output of the pipeline processing execution means external memory address match detection means, the data transmitted by the pipeline processing execution means data bypass bus is used, or the data separately loaded from the pipeline processing execution means external memory is used. It further comprises a first data providing means for selecting whether to use.

Pipeline processing execution means The external memory address match detection means outputs a match signal indicating whether or not the data is bypassed. If the pipeline processing execution means match signal indicates a match, pipeline processing execution means is executed. It further comprises an instruction changing means for changing the predetermined instruction of the means 1 into an instruction for storing the bypassed pipeline processing execution means data in the pipeline processing execution means temporary data storage means.

One pipeline processing executing means The pipeline processing executing means bypass control means in the pipeline processing executing means is one pipeline processing executing means corresponding to one pipeline processing executing means. Pipeline processing execution means obtained in the instruction Address of temporary data storage means and other pipeline processing execution means Other pipeline processing execution means Corresponding to pipeline processing execution means Pipeline processing obtained in a predetermined instruction The execution means temporary data storage means further includes temporary data storage means address coincidence detection means for detecting a match with the address of the temporary data storage means. Further, according to the output of the other pipeline processing executing means, the pipeline processing executing means, the pipeline processing executing means, the external memory address matching detecting means, and the temporary data storing means, the address matching detecting means, It further comprises a second data providing means for selecting whether to use the data transmitted by the bus.

[0025]

In the parallel computer according to the present invention, the first data providing means is responsive to the external memory address coincidence detecting means and the data written to the external memory by the access instruction to the other pipeline processing executing means to the external memory. Is directly given to the pipeline processing execution means that is executing the instruction to access the external memory at the same address. That is, the required data can be obtained without waiting for writing to the external memory.

Further, the external memory address coincidence detecting means has means for stopping an access instruction to the external memory and changing to a write instruction for the temporary data storing means when the address coincidence is detected. Therefore, useless access commands are not issued.

Further, it is judged that the necessary data has been obtained, and the data is directly supplied from another pipeline to the pipeline processing executing means which uses the read data. That is, it is possible to obtain necessary data without waiting for the data to be read from the external memory.

By the above operation, the data executed by the other pipeline processing execution means is directly received,
Instructions can be completed in a short time without waiting for the end of execution.

[0029]

FIG. 1 is a block diagram of a superscalar processor showing an embodiment of the present invention. The superscalar 20 includes an instruction fetch stage 4 for fetching a plurality of instructions stored in the instruction memory 1, an instruction decode stage 5 for decoding an instruction fetched in the instruction fetch stage 4, and a plurality of pipeline stages each having a pipeline structure. Functional units 6-9 and a register file 3 for temporarily holding data used for executing instructions.
The functional units 6 to 9 can access the external data memory 2 via the data bus 11. The register file 3 is composed of a RAM and is accessed by the functional units 6-9.

Superscalar processor 20 operates in response to an externally applied two-phase non-overlap clock signal. Since the basic operation is the same as that of the conventional superscalar processor 20 shown in FIG. 14, the description will be omitted.

Memory data bypass 10, data
The bypass 12 is provided between the respective functional units 6-9.

Via the memory data bypass 10,
The data obtained by the data providing means in the functional unit are transmitted. Further, via the data bypass 12, the memory address obtained in the functional unit executing the memory access instruction is also transmitted between the functional units 6 to 9. A signal indicating that other data has been bypassed and a storage address (address of the register file 3) of data obtained as a result of processing included in an instruction processed in each functional unit are transmitted between the functional units 6 to 9. To be done.

FIG. 2 shows a block diagram of the functional unit 6 together with the instruction decode stage 5. The other functional units 7 to 9 are similarly configured. The instruction given from the decode stage 5 includes an instruction code OP ₆ , a storage address D ₆ and two source addresses S ₁₁ and S ₁₂ , both of which are addresses of the register file 3. The source addresses S ₁₁ and S ₁₂ indicate the addresses of the register file 3 in which the data used to execute the instruction are stored.
The storage address D ₆ indicates the address of the register file 3 in which the data executed in the functional unit 6 should be stored.

The functional unit 6 executes an operation of an instruction and calculation of a memory address (address of the memory 2), an execution stage 61, a memory access stage 62 for accessing the data memory 2, and the obtained data. Write back to write data to register file 3
It consists of stage 63.

The execution stage 61 includes a memory / address comparator 90, a memory / data selector 91, an instruction changer 92, a storage register 94, and a selection circuit 97.

The memory / address comparator 90 uses the instruction OP processed by the other functional units 7 to 9 shown in FIG.
_{7 to} OP ₉ and memory addresses M _{7 to} M ₉ calculated by the operation executor 84 included in the functional units 7 to ₉ ,
And the read address M calculated by the operation executor 84 and the instruction OP ₆ being processed in the functional unit 6.
Receive ₆

Now, if the instructions OP _{7 to} OP ₉ are write instructions (store instructions), the memory addresses M _{7 to} M _{9 are} stored.
Is the write memory address. If the instruction OP ₆ is a read instruction (load instruction), the address M ₆ is a read address. Memory / address comparator 90
Compares these and outputs signals BY ₇ , BY ₈ and BY ₉ indicating the comparison result (match / mismatch). Details will be described later.

The memory data selector 91 is connected to another functional unit 7 via the memory data bypass 10.
Memory data R ₇ , R ₈ , to be stored in
Receive R ₉ . Then, it operates under the control of the signals BY ₇ , BY ₈ and BY ₉ . Details will be described later.

The instruction changer 92 is controlled by the signals BY _{7 to} BY ₉ output from the memory / address comparator 90, and changes the instruction based on the instruction code held in the register 94. Details will be described later.

The storage register 94 is used in the decoding stage 5
The instruction code OP ₆ given by the above is held. The held instruction code OP ₆ is stored in the instruction changer 92 and the selection circuit 9
7 and register 9 in the memory access stage 62
Given to 5.

When the instruction code OP ₆ is a store instruction, the selection circuit 97 outputs the data D ₃ from the register file _3.
If the instruction code OP ₆ is another instruction, the storage address D ₆ is selected and the signal R ₆ is output.

The execution stage 61 further includes a register file / address comparator 80, a storage register 81, a register file / data selector 83, and an operation executor 84.

Register file address comparator 80
Receives the storage addresses D ₇ , D ₈ and D ₉ obtained from the other functional units 7 to ₉ and the source addresses S ₁₁ and S ₁₂ included in the instruction of the functional unit 6. The source addresses S ₁₁ , S ₁₂ and the storage addresses D ₇ , D ₈ , D ₉
Selection signal S indicating the comparison result (match / mismatch)
Outputs _{17 to} S ₁₉ and S _{27 to} S ₂₉ . Details will be described later.

The storage register 81 is used in the decoding stage 5
The storage address D ₆ given from is held. The stored storage address D ₆ is provided to the address comparator 80 of another functional unit and the register 82 in the memory access stage 62.

Register file data selector 83
Register file 3 via decode stage 5
It receives _two data D ₁ and D ₂ given by In addition, the register file data selector 83 is provided with the memory data MD ₇ obtained in another functional unit.
Receive MD ₉ through data bypass 12. The register file data selector 83 receives the selection signals S _{17 to} S ₁₉ and S _{27 to} S ₂₉ supplied from the address comparator 80.
And 3 obtained in each of the other functional units 7-9
It operates in response to one signal BY ₆ . Details will be described later.

The operation executor 84 uses the data buses 31 and 3
It is connected to the register file data selector 83 via 2 and executes a predetermined operation based on the data selected by the register file data selector 83. The execution result of the operation is given to the register 85 and the memory / address comparator 90. This is an address for accessing the data memory 2.

The memory access stage 62 has a register 82 and a register 85 for holding the storage address R _6.
And a data register 86 for holding the data of the calculation result of. The write back stage 63 transfers the execution result data to the register file 3 according to the given storage address.
Write in.

An example of the register file / address comparator 80 shown in FIG. 2 is shown in FIG. The register file address comparator 80 detects a match between the source address S ₁₁ and the storage addresses D ₇ , D ₈ and D ₉ of the instructions handled in the other functional units 7 to 9 shown in FIG. 1, respectively. The detectors 811 to 813 are provided. The source address S ₁₂ and the other functional units 7 to 7 shown in FIG.
Storage address D ₇ of the instructions handled in 9, D _8, D
Match detectors 821 to 8 for respectively detecting a match with ₉
Equipped with 23.

The coincidence detectors 811 to 813 generate coincidence signals S _{17 to} S ₁₉ , respectively. Also, the coincidence detector 821
Through 823 generate coincidence signals S _{27 through} S ₂₉ , respectively. For example, the detector 811 detects a match between the storage address D ₇ and the source address S ₁₁ and generates a match signal S ₁₇ . Coincidence signal _{S 17 ~S 19, S 27 ~S} 29 , the arithmetic execution unit 8
It is given to the register file data selector 83 as a signal for selecting the data calculated in 4.

Register file data selector 83
An example is shown in FIG. The register file data selector 83 includes tristate buffers 910 to 913 having output ends connected to the data bus 31 and tristate buffers 920 to 923 having output ends connected to the data bus 32.

Tristate buffers 910 and 920
Respectively receives the data D ₁ and D ₂ given from the register file 3. Also, tri-state buffers 911 to 913, respectively receive the memory data MD ₇ to MD ₉ obtained in other functional units via a data bypass 12 shown in FIG. Similarly, the tri-state buffers 920 to 923 also have the data bypass 12
The memory data MD _{7 to} MD ₉ obtained in the other functional units are respectively received via.

Tristate buffers 910 to 913
Is a signal BY indicating that the selection signals S _{17 to} S ₁₉ given from the register file address comparator 80 and the memory data in the functional units 7 to 9 are obtained.
Controlled according to ₆ . For example, the tri-state buffer 911 applies the data MD ₇ on the data bypass 12 to the data bus 31 when the selection signal S ₁₇ is applied at a high level and the signal BY ₆ from the functional unit 7 is applied at a high level. . On the other hand, the tri-state buffer 910
Indicates that all of the selection signals S _{17 to} S ₁₉ are low, or the signal BY ₆ obtained from the functional units 7 to 9 is
Register file 3 when all indicate low levels
The data D ₁ given by the above is given to the data bus 31.
The tristate buffers 920 to 923 operate similarly.

FIG. 5 shows an example of the arithmetic execution unit 84. The operation executor 84 has registers 841 and 842 which respectively hold data obtained via the data buses 31 and 32,
It is composed of an arithmetic unit 843 that executes an arithmetic operation using the data held by the registers 841 and 842.

An example of the memory address comparator is shown in FIG. The memory / address comparator 90 is a match detector 901-
It consists of 903. The coincidence detector 901 indicates the instruction OP ₇ being processed by another functional unit 7, the write memory address M ₇ calculated by the operation executor 84 of the functional unit 7, and the instruction being processed by this functional unit 6. OP ₆ and operation executor 8 of this functional unit 6
The read address M ₆ calculated by 4 is input. The same applies to the coincidence detectors 902 and 903. That is, the instruction OP ₆ processed by the functional unit 6 and the read address M ₆ calculated by the operation executor 84 of the functional unit ₆ are input to both the coincidence detectors 902 and 903. Then, the coincidence detector 902 also receives the instruction OP ₈ being processed by the other functional unit 8 and the write memory address M ₈ calculated by the operation executor 84 of the functional unit 8. Coincidence detector 90
3 is an instruction O processed by another functional unit 9.
P ₉ and the write memory address M ₉ calculated by the operation executor 84 of the functional unit 9 are also input.

For example, the detector 910 uses the instruction code OP ₇
Is a memory write instruction and OP ₆ is a memory read instruction, write memory address M
A match between ₇ and the read address M ₆ is detected, and a match signal BY ₇ is generated. This is a signal indicating that the memory data has been obtained. The signals BY ₈ and BY ₉ are similarly obtained. The signals BY _{7 to} BY ₉ are used as signals for selecting memory data by the memory data selector 91.
It is also given to the instruction changer 92.

FIG. 7 shows an example of the memory data selector 91. The memory data selector 91 includes tristate buffers 910 to 913. The tri-state buffer 910 stores memory data (output data of the arithmetic execution unit 84) R _{7 to} R ₉ to be stored in the other functional units 7 to 9 via the memory / data bypass 10.
Receive each of. Tri-state buffer 910
～913 is controlled in accordance with signals BY ₇ ~BY ₉ provided from a memory address comparator 90.

For example, the tri-state buffer 911
Provides the data on data bypass 10 to data bypass 12 and register 86 as signal MD ₆ when signal BY ₇ is applied at a high level.

FIG. 8 shows an example of the instruction changer. The instruction changer 92 includes a register 921 that holds a register file write instruction that is a change instruction and a selection circuit 922 that is connected to the register 95. The selection circuit 922 outputs the signals BY _{7 to} BY, which are given from the instruction code memory / address comparator 90 and indicate that the memory data has been obtained.
₉ and the instruction code connected to its own register 94. The selection circuit 922 is controlled by the signals BY _{7 to} BY ₉ . That is, one of the signals BY _{7 to} BY ₉
If there is even a high level, the instruction code held in the register 921 is selected and written in the register 96.

The operation will be described with reference to FIG. In the following description, it is assumed that the superscalar processor 20 shown in FIG. 1 executes the instructions 11 to 13 described with reference to FIG. It is assumed that the pipeline PL1 corresponds to the functional unit 6, the pipeline PL2 corresponds to the functional unit 7, and the pipeline PL3 corresponds to the functional unit 8.

In the pipeline PL1, the period T ₁
Instruction fetch stage 4 of the processing of instruction 11 in
Processing IF is performed, and processing ID in the instruction decoding stage 5 is performed in the period T ₂ . Processes EXC, MEM, W in the execution stage 61, the memory access stage 62, and the write back stage 63
B is processed in the periods T ₃ , T ₄ , and T ₅ , respectively.

[0061] On the other hand, in the pipeline PL2, PL3, among the processing of instructions 11 and 12 in the period T _1, is processed IF the execution of the instruction fetch stage 4, the process EXC in the instruction decode stage 5 in the period T ₂ Done. In pipeline PL2, it is calculated memory address in the period T _3, and the memory address of the other functional units 6, 8 and 9 are compared. As a result, if the memory address calculated in the pipeline PL1 matches, the data in the pipeline PL1 is transferred to the pipeline PL2 via the memory data bypass 10.

[0062] In the pipeline PL3, but waits during the period T _3, in a period T _4, since already running data pipeline PL2 is obtained,
Data is transferred via the data bus 12 and the execute stage 62 is processed during period T ₄ .

FIG. 10 is a block diagram of the functional unit 7 shown similarly to FIG. The memory address comparator 90 of the functional unit ₇ compares its own memory address M ₇ with the memory addresses M ₆ , M ₈ and M ₉ of the other functional units 6 and 8, 9. In addition, other functional units 6,
The instruction codes OP ₆ , OP ₈ and OP ₉ of ₈ and ₉ are referred to. If these instruction code OP _6, OP _8, OP ₉ is a write command, and an address match is detected, it generates a signal _{BY 6, BY 8, BY 9} .

Further, the memory data selector 91 of the functional unit 7 is responsive to the signals BY ₆ , BY ₈ and BY ₉ to obtain the data R ₆ , R ₈ and R obtained via the memory data bus 10. ₉ is selectively applied to the register 86 as the signal MD ₇ . That is, when the memory address matches another functional unit whose instruction code is a write instruction, the data obtained from the register 81 of the functional unit is transferred to the register 86 of the functional unit 7.

That is, since the functional unit 7 can obtain the data without reading from the data memory 2, the processing EXC of the instruction 12 does not need to wait for the end of the processing WB of the instruction 11.

FIG. 11 shows the instruction changer 92 of the functional unit 7.
Shows the configuration of. The instruction changer 92 of the functional unit 7 selects the register 95 or the register 921 in response to the signals BY ₆ , BY ₈ and BY ₉ . Signals BY ₆ and B
When at least one of Y ₈ and BY ₉ has a high level, the instruction code held in the register 921 is selected and written in the register 96, so that the instruction can be changed. Therefore, it becomes unnecessary to execute useless memory access instructions.

FIG. 12 shows the configuration of the register file / address comparator 80 of the functional unit 8. Functional unit 8
Register file address comparator 80 compares the source address S _11, S ₁₂ contained in the storage address D _6, D _7, D ₉ and its own instruction of other functional units 6, 7, 9. When an address match is detected, the selection signals S ₁₆ , S ₁₇ , S ₁₉ and S ₂₆ , S ₂₇ , S ₂₉ are generated.

FIG. 13 shows the configuration of the register file data selector 83 of the functional unit 8. The register file data selector 83 of the functional unit 8 receives the memory data from the selection signals S ₁₆ , S ₁₇ , S ₁₉ and S ₂₆ , S ₂₇ , S ₂₉ , and the other functional units 6, 7, and 9. In response to the obtained signal BY ₈ , the memory data MD ₆ , MD ₇ , MD ₉ obtained in the other functional units 6, 7, 9 on the data bypass 12 are applied to the data bus 31.

That is, the data selection signals S ₁₆ , S ₁₇ , S
_{When 19} and S ₂₆ , S ₂₇ , S ₂₉ are given at a high level and the signals BY ₆ , BY ₇ , BY ₉ are given at a high level, the data MD on the data bypass 12 is responded according to the signals. ₆ , MD ₇ , MD ₉ are supplied to the data buses 31 to 32.

Therefore, the data of the other functional units 6, 7, 9 are transferred to the functional unit 8. That is, since the functional unit 8 can obtain the data without waiting for the data to be written in the register file 3, the process ID of the instruction 13 does not need to wait for the end of the process WB of the instruction 12.

As described above, the instructions 12 and 13 are waiting
The time can be shortened. That is, as shown in FIG.
Sea urchin, period T₃Of the pipeline PL1 at the end of
Data through the memory / data bus 10 through the pipeline PL
Given to 2, so the period T _FourInstruction without stopping at
12 can be processed continuously. Also, a memory read instruction
Will not be executed.

[0072] Further, since the data applied to the pipe line PL2 is supplied to a pipe line PL3 via the data bus 12, execution stage in the period T ₄ (EX
C) can be processed.

[0073]

As described above, according to the present invention, the address match is detected, and the memory write data of another pipeline is directly applied to another pipeline before being written in the memory. The time required for execution can be shortened.

Further, the memory access can be reduced by stopping the execution of the unnecessary memory read instruction.

Furthermore, since the data which should be obtained by the memory read instruction obtained by the above means is directly given to another pipeline, the time required for executing the instruction can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a functional unit 6.

FIG. 3 is a configuration diagram of a register file / address comparator of a functional unit 6.

[Fig. 4] Register file data of functional unit 6
It is a block diagram of a selector.

FIG. 5 is a configuration diagram of an arithmetic execution unit.

FIG. 6 is a configuration diagram of a memory / address comparator.

FIG. 7 is a configuration diagram of a memory data selector.

FIG. 8 is a configuration diagram of an instruction changer.

FIG. 9 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 10 is a configuration diagram of a functional unit 7.

11 is a configuration diagram of an instruction changer of the functional unit 7. FIG.

12 is a configuration diagram of a register file / address comparator of the functional unit 8. FIG.

13 is a configuration diagram of a register file data selector of the functional unit 8. FIG.

FIG. 14 is a block diagram showing a conventional technique.

FIG. 15 is a timing diagram showing a conventional technique.

FIG. 16 is a timing diagram showing a conventional technique.

FIG. 17 is a timing diagram showing a conventional technique.

[Explanation of symbols]

 5 instruction decode stage 10 memory data bypass 12 data bypass 80 register file address comparator 83 register file data selector 90 memory address comparator 91 memory data selector 92 instruction modifier

Claims (4)

[Claims] 1. A plurality of pipeline processing execution means, a plurality of given instructions are fetched, a predetermined instruction that can be simultaneously executed is found from the plurality of fetched instructions, and the pipeline processing execution means is provided. An instruction giving means for inputting the predetermined instruction, a temporary data storage means for holding the data for a relatively short period during the processing of the predetermined instruction, an external memory for holding the data for a relatively long term, and the pipeline processing execution A data bypass bus for transmitting data handled by the means, and each of the pipeline processing execution means includes the data bypass bus.
A parallel computer having bypass control means for determining whether to use the data transmitted by the bypass bus. 2. The bypass control means in the one pipeline processing execution means, the memory address of the external memory obtained in one of the predetermined instructions corresponding to the one pipeline processing execution means, and the like. External memory address coincidence detecting means for detecting coincidence with the memory address of the external memory obtained in the other predetermined instruction corresponding to the pipeline processing executing means, and according to the output of the external memory address coincidence detecting means. ,
The parallel computer according to claim 1, further comprising a first data providing unit that selects whether to use the data transmitted by the data bypass bus or the data separately loaded from the external memory. 3. The external memory address coincidence detection means outputs a coincidence signal indicating whether or not data is bypassed, and when the coincidence signal indicates coincidence, the one predetermined instruction is bypassed. The parallel computer according to claim 2, further comprising an instruction changing unit that changes the data into an instruction to store the data in the temporary data storage unit. 4. The bypass control means in the one pipeline processing execution means, the address of the temporary data storage means obtained in the one predetermined instruction corresponding to the one pipeline processing execution means, Temporary data storage means address coincidence detection means for detecting coincidence with the address of the temporary data storage means obtained in the other predetermined instruction corresponding to the other pipeline processing execution means, and the other pipeline processing Second data providing means for selecting whether to use the data transmitted by the data bypass bus according to the output of the external memory address coincidence detecting means of the executing means and the output of the temporary data storing means address coincidence detecting means. And further comprising:
The described parallel computer.