JPH06133281A - Picture signal processing unit - Google Patents

Abstract

PURPOSE:To avoid deterioration in vertical resolution by eliminating disturbance of dual image. CONSTITUTION:An interlace scanning frame picture signal of 60 fields.30 frames/sec from an input terminal 11 is converted into a sequential scanning frame picture signal B by a sequential scanning frame configuration circuit 12. A motion vector detection circuit 15 detects a motion vector between a current sequence scanning frame and a onepreceding frame sequential scanning frame from a frame memory 13. Then motion vector correction circuits 16, 17 reconstitute a sequential scanning frame picture before 1/60sec, an adder 18 and a divider 19 average the picture and the result is sent to a changeover switch 20 and the result is alternately selected with a frame delay signal from a frame memory 14 for each field period to obtain a sequential scanning frame picture signal of 60 fields.60 frames/sec.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus used for converting signals of so-called CG (computer graphics) images and animation images into ordinary television signals.

[0002]

2. Description of the Related Art Generally, so-called CG (computer graphics) images and animation images are made at a rate of 30 screens per second, that is, 30 frames / second.

When converting this into a general (for example, NTSC system) television signal, in a normal case, for example, an odd line of one screen (one frame) of the CG image is set as the first field of the television image. , The even lines are assigned to the second field of the television image.

[0004]

That is, according to the above-mentioned conventional method, a signal of an image of 30 fields and 30 frames / sec formed by sequential scanning such as a CG image or an animation image is interlaced to 60. Field-30
It will be assigned to the television signal of frames / second.

For this reason, in the converted television signal, so-called double image interference may occur in the moving image portion, and the vertical resolution is deteriorated compared to the vertical resolution of the progressive scan image before conversion. There is.

The present invention has been made in view of the above circumstances, and interlaced scanning obtained by converting a progressive scanning frame image signal of 30 fields / 30 frames / second such as a CG image or an animation image. It is an object of the present invention to provide an image signal processing device capable of removing double image interference of a television signal of 60 fields and 30 frames / sec, and without deterioration of vertical resolution.

[0007]

According to the image signal processing apparatus of the present invention, an image signal converted from 30 fields / 30 frames / sec of progressive scanning to 60 fields / 30 frames / sec of interlaced scanning is obtained. A progressive scan conversion means for forming a progressive scan frame image signal based on the above, and a motion vector between the progressive scan frame image signal of the current frame and the progressive scan frame image signal of the preceding frame output from the progressive scan conversion means. And a motion vector detecting means for detecting the motion vector, and performing motion correction on the progressive scanning frame image signal of the current frame based on the motion vector, and performing the first sequential scanning 1/60 seconds before the current progressive scanning frame. First motion correction means for forming a frame image signal, and the progressive scanning frame image of the preceding frame based on the motion vector By applying motion compensation to the item, a second pre 1/60 seconds for progressive scan frames of said present frame
Second motion correction means for forming a progressive scanning frame image signal of, and an image signal synthesizing means for forming an image signal of 60 fields / 60 frames / second based on the first and second progressive scanning frame image signals. By having
The above problems are solved.

The image signal synthesizing means adds the first and second progressive scanning frame image signals, a divider for controlling the gain of the output of the adding means, and a divider. It is preferable to have a configuration having a selection means for selecting an output and an output of the progressive scan conversion means delayed by a predetermined time. Further, conversion means for converting the progressive scanning frame image signal formed by the progressive scanning conversion means into an interlaced scanning frame image signal is provided, or the 60 field / 60 frame / second image formed by the image signal synthesizing means. Signal 60
It is preferable to provide a converting means for converting an image signal of 30 frames / second in the field.

[0009]

Since the motion vector correction is applied to the progressive scanning frame image signal and the frame images are obtained at the interval of 1/60 seconds, the double image interference in the moving image part of the CG image or the animation image can be removed, and the CG image can be removed. Also, it is possible to prevent deterioration of the vertical resolution of an animation image and to display a high quality image. Also, 60 fields obtained in this way
By converting an image signal of 60 frames / second into an image signal of 60 fields / 30 frames / second, a high quality image can be obtained even with a normal television receiver.

[0010]

1 is a block circuit diagram showing a schematic configuration of a first embodiment of an image signal processing apparatus according to the present invention. A concrete example of signals at respective parts A to J in FIG. 2 A to J
Are shown in each.

In FIGS. 1 and 2, an input terminal 11 is supplied with a general (for example, NTSC system) television signal A. This television input signal A
For example, a 30-field / 30-frame / sec image created by sequential scanning, such as a CG (computer graphics) image signal or an animation image signal, is converted to an interlaced-scan 60-field / 30 frame / sec image. The signal obtained by the above is used. Here, the symbols S _no , S _ne, etc. in the signal A of FIG. 2 indicate the image component of the odd field of the nth field and the image component of the even field. Input terminal 1
In addition to the signals of the CG image and the animation image as described above, 1 may be supplied with a normal video signal of 60 fields and 30 frames / sec.

The 60 field / 30 frame / sec television input signal A supplied to the input terminal 11 is sent to the progressive scan conversion means or the progressive scan frame forming circuit 12. The progressive scanning frame composing circuit 12 composes a progressive scanning frame image by using the signal of the current field and the signal of the previous field of the inputted television signal of 60 fields · 30 frames / sec, and the progressive scanning frame is formed. The image signal B is output. Symbol S in signal B of FIG.
_n indicates the frame image component of the nth frame.

The progressive scan frame image signal B output from the progressive scan frame configuration circuit 12 is sent to the series connection circuit of the frame memories 13 and 14 and also to the vector detection circuit 15. These frame memories 1
The output signals from 3 and 14 are like signals C and D because the progressive scanning frame signal B is sequentially delayed by one frame. That is, the frame memory 1
The progressive scan frame image signal B input to
In the case of the frame image component S _n of the frame, the output signal C from the frame memory 13 becomes the component S _{n-1 of the (n-1) th} frame, and the output signal D from the frame memory 14 becomes the component of the (n-2) th frame. It becomes the component S _n-2 .

The output signal C from the frame memory 13 is also sent to the vector detection circuit 15, and the vector detection circuit 15 receives the progressive scan frame image signal B of the current frame from the progressive scan frame composing circuit 12. A motion vector with respect to the progressive scanning frame image signal C one frame before stored in the frame memory 13 is detected. That is, the motion vector V _(n between the progressive scan frame image signal components S _n-1 of the (n-1) th frame of the output signal C from the n-th frame of the frame image component S _n and the frame memory 13 B _{-1) -n} is detected and the vector detection signal E of FIG. 2 is output. An example of this motion detection algorithm is a block matching method.

The output signal C from the frame memory 13 is sent to the vector correction circuit 16, and the output signal D from the frame memory 14 is sent to the vector correction circuit 17. An information signal (vector detection output signal) E of the motion vector detected by the vector detection circuit 15 is supplied to these vector correction circuits 16 and 17. The vector correction circuit 16 stores the 1 stored in the frame memory 13.
The motion vector (signal E) detected by the vector detection circuit 15 for the progressive scanning frame image signal B before the frame
Is used to reconstruct the progressive scan frame image signal of 1/60 second. Similarly, the vector correction circuit 17 also uses the motion vector (signal E) detected by the vector detection circuit 15 for the progressive scanning frame image signal D of two frames before held in the frame memory 14, and also 1/60 Reconstruct the progressive scan frame image signal of seconds before. That is, for example, using the motion vector V _1-2 of the signal E for the second frame image component S ₂ of the signal C, the frame image component (S ₁₂ ) ′ between the first frame and the second frame is reconstructed. The first frame image component S ₁ of the signal D and the motion vector V _1-2 of the signal E is used for the first frame and the second frame.
It is not to reconstruct a frame image component (S ₁₂₎ "between frame.

In this way, the vector correction circuits 16 and 1
The 1/60 second preceding progressive scan frame image signals respectively obtained from 7 are sent to the adder 18 to be added, and the divider 1
By controlling the gain at 9,
The progressive scanning frame image signal F 60 seconds before is obtained. The division coefficient of the divider 19 may be 2, for example. In the case of the specific example, the aforementioned frame image component in the output signal from the vector correction circuit 16 (S ₁₂₎ ', and the frame image component in the output signal from the vector correction circuit 17 (S ₁₂₎ " The frame image component S ₁₂ in the split calculation force signal F is obtained by adding and dividing by 2 (taking the average).
0 to the selected terminal b.

The change-over switch 20 has three selected terminals a, b, c, and the change-over is controlled by a change-over signal I from the CG / animation detecting circuit 21. The field delay output signal G from the frame memory 14 is supplied to the selected terminal a of the changeover switch 20, and the interlaced scanning frame image signal H from the interlaced scanning frame configuration circuit 22 is supplied to the selected terminal c. Frame memory 1
The field delayed output signal G from 4 is a signal obtained by delaying the signal C, which is an input signal to the frame memory 14, by one field. Interlaced scanning frame configuration circuit 2
Reference numeral 2 denotes a progressive scanning frame composing circuit 12 which is the progressive scanning conversion means when the input signal A to the input terminal 11 is not an image signal based on the CG image or the animation image.
For converting the progressive scanning frame image signal formed by the interlaced scanning frame image signal, that is, converting one frame image into a signal for displaying an odd field image and an even field image, and outputting the signal. Actually, the sequential scanning frame image signal C from the frame memory 13 is converted into the interlaced scanning frame image signal H for timing adjustment, and the changeover switch 2
0 to the selected terminal c.

Here, when the input signal A is an image signal based on the CG image or animation image, CG.
As shown by I in FIG. 2, the animation detection circuit 21 sends a changeover signal to the changeover switch 20 so as to alternately change the selected terminals a and b every field cycle. As a result, the changeover switch 20 outputs a signal as indicated by J in FIG. This output signal J is an image signal of 60 fields and 60 frames / second, and is output terminal 2
It is taken out via 3.

Therefore, 1/60 is obtained by motion vector correction.
Since new frames are created at intervals of a second (field period), it is possible to remove double image interference in the moving image portion. In addition, the vertical resolution of a CG image or an animation image that is originally a sequentially scanned image need not be degraded. That is, an image signal based on a CG image or an animation image can be displayed with high image quality.

When the input signal A is not an image signal based on the CG image or animation image, CG.
The animation detection circuit 21 outputs a switching control signal for switching and connecting the changeover switch 20 to the selected terminal c. Therefore, at this time, the changeover switch 20 selects the interlaced scanning frame image signal H from the interlaced scanning frame configuration circuit 22, and the interlaced scanning frame image signal H is taken out through the output terminal 23.

Next, FIG. 3 is a block circuit diagram showing a schematic configuration of a second embodiment of the image signal processing apparatus according to the present invention. Concrete examples of signals at respective parts A to J in FIG. These are shown in A to J of FIG. 4, respectively.

In FIG. 3, parts corresponding to the respective parts in FIG. 1 are designated by the same reference numerals, and the structure and operation of these parts are the same as in the description of FIG. 1 described above. Only the essential parts will be described below, with simplification or omission. The symbols S _1o in the signals A to J in FIG.
S ₁ , V _0-1, etc. have the same meanings as the symbols S _1o , S ₁ , V _0-1, etc. in the signals A to J of FIG. 2 described above.

The progressive scan frame construction circuit 12 reconstructs a progressive scan frame image using the current field and the previous field of the input television image signal A.
The motion vector detection circuit 15 detects a motion vector between the current progressive scan frame and the previous progressive scan frame held in the frame memory 13. As a motion vector detection algorithm, a block matching method or the like can be considered.

The vector correction circuit 16 uses the vector detected by the motion vector detection circuit 15 for the sequential scanning frame of one frame before stored in the frame memory 13 and outputs the sequential scanning frame image of 1/60 second before. Reconfigure. Similarly, the vector correction circuit 17 uses the vector detected by the motion vector detection circuit 15 with respect to the sequential scanning frame two frames before stored in the frame memory 14 to obtain the sequential scanning frame image 1/60 second before. Reconstruct. The reconstructed two 1/60 second sequential scanning frames are added by the adder 18 and gain-controlled by the divider 19. The division coefficient is 2.

The signals A to G in FIG. 4 corresponding to the above-mentioned respective components are the same as the above signals A to G in FIG.

Next, the changeover switch 30 has two terminals a and b to be selected, and the changeover is controlled by the changeover control signal H from the timing generation circuit 31. As shown in FIG. 4, the switching control signal H is a signal that alternately switches the selected terminals a and b in units of the field cycle (1/60 seconds). Therefore, the changeover switch 30 switches between the motion vector-corrected frame image from the divider 19 and the motion vector-uncorrected frame image which is the field delay output from the frame memory 14, and is indicated by I in FIG. Like 6
Outputs a progressive scanning frame image signal of 0 fields and 60 frames / sec.

Next, the interlaced scanning frame construction circuit 32
Is the field 60 of the output signal I of the changeover switch.
A 60-field / 30-frame / second interlaced scanning frame is reconstructed from a 0-frame / second progressive-scanning frame, and a signal as indicated by J in FIG. 4 is sent to the output terminal 33.
The interlaced scanning frame configuration circuit 32 creates an odd field image component S _0o from one frame image component of the output signal I from the changeover switch 30, for example, S ₀ , and the next frame image component, for example, S _01. From the even field image component S _01e .

According to the second embodiment, since new frames are created at 1/60 second intervals by motion vector correction and then interlaced scanning images of 60 fields / 30 frames / second are obtained, the moving image portion is obtained. It is possible to eliminate the double image interference of. As a result, the CG image and the animation image can be displayed with high image quality. Further, since an image signal of 60 fields and 30 frames / second, which is the same as a normal television signal, can be obtained, it can be monitored by a standard television receiver for general household use.

Next, a third embodiment of the image signal processing apparatus according to the present invention will be described with reference to FIGS. Here, FIG. 5 shows processing blocks on the transmitting side, and FIG. 6 shows processing blocks on the image receiving side.
7A to 7E, and E to K in FIG.
Specific examples of the signals of the respective parts are shown in E to K of FIG. Here, the output signal E on the transmitting side is the input signal E on the image receiving side.
Is the same as. Further, FIG. 7, the symbol S _1o in each signal A~K in FIG 8, S _1, V _0-1, etc., the symbol S _1o in each signal A~J of Figure 2 described above, S _1, V ₀ It has the same meaning as _-1 mag.

First, in FIG. 5, an input signal A of 60 fields and 30 frames input from the input terminal 51 is
It is sent to the progressive scan frame configuration circuit 52. The progressive scan frame configuration circuit 52 reconstructs a progressive scan frame image using the current field and the previous field of the input signal A, and outputs the progressive scan frame image signal B to the frame memory 5.
3 and the motion vector detection circuit 54, respectively.

The motion vector detecting circuit 54 receives the progressive scan frame image signal B from the progressive scan frame composing circuit 52.
Inside the current progressive scan frame and the progressive scan frame image signal C delayed by one frame from the frame memory 53.
The motion vector between the preceding frame and the preceding progressive scanning frame is detected. A block matching method or the like is used for the motion vector detection algorithm.

In the adder 55 for multiplexing the motion vector information with the image signal, the motion vector from the motion vector detecting circuit 54 is added, for example, in the vertical blanking period in the progressive scanning frame image signal C from the frame memory 53. Information signals are multiplexed and sent to the buffer memory 56. The buffer memory 56 returns the signal subjected to the double speed processing to the normal rate and outputs the output signal as shown in E of FIG. That is, this buffer memory output signal E
Is a progressive scanning signal representing one frame image in 1/30 seconds.

Next, in the image receiving side processing block of FIG.
The output signal E from the buffer memory 56 of the processing block on the transmission side of FIG. 5 is input to the input terminal 61.
The input signal E is sent to the buffer memory 62 and converted into a signal F having a double data rate as usual. The buffer memory output signal F is sent to the frame memory 63 and the motion vector separation circuit 64, respectively.

The motion vector separation circuit 64 separates or detects the information signal of the motion vector multiplexed in the vertical blanking period or the like as described above, and sends it to the motion vector correction circuits 65 and 66, respectively.

The vector correction circuit 65 uses the motion vector obtained from the motion vector separation circuit 64 for the previous scanning frame in the progressive scanning frame image signal G delayed by one frame in the frame memory 63. Then, the progressive scan frame image 1/60 seconds before is reconstructed. Similarly, the vector correction circuit 66 uses the motion vector obtained from the motion vector separation circuit 64 for the current progressive scan frame in the buffer memory output signal F to obtain a progressive scan frame image 1/60 second before. Reconstruct.

The two reconstructed 1/60 second progressive scan frame images are added by the adder 67 and the divider 6
The gain is controlled in 8 to become the signal H. In addition,
The division coefficient of the divider 68 is 2. The divider output signal H is sent to the selected terminal b of the changeover switch 69. The field delayed output signal I from the frame memory 63 is supplied to the selected terminal a of the changeover switch 69. This changeover switch 69 is used for the timing generation circuit 7
Switching control is performed by the switching control signal J made of 0, and the frame image transmitted (field delay output signal I from the frame memory 63) and the frame image obtained by vector correction using the motion vector And the output signal K is output from the output terminal 71.

Also in the third embodiment, since new frames are created at 1/60 second intervals by motion vector correction, a 60-field / 60-frame / sequentially scanned image is obtained as a result, and a moving image part is displayed. Double image interference can be removed, deterioration of vertical resolution of a CG image or an animation image that is originally a sequentially scanned image can be prevented, and an image signal based on the CG image or the animation image can be displayed with high image quality.

The present invention is not limited to the above embodiment, and instead of the changeover switch 69 having the two selected terminals a and b of the third embodiment, for example,
By using the changeover switch 20 having the three selected terminals a, b, and c as shown in FIG. 1, the interlaced scanning is performed by the CG / animation detection circuit 21 or the like in the case of a television signal other than CG / animation. It may be configured to output a frame configuration signal. Although the above embodiments have been described with reference to a television signal of 60 fields and 30 frames / sec as a reference, the present invention can be easily applied to a television signal of 50 fields and 25 frames / sec. is there. Besides, various modifications can be made without departing from the scope of the present invention.

[0039]

As is apparent from the above description, according to the image signal processing apparatus of the present invention, conversion from 30 fields / 30 frames / sec for progressive scanning to 60 fields / 30 frames / sec for interlaced scanning is performed. A frame image signal for progressive scanning is formed based on the image signal thus generated, and a motion vector between the progressive scanning frame image signal of the current frame of this signal and the progressive scanning frame image signal of one frame before is detected, and this motion is detected. Motion correction is applied to the progressive scanning frame image signal of the current frame based on the vector to form a progressive scanning frame image signal 1/60 second before the current progressive scanning frame. Double image interference in the case of an image can be removed, and a high quality image can be displayed without deteriorating the vertical resolution.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a first embodiment of an image signal processing device according to the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

FIG. 3 is a block circuit diagram showing a schematic configuration of a second embodiment of the image signal processing device according to the present invention.

FIG. 4 is a time chart for explaining the operation of the second embodiment.

FIG. 5 is a block circuit diagram showing a schematic configuration of a transmission side processing block of a third embodiment of the image signal processing apparatus according to the present invention.

FIG. 6 is a block circuit diagram showing a schematic configuration of an image receiving side processing block of a third embodiment of the image signal processing apparatus according to the present invention.

FIG. 7 is a time chart for explaining the operation of the transmission side processing block of the third embodiment.

FIG. 8 is a time chart for explaining the operation of the image receiving side processing block of the third embodiment.

[Explanation of symbols]

 12 ... Sequential scanning frame configuration circuit 13, 14 ... Frame memory 15 ... Motion vector detection circuit 16, 17 ... Motion vector correction circuit 18 ... Addition Device 19: Divider 20, 30 ... Changeover switch 21 ... CG / animation detection circuit 22, 32 ... Interlaced scanning frame configuration circuit 31. Timing Generator circuit

Claims (9)

[Claims] 1. A progressive scan conversion means for forming a progressive scan frame image signal based on an image signal converted from progressive scan 30 fields / 30 frames / sec to interlace scan 60 fields / 30 frames / sec. Motion vector detecting means for detecting a motion vector between the progressive scan frame image signal of the current frame and the progressive scan frame image signal of the preceding frame output from the progressive scan converting means, and the motion vector detecting means based on the motion vector. First motion correction means for performing motion correction on the progressive scan frame image signal of the frame to form a first progressive scan frame image signal 1/60 second before the current progressive scan frame; On the basis of the above, motion correction is applied to the progressive scanning frame image signal of the preceding frame to obtain the progressive scanning frame of the current frame. Second motion correction means for forming a second progressive scanning frame image signal 1/60 seconds before the frame, and 60 fields / 60 frames / frame based on the first and second sequential scanning frame image signals. An image signal processing device, comprising: an image signal synthesizing unit for forming an image signal of second. 2. The image signal synthesizing means, adding means for adding the first and second progressive scanning frame image signals, a divider for gain control of the output of the adding means, and an output of the divider. 2. The image signal processing apparatus according to claim 1, further comprising: selecting means for selecting an output of the progressive scan converting means delayed by a predetermined time. 3. The image signal processing apparatus according to claim 1, further comprising conversion means for converting the progressive scanning frame image signal formed by the progressive scanning converting means into an interlaced scanning frame image signal. 4. A conversion means for converting the 60 field / 60 frame / second image signal formed by the image signal combining means into a 60 field / 30 frame / second image signal. The image signal processing device according to 1 or 2. 5. A progressive scan frame image signal formed based on an image signal converted from progressive scan 30 fields / 30 frames / sec to interlace scan 60 fields / 30 frames / sec. An image signal formed by multiplexing the information signal of the motion vector between the image of the current frame of the signal and the image one frame before is input, and vector separation means for separating the motion vector from the input image signal, Motion correction is applied to the image of the current frame of the progressive scan frame image signal based on the separated motion vector to form a first progressive scan frame image signal 1/60 second before the current progressive scan frame. First motion correction means for performing motion correction on the image one frame before the progressive scanning frame image signal based on the motion vector. Second motion correction means for forming a second progressive scan frame image signal 1/60 second before the progressive scan frame of the current frame, and the first and second progressive scan frame image signals And an image signal synthesizing means for forming an image signal of 60 fields and 60 frames / second based on the above. 6. The image signal synthesizing means adds means for adding the first and second progressive scanning frame image signals, a divider for gain control of the output of the adding means, and an output of the divider. 6. An image signal processing apparatus according to claim 5, further comprising: selecting means for selecting an output of the progressive scan converting means delayed by a predetermined time. 7. The image signal processing apparatus according to claim 5, further comprising conversion means for converting the input progressive scanning frame image signal into an interlaced scanning frame image signal. 8. A conversion means for converting the image signal of 60 fields.60 frames / second formed by the image signal combining means into an image signal of 60 fields.30 frames / second. 5. The image signal processing device according to 5 or 6. 9. The motion vector information in the input image signal is multiplexed in a vertical blanking period of the progressive scan frame image signal.
The image signal processing device described.